diff options
| -rw-r--r-- | src/arch/hsail/gpu_isa.hh | 1 | ||||
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 4 | ||||
| -rw-r--r-- | src/cpu/checker/cpu.hh | 135 | ||||
| -rw-r--r-- | src/cpu/checker/thread_context.hh | 89 | ||||
| -rw-r--r-- | src/cpu/exec_context.hh | 29 | ||||
| -rw-r--r-- | src/cpu/kvm/x86_cpu.cc | 14 | ||||
| -rw-r--r-- | src/cpu/minor/exec_context.hh | 36 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.cc | 24 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.hh | 26 | ||||
| -rw-r--r-- | src/cpu/o3/dyn_inst.hh | 43 | ||||
| -rw-r--r-- | src/cpu/o3/regfile.hh | 57 | ||||
| -rw-r--r-- | src/cpu/o3/thread_context.hh | 65 | ||||
| -rw-r--r-- | src/cpu/o3/thread_context_impl.hh | 12 | ||||
| -rw-r--r-- | src/cpu/simple/exec_context.hh | 127 | ||||
| -rw-r--r-- | src/cpu/simple_thread.hh | 79 | ||||
| -rw-r--r-- | src/cpu/thread_context.cc | 20 | ||||
| -rw-r--r-- | src/cpu/thread_context.hh | 56 | ||||
| -rw-r--r-- | src/dev/arm/generic_timer.cc | 10 | ||||
| -rw-r--r-- | src/dev/arm/generic_timer.hh | 8 | ||||
| -rw-r--r-- | src/gpu-compute/gpu_exec_context.cc | 4 | ||||
| -rw-r--r-- | src/gpu-compute/gpu_exec_context.hh | 5 | ||||
| -rw-r--r-- | src/gpu-compute/gpu_tlb.cc | 4 | ||||
| -rw-r--r-- | src/sim/process.cc | 4 | ||||
| -rw-r--r-- | src/sim/process.hh | 9 | ||||
| -rw-r--r-- | src/sim/syscall_desc.cc | 2 | ||||
| -rw-r--r-- | src/sim/syscall_emul.hh | 4 |
26 files changed, 478 insertions, 389 deletions
diff --git a/src/arch/hsail/gpu_isa.hh b/src/arch/hsail/gpu_isa.hh index 425522a48..fa2cde3b1 100644 --- a/src/arch/hsail/gpu_isa.hh +++ b/src/arch/hsail/gpu_isa.hh @@ -40,6 +40,7 @@ #include "arch/hsail/gpu_types.hh" #include "base/logging.hh" +#include "base/types.hh" #include "gpu-compute/misc.hh" namespace HsailISA diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index ae2911c2d..c2a14089a 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -649,7 +649,7 @@ class BaseDynInst : public ExecContext, public RefCounted /** @} */ /** Records an integer register being set to a value. */ - void setIntRegOperand(const StaticInst *si, int idx, IntReg val) + void setIntRegOperand(const StaticInst *si, int idx, RegVal val) { setScalarResult(val); } @@ -669,7 +669,7 @@ class BaseDynInst : public ExecContext, public RefCounted /** Records an fp register being set to an integer value. */ void - setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) + setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) { setScalarResult(val); } diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 5673641aa..2c7e022bd 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -88,9 +88,6 @@ class CheckerCPU : public BaseCPU, public ExecContext { protected: typedef TheISA::MachInst MachInst; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscReg MiscReg; using VecRegContainer = TheISA::VecRegContainer; /** id attached to all issued requests */ @@ -189,15 +186,16 @@ class CheckerCPU : public BaseCPU, public ExecContext // storage (which is pretty hard to imagine they would have reason // to do). - IntReg readIntRegOperand(const StaticInst *si, int idx) override + RegVal + readIntRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); assert(reg.isIntReg()); return thread->readIntReg(reg.index()); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, - int idx) override + RegVal + readFloatRegOperandBits(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); @@ -207,8 +205,8 @@ class CheckerCPU : public BaseCPU, public ExecContext /** * Read source vector register operand. */ - const VecRegContainer& readVecRegOperand(const StaticInst *si, - int idx) const override + const VecRegContainer & + readVecRegOperand(const StaticInst *si, int idx) const override { const RegId& reg = si->srcRegIdx(idx); assert(reg.isVecReg()); @@ -218,8 +216,8 @@ class CheckerCPU : public BaseCPU, public ExecContext /** * Read destination vector register operand for modification. */ - VecRegContainer& getWritableVecRegOperand(const StaticInst *si, - int idx) override + VecRegContainer & + getWritableVecRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isVecReg()); @@ -230,8 +228,7 @@ class CheckerCPU : public BaseCPU, public ExecContext /** @{ */ /** Reads source vector 8bit operand. */ virtual ConstVecLane8 - readVec8BitLaneOperand(const StaticInst *si, int idx) const - override + readVec8BitLaneOperand(const StaticInst *si, int idx) const override { const RegId& reg = si->destRegIdx(idx); assert(reg.isVecReg()); @@ -240,8 +237,7 @@ class CheckerCPU : public BaseCPU, public ExecContext /** Reads source vector 16bit operand. */ virtual ConstVecLane16 - readVec16BitLaneOperand(const StaticInst *si, int idx) const - override + readVec16BitLaneOperand(const StaticInst *si, int idx) const override { const RegId& reg = si->destRegIdx(idx); assert(reg.isVecReg()); @@ -250,8 +246,7 @@ class CheckerCPU : public BaseCPU, public ExecContext /** Reads source vector 32bit operand. */ virtual ConstVecLane32 - readVec32BitLaneOperand(const StaticInst *si, int idx) const - override + readVec32BitLaneOperand(const StaticInst *si, int idx) const override { const RegId& reg = si->destRegIdx(idx); assert(reg.isVecReg()); @@ -260,8 +255,7 @@ class CheckerCPU : public BaseCPU, public ExecContext /** Reads source vector 64bit operand. */ virtual ConstVecLane64 - readVec64BitLaneOperand(const StaticInst *si, int idx) const - override + readVec64BitLaneOperand(const StaticInst *si, int idx) const override { const RegId& reg = si->destRegIdx(idx); assert(reg.isVecReg()); @@ -303,13 +297,15 @@ class CheckerCPU : public BaseCPU, public ExecContext } /** @} */ - VecElem readVecElemOperand(const StaticInst *si, int idx) const override + VecElem + readVecElemOperand(const StaticInst *si, int idx) const override { const RegId& reg = si->srcRegIdx(idx); return thread->readVecElem(reg); } - CCReg readCCRegOperand(const StaticInst *si, int idx) override + CCReg + readCCRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); assert(reg.isCCReg()); @@ -317,28 +313,31 @@ class CheckerCPU : public BaseCPU, public ExecContext } template<typename T> - void setScalarResult(T&& t) + void + setScalarResult(T&& t) { result.push(InstResult(std::forward<T>(t), - InstResult::ResultType::Scalar)); + InstResult::ResultType::Scalar)); } template<typename T> - void setVecResult(T&& t) + void + setVecResult(T&& t) { result.push(InstResult(std::forward<T>(t), - InstResult::ResultType::VecReg)); + InstResult::ResultType::VecReg)); } template<typename T> - void setVecElemResult(T&& t) + void + setVecElemResult(T&& t) { result.push(InstResult(std::forward<T>(t), - InstResult::ResultType::VecElem)); + InstResult::ResultType::VecElem)); } - void setIntRegOperand(const StaticInst *si, int idx, - IntReg val) override + void + setIntRegOperand(const StaticInst *si, int idx, RegVal val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isIntReg()); @@ -346,8 +345,8 @@ class CheckerCPU : public BaseCPU, public ExecContext setScalarResult(val); } - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) override + void + setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); @@ -355,7 +354,8 @@ class CheckerCPU : public BaseCPU, public ExecContext setScalarResult(val); } - void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override + void + setCCRegOperand(const StaticInst *si, int idx, CCReg val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isCCReg()); @@ -363,8 +363,9 @@ class CheckerCPU : public BaseCPU, public ExecContext setScalarResult((uint64_t)val); } - void setVecRegOperand(const StaticInst *si, int idx, - const VecRegContainer& val) override + void + setVecRegOperand(const StaticInst *si, int idx, + const VecRegContainer& val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isVecReg()); @@ -372,8 +373,9 @@ class CheckerCPU : public BaseCPU, public ExecContext setVecResult(val); } - void setVecElemOperand(const StaticInst *si, int idx, - const VecElem val) override + void + setVecElemOperand(const StaticInst *si, int idx, + const VecElem val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isVecElem()); @@ -383,13 +385,15 @@ class CheckerCPU : public BaseCPU, public ExecContext bool readPredicate() const override { return thread->readPredicate(); } - void setPredicate(bool val) override + void + setPredicate(bool val) override { thread->setPredicate(val); } TheISA::PCState pcState() const override { return thread->pcState(); } - void pcState(const TheISA::PCState &val) override + void + pcState(const TheISA::PCState &val) override { DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", val, thread->pcState()); @@ -400,39 +404,47 @@ class CheckerCPU : public BaseCPU, public ExecContext MicroPC microPC() { return thread->microPC(); } ////////////////////////////////////////// - MiscReg readMiscRegNoEffect(int misc_reg) const + RegVal + readMiscRegNoEffect(int misc_reg) const { return thread->readMiscRegNoEffect(misc_reg); } - MiscReg readMiscReg(int misc_reg) override + RegVal + readMiscReg(int misc_reg) override { return thread->readMiscReg(misc_reg); } - void setMiscRegNoEffect(int misc_reg, const MiscReg &val) + void + setMiscRegNoEffect(int misc_reg, const RegVal &val) { - DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); + DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", + misc_reg); miscRegIdxs.push(misc_reg); return thread->setMiscRegNoEffect(misc_reg, val); } - void setMiscReg(int misc_reg, const MiscReg &val) override + void + setMiscReg(int misc_reg, const RegVal &val) override { - DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); + DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", + misc_reg); miscRegIdxs.push(misc_reg); return thread->setMiscReg(misc_reg, val); } - MiscReg readMiscRegOperand(const StaticInst *si, int idx) override + RegVal + readMiscRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); assert(reg.isMiscReg()); return thread->readMiscReg(reg.index()); } - void setMiscRegOperand(const StaticInst *si, int idx, - const MiscReg &val) override + void + setMiscRegOperand(const StaticInst *si, int idx, + const RegVal &val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isMiscReg()); @@ -440,14 +452,15 @@ class CheckerCPU : public BaseCPU, public ExecContext } #if THE_ISA == MIPS_ISA - MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override + RegVal + readRegOtherThread(const RegId &misc_reg, ThreadID tid) override { panic("MIPS MT not defined for CheckerCPU.\n"); return 0; } - void setRegOtherThread(const RegId& misc_reg, MiscReg val, - ThreadID tid) override + void + setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override { panic("MIPS MT not defined for CheckerCPU.\n"); } @@ -455,33 +468,36 @@ class CheckerCPU : public BaseCPU, public ExecContext ///////////////////////////////////////// - void recordPCChange(const TheISA::PCState &val) + void + recordPCChange(const TheISA::PCState &val) { changedPC = true; newPCState = val; } - void demapPage(Addr vaddr, uint64_t asn) override + void + demapPage(Addr vaddr, uint64_t asn) override { this->itb->demapPage(vaddr, asn); this->dtb->demapPage(vaddr, asn); } // monitor/mwait funtions - void armMonitor(Addr address) override - { BaseCPU::armMonitor(0, address); } + void armMonitor(Addr address) override { BaseCPU::armMonitor(0, address); } bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } void mwaitAtomic(ThreadContext *tc) override { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } AddressMonitor *getAddrMonitor() override { return BaseCPU::getCpuAddrMonitor(0); } - void demapInstPage(Addr vaddr, uint64_t asn) + void + demapInstPage(Addr vaddr, uint64_t asn) { this->itb->demapPage(vaddr, asn); } - void demapDataPage(Addr vaddr, uint64_t asn) + void + demapDataPage(Addr vaddr, uint64_t asn) { this->dtb->demapPage(vaddr, asn); } @@ -491,12 +507,12 @@ class CheckerCPU : public BaseCPU, public ExecContext Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res) override; - unsigned int readStCondFailures() const override { + unsigned int + readStCondFailures() const override { return thread->readStCondFailures(); } - void setStCondFailures(unsigned int sc_failures) override - {} + void setStCondFailures(unsigned int sc_failures) override {} ///////////////////////////////////////////////////// Fault hwrei() override { return thread->hwrei(); } @@ -507,7 +523,8 @@ class CheckerCPU : public BaseCPU, public ExecContext // The checker's state would have already been updated by the syscall. void syscall(int64_t callnum, Fault *fault) override { } - void handleError() + void + handleError() { if (exitOnError) dumpAndExit(); diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 85053dfa6..854771fdd 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -206,11 +206,13 @@ class CheckerThreadContext : public ThreadContext // // New accessors for new decoder. // - uint64_t readIntReg(int reg_idx) - { return actualTC->readIntReg(reg_idx); } + RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - FloatRegBits readFloatRegBits(int reg_idx) - { return actualTC->readFloatRegBits(reg_idx); } + RegVal + readFloatRegBits(int reg_idx) + { + return actualTC->readFloatRegBits(reg_idx); + } const VecRegContainer& readVecReg(const RegId& reg) const { return actualTC->readVecReg(reg); } @@ -264,31 +266,36 @@ class CheckerThreadContext : public ThreadContext CCReg readCCReg(int reg_idx) { return actualTC->readCCReg(reg_idx); } - void setIntReg(int reg_idx, uint64_t val) + void + setIntReg(int reg_idx, RegVal val) { actualTC->setIntReg(reg_idx, val); checkerTC->setIntReg(reg_idx, val); } - void setFloatRegBits(int reg_idx, FloatRegBits val) + void + setFloatRegBits(int reg_idx, RegVal val) { actualTC->setFloatRegBits(reg_idx, val); checkerTC->setFloatRegBits(reg_idx, val); } - void setVecReg(const RegId& reg, const VecRegContainer& val) + void + setVecReg(const RegId& reg, const VecRegContainer& val) { actualTC->setVecReg(reg, val); checkerTC->setVecReg(reg, val); } - void setVecElem(const RegId& reg, const VecElem& val) + void + setVecElem(const RegId& reg, const VecElem& val) { actualTC->setVecElem(reg, val); checkerTC->setVecElem(reg, val); } - void setCCReg(int reg_idx, CCReg val) + void + setCCReg(int reg_idx, CCReg val) { actualTC->setCCReg(reg_idx, val); checkerTC->setCCReg(reg_idx, val); @@ -299,7 +306,8 @@ class CheckerThreadContext : public ThreadContext { return actualTC->pcState(); } /** Sets this thread's PC state. */ - void pcState(const TheISA::PCState &val) + void + pcState(const TheISA::PCState &val) { DPRINTF(Checker, "Changing PC to %s, old PC %s\n", val, checkerTC->pcState()); @@ -308,13 +316,15 @@ class CheckerThreadContext : public ThreadContext return actualTC->pcState(val); } - void setNPC(Addr val) + void + setNPC(Addr val) { checkerTC->setNPC(val); actualTC->setNPC(val); } - void pcStateNoRecord(const TheISA::PCState &val) + void + pcStateNoRecord(const TheISA::PCState &val) { return actualTC->pcState(val); } @@ -331,13 +341,14 @@ class CheckerThreadContext : public ThreadContext MicroPC microPC() { return actualTC->microPC(); } - MiscReg readMiscRegNoEffect(int misc_reg) const + RegVal readMiscRegNoEffect(int misc_reg) const { return actualTC->readMiscRegNoEffect(misc_reg); } - MiscReg readMiscReg(int misc_reg) + RegVal readMiscReg(int misc_reg) { return actualTC->readMiscReg(misc_reg); } - void setMiscRegNoEffect(int misc_reg, const MiscReg &val) + void + setMiscRegNoEffect(int misc_reg, const RegVal &val) { DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" " and O3..\n", misc_reg); @@ -345,7 +356,8 @@ class CheckerThreadContext : public ThreadContext actualTC->setMiscRegNoEffect(misc_reg, val); } - void setMiscReg(int misc_reg, const MiscReg &val) + void + setMiscReg(int misc_reg, const RegVal &val) { DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" " and O3..\n", misc_reg); @@ -353,40 +365,57 @@ class CheckerThreadContext : public ThreadContext actualTC->setMiscReg(misc_reg, val); } - RegId flattenRegId(const RegId& regId) const { + RegId + flattenRegId(const RegId& regId) const + { return actualTC->flattenRegId(regId); } unsigned readStCondFailures() { return actualTC->readStCondFailures(); } - void setStCondFailures(unsigned sc_failures) + void + setStCondFailures(unsigned sc_failures) { actualTC->setStCondFailures(sc_failures); } Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } - uint64_t readIntRegFlat(int idx) - { return actualTC->readIntRegFlat(idx); } + RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); } - void setIntRegFlat(int idx, uint64_t val) - { actualTC->setIntRegFlat(idx, val); } + void + setIntRegFlat(int idx, RegVal val) + { + actualTC->setIntRegFlat(idx, val); + } - FloatRegBits readFloatRegBitsFlat(int idx) - { return actualTC->readFloatRegBitsFlat(idx); } + RegVal + readFloatRegBitsFlat(int idx) + { + return actualTC->readFloatRegBitsFlat(idx); + } - void setFloatRegBitsFlat(int idx, FloatRegBits val) - { actualTC->setFloatRegBitsFlat(idx, val); } + void + setFloatRegBitsFlat(int idx, RegVal val) + { + actualTC->setFloatRegBitsFlat(idx, val); + } - const VecRegContainer& readVecRegFlat(int idx) const - { return actualTC->readVecRegFlat(idx); } + const VecRegContainer & + readVecRegFlat(int idx) const + { + return actualTC->readVecRegFlat(idx); + } /** * Read vector register for modification, flat indexing. */ - VecRegContainer& getWritableVecRegFlat(int idx) - { return actualTC->getWritableVecRegFlat(idx); } + VecRegContainer & + getWritableVecRegFlat(int idx) + { + return actualTC->getWritableVecRegFlat(idx); + } void setVecRegFlat(int idx, const VecRegContainer& val) { actualTC->setVecRegFlat(idx, val); } diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 89efe8415..0fe4a731a 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -72,11 +72,7 @@ */ class ExecContext { public: - typedef TheISA::IntReg IntReg; typedef TheISA::PCState PCState; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscReg MiscReg; typedef TheISA::CCReg CCReg; using VecRegContainer = TheISA::VecRegContainer; @@ -90,11 +86,11 @@ class ExecContext { */ /** Reads an integer register. */ - virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; + virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0; /** Sets an integer register to a value. */ virtual void setIntRegOperand(const StaticInst *si, - int idx, IntReg val) = 0; + int idx, RegVal val) = 0; /** @} */ @@ -106,13 +102,12 @@ class ExecContext { /** Reads a floating point register in its binary format, instead * of by value. */ - virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, - int idx) = 0; + virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0; /** Sets the bits of a floating point register of single width * to a binary value. */ virtual void setFloatRegOperandBits(const StaticInst *si, - int idx, FloatRegBits val) = 0; + int idx, RegVal val) = 0; /** @} */ @@ -185,21 +180,21 @@ class ExecContext { * @{ * @name Misc Register Interfaces */ - virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; + virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0; virtual void setMiscRegOperand(const StaticInst *si, - int idx, const MiscReg &val) = 0; + int idx, const RegVal &val) = 0; /** * Reads a miscellaneous register, handling any architectural * side effects due to reading that register. */ - virtual MiscReg readMiscReg(int misc_reg) = 0; + virtual RegVal readMiscReg(int misc_reg) = 0; /** * Sets a miscellaneous register, handling any architectural * side effects due to writing that register. */ - virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual void setMiscReg(int misc_reg, const RegVal &val) = 0; /** @} */ @@ -326,10 +321,10 @@ class ExecContext { */ #if THE_ISA == MIPS_ISA - virtual MiscReg readRegOtherThread(const RegId& reg, - ThreadID tid = InvalidThreadID) = 0; - virtual void setRegOtherThread(const RegId& reg, MiscReg val, - ThreadID tid = InvalidThreadID) = 0; + virtual RegVal readRegOtherThread(const RegId ®, + ThreadID tid=InvalidThreadID) = 0; + virtual void setRegOtherThread(const RegId& reg, RegVal val, + ThreadID tid=InvalidThreadID) = 0; #endif /** @} */ diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc index c7625bcc6..268fb9e6d 100644 --- a/src/cpu/kvm/x86_cpu.cc +++ b/src/cpu/kvm/x86_cpu.cc @@ -823,9 +823,6 @@ template <typename T> static void updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) { - static_assert(sizeof(X86ISA::FloatRegBits) == 8, - "Unexpected size of X86ISA::FloatRegBits"); - fpu.mxcsr = tc->readMiscRegNoEffect(MISCREG_MXCSR); fpu.fcw = tc->readMiscRegNoEffect(MISCREG_FCW); // No need to rebuild from MISCREG_FSW and MISCREG_TOP if we read @@ -850,9 +847,9 @@ updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) // TODO: We should update the MMX state for (int i = 0; i < 16; ++i) { - *(X86ISA::FloatRegBits *)&fpu.xmm[i][0] = + *(uint64_t *)&fpu.xmm[i][0] = tc->readFloatRegBits(FLOATREG_XMM_LOW(i)); - *(X86ISA::FloatRegBits *)&fpu.xmm[i][8] = + *(uint64_t *)&fpu.xmm[i][8] = tc->readFloatRegBits(FLOATREG_XMM_HIGH(i)); } } @@ -1048,9 +1045,6 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) { const unsigned top((fpu.fsw >> 11) & 0x7); - static_assert(sizeof(X86ISA::FloatRegBits) == 8, - "Unexpected size of X86ISA::FloatRegBits"); - for (int i = 0; i < 8; ++i) { const unsigned reg_idx((i + top) & 0x7); const double value(X86ISA::loadFloat80(fpu.fpr[i])); @@ -1075,9 +1069,9 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) for (int i = 0; i < 16; ++i) { tc->setFloatRegBits(FLOATREG_XMM_LOW(i), - *(X86ISA::FloatRegBits *)&fpu.xmm[i][0]); + *(uint64_t *)&fpu.xmm[i][0]); tc->setFloatRegBits(FLOATREG_XMM_HIGH(i), - *(X86ISA::FloatRegBits *)&fpu.xmm[i][8]); + *(uint64_t *)&fpu.xmm[i][8]); } } diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 19bae74bf..9f8e9f7af 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -121,7 +121,7 @@ class ExecContext : public ::ExecContext return NoFault; } - IntReg + RegVal readIntRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); @@ -129,7 +129,7 @@ class ExecContext : public ::ExecContext return thread.readIntReg(reg.index()); } - TheISA::FloatRegBits + RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); @@ -137,7 +137,7 @@ class ExecContext : public ::ExecContext return thread.readFloatRegBits(reg.index()); } - const TheISA::VecRegContainer& + const TheISA::VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override { const RegId& reg = si->srcRegIdx(idx); @@ -145,7 +145,7 @@ class ExecContext : public ::ExecContext return thread.readVecReg(reg); } - TheISA::VecRegContainer& + TheISA::VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->destRegIdx(idx); @@ -162,7 +162,7 @@ class ExecContext : public ::ExecContext } void - setIntRegOperand(const StaticInst *si, int idx, IntReg val) override + setIntRegOperand(const StaticInst *si, int idx, RegVal val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isIntReg()); @@ -170,8 +170,7 @@ class ExecContext : public ::ExecContext } void - setFloatRegOperandBits(const StaticInst *si, int idx, - TheISA::FloatRegBits val) override + setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); @@ -232,8 +231,7 @@ class ExecContext : public ::ExecContext /** Write a lane of the destination vector operand. */ template <typename LD> void - setVecLaneOperandT(const StaticInst *si, int idx, - const LD& val) + setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) { const RegId& reg = si->destRegIdx(idx); assert(reg.isVecReg()); @@ -298,25 +296,25 @@ class ExecContext : public ::ExecContext thread.pcState(val); } - TheISA::MiscReg + RegVal readMiscRegNoEffect(int misc_reg) const { return thread.readMiscRegNoEffect(misc_reg); } - TheISA::MiscReg + RegVal readMiscReg(int misc_reg) override { return thread.readMiscReg(misc_reg); } void - setMiscReg(int misc_reg, const TheISA::MiscReg &val) override + setMiscReg(int misc_reg, const RegVal &val) override { thread.setMiscReg(misc_reg, val); } - TheISA::MiscReg + RegVal readMiscRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); @@ -326,7 +324,7 @@ class ExecContext : public ::ExecContext void setMiscRegOperand(const StaticInst *si, int idx, - const TheISA::MiscReg &val) override + const RegVal &val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isMiscReg()); @@ -355,7 +353,7 @@ class ExecContext : public ::ExecContext void syscall(int64_t callnum, Fault *fault) override - { + { if (FullSystem) panic("Syscall emulation isn't available in FS mode.\n"); @@ -410,8 +408,8 @@ class ExecContext : public ::ExecContext BaseCPU *getCpuPtr() { return &cpu; } /* MIPS: other thread register reading/writing */ - uint64_t - readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID) + RegVal + readRegOtherThread(const RegId ®, ThreadID tid=InvalidThreadID) { SimpleThread *other_thread = (tid == InvalidThreadID ? &thread : cpu.threads[tid]); @@ -433,8 +431,8 @@ class ExecContext : public ::ExecContext } void - setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val, - ThreadID tid = InvalidThreadID) + setRegOtherThread(const RegId ®, const RegVal &val, + ThreadID tid=InvalidThreadID) { SimpleThread *other_thread = (tid == InvalidThreadID ? &thread : cpu.threads[tid]); diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 8f399e9f5..c65e509f9 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1244,14 +1244,14 @@ FullO3CPU<Impl>::verifyMemoryMode() const } template <class Impl> -TheISA::MiscReg +RegVal FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const { return this->isa[tid]->readMiscRegNoEffect(misc_reg); } template <class Impl> -TheISA::MiscReg +RegVal FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) { miscRegfileReads++; @@ -1261,7 +1261,7 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) template <class Impl> void FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, - const TheISA::MiscReg &val, ThreadID tid) + const RegVal &val, ThreadID tid) { this->isa[tid]->setMiscRegNoEffect(misc_reg, val); } @@ -1269,14 +1269,14 @@ FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, template <class Impl> void FullO3CPU<Impl>::setMiscReg(int misc_reg, - const TheISA::MiscReg &val, ThreadID tid) + const RegVal &val, ThreadID tid) { miscRegfileWrites++; this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); } template <class Impl> -uint64_t +RegVal FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) { intRegfileReads++; @@ -1284,7 +1284,7 @@ FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) } template <class Impl> -FloatRegBits +RegVal FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg) { fpRegfileReads++; @@ -1327,7 +1327,7 @@ FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg) template <class Impl> void -FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val) +FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) { intRegfileWrites++; regFile.setIntReg(phys_reg, val); @@ -1335,7 +1335,7 @@ FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val) template <class Impl> void -FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) +FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) { fpRegfileWrites++; regFile.setFloatRegBits(phys_reg, val); @@ -1366,7 +1366,7 @@ FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val) } template <class Impl> -uint64_t +RegVal FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) { intRegfileReads++; @@ -1377,7 +1377,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) } template <class Impl> -uint64_t +RegVal FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid) { fpRegfileReads++; @@ -1430,7 +1430,7 @@ FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) +FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid) { intRegfileWrites++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( @@ -1441,7 +1441,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid) +FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid) { fpRegfileWrites++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 4c4677615..431eb0f2f 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -382,26 +382,24 @@ class FullO3CPU : public BaseO3CPU /** Register accessors. Index refers to the physical register index. */ /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; + RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const; /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); + RegVal readMiscReg(int misc_reg, ThreadID tid); /** Sets a miscellaneous register. */ - void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, - ThreadID tid); + void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val, - ThreadID tid); + void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid); - uint64_t readIntReg(PhysRegIdPtr phys_reg); + RegVal readIntReg(PhysRegIdPtr phys_reg); - TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg); + RegVal readFloatRegBits(PhysRegIdPtr phys_reg); const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; @@ -445,9 +443,9 @@ class FullO3CPU : public BaseO3CPU TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); - void setIntReg(PhysRegIdPtr phys_reg, uint64_t val); + void setIntReg(PhysRegIdPtr phys_reg, RegVal val); - void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val); + void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val); void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); @@ -455,9 +453,9 @@ class FullO3CPU : public BaseO3CPU void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); - uint64_t readArchIntReg(int reg_idx, ThreadID tid); + RegVal readArchIntReg(int reg_idx, ThreadID tid); - uint64_t readArchFloatRegBits(int reg_idx, ThreadID tid); + RegVal readArchFloatRegBits(int reg_idx, ThreadID tid); const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; /** Read architectural vector register for modification. */ @@ -494,9 +492,9 @@ class FullO3CPU : public BaseO3CPU * architected register first, then accesses that physical * register. */ - void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); + void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); - void setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid); + void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid); void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index d4fbc78f9..9054b2089 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -66,17 +66,11 @@ class BaseO3DynInst : public BaseDynInst<Impl> /** Binary machine instruction type. */ typedef TheISA::MachInst MachInst; /** Register types. */ - typedef TheISA::IntReg IntReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::CCReg CCReg; using VecRegContainer = TheISA::VecRegContainer; using VecElem = TheISA::VecElem; static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; - /** Misc register type. */ - typedef TheISA::MiscReg MiscReg; - enum { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs @@ -114,7 +108,7 @@ class BaseO3DynInst : public BaseDynInst<Impl> using BaseDynInst<Impl>::_destRegIdx; /** Values to be written to the destination misc. registers. */ - std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; + std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal; /** Indexes of the destination misc. registers. They are needed to defer * the write accesses to the misc. registers until the commit stage, when @@ -142,7 +136,8 @@ class BaseO3DynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscReg(int misc_reg) + RegVal + readMiscReg(int misc_reg) { return this->cpu->readMiscReg(misc_reg, this->threadNumber); } @@ -150,7 +145,8 @@ class BaseO3DynInst : public BaseDynInst<Impl> /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscReg(int misc_reg, const MiscReg &val) + void + setMiscReg(int misc_reg, const RegVal &val) { /** Writes to misc. registers are recorded and deferred until the * commit stage, when updateMiscRegs() is called. First, check if @@ -174,7 +170,8 @@ class BaseO3DynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) + RegVal + readMiscRegOperand(const StaticInst *si, int idx) { const RegId& reg = si->srcRegIdx(idx); assert(reg.isMiscReg()); @@ -184,8 +181,8 @@ class BaseO3DynInst : public BaseDynInst<Impl> /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscRegOperand(const StaticInst *si, int idx, - const MiscReg &val) + void + setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val) { const RegId& reg = si->destRegIdx(idx); assert(reg.isMiscReg()); @@ -193,7 +190,8 @@ class BaseO3DynInst : public BaseDynInst<Impl> } /** Called at the commit stage to update the misc. registers. */ - void updateMiscRegs() + void + updateMiscRegs() { // @todo: Pretty convoluted way to avoid squashing from happening when // using the TC during an instruction's execution (specifically for @@ -268,12 +266,14 @@ class BaseO3DynInst : public BaseDynInst<Impl> // storage (which is pretty hard to imagine they would have reason // to do). - IntReg readIntRegOperand(const StaticInst *si, int idx) + RegVal + readIntRegOperand(const StaticInst *si, int idx) { return this->cpu->readIntReg(this->_srcRegIdx[idx]); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) + RegVal + readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); } @@ -369,14 +369,15 @@ class BaseO3DynInst : public BaseDynInst<Impl> /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntRegOperand(const StaticInst *si, int idx, IntReg val) + void + setIntRegOperand(const StaticInst *si, int idx, RegVal val) { this->cpu->setIntReg(this->_destRegIdx[idx], val); BaseDynInst<Impl>::setIntRegOperand(si, idx, val); } - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) + void + setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) { this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); @@ -405,13 +406,15 @@ class BaseO3DynInst : public BaseDynInst<Impl> } #if THE_ISA == MIPS_ISA - MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) + RegVal + readRegOtherThread(const RegId& misc_reg, ThreadID tid) { panic("MIPS MT not defined for O3 CPU.\n"); return 0; } - void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID tid) + void + setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) { panic("MIPS MT not defined for O3 CPU.\n"); } diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 354fe2bc5..9d9113240 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -65,9 +65,6 @@ class PhysRegFile { private: - typedef TheISA::IntReg IntReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::CCReg CCReg; using VecElem = TheISA::VecElem; using VecRegContainer = TheISA::VecRegContainer; @@ -80,11 +77,11 @@ class PhysRegFile static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; /** Integer register file. */ - std::vector<IntReg> intRegFile; + std::vector<RegVal> intRegFile; std::vector<PhysRegId> intRegIds; /** Floating point register file. */ - std::vector<FloatRegBits> floatRegFile; + std::vector<RegVal> floatRegFile; std::vector<PhysRegId> floatRegIds; /** Vector register file. */ @@ -173,7 +170,8 @@ class PhysRegFile } /** Reads an integer register. */ - uint64_t readIntReg(PhysRegIdPtr phys_reg) const + RegVal + readIntReg(PhysRegIdPtr phys_reg) const { assert(phys_reg->isIntPhysReg()); @@ -182,21 +180,22 @@ class PhysRegFile return intRegFile[phys_reg->index()]; } - FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const + RegVal + readFloatRegBits(PhysRegIdPtr phys_reg) const { assert(phys_reg->isFloatPhysReg()); - FloatRegBits floatRegBits = floatRegFile[phys_reg->index()]; + RegVal floatRegBits = floatRegFile[phys_reg->index()]; DPRINTF(IEW, "RegFile: Access to float register %i as int, " - "has data %#x\n", phys_reg->index(), - (uint64_t)floatRegBits); + "has data %#x\n", phys_reg->index(), floatRegBits); return floatRegBits; } /** Reads a vector register. */ - const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const + const VecRegContainer & + readVecReg(PhysRegIdPtr phys_reg) const { assert(phys_reg->isVectorPhysReg()); @@ -208,7 +207,8 @@ class PhysRegFile } /** Reads a vector register for modification. */ - VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg) + VecRegContainer & + getWritableVecReg(PhysRegIdPtr phys_reg) { /* const_cast for not duplicating code above. */ return const_cast<VecRegContainer&>(readVecReg(phys_reg)); @@ -245,7 +245,8 @@ class PhysRegFile } /** Reads a vector element. */ - const VecElem& readVecElem(PhysRegIdPtr phys_reg) const + const VecElem & + readVecElem(PhysRegIdPtr phys_reg) const { assert(phys_reg->isVectorPhysElem()); auto ret = vectorRegFile[phys_reg->index()].as<VecElem>(); @@ -258,7 +259,8 @@ class PhysRegFile } /** Reads a condition-code register. */ - CCReg readCCReg(PhysRegIdPtr phys_reg) + CCReg + readCCReg(PhysRegIdPtr phys_reg) { assert(phys_reg->isCCPhysReg()); @@ -270,7 +272,8 @@ class PhysRegFile } /** Sets an integer register to the given value. */ - void setIntReg(PhysRegIdPtr phys_reg, uint64_t val) + void + setIntReg(PhysRegIdPtr phys_reg, RegVal val) { assert(phys_reg->isIntPhysReg()); @@ -281,7 +284,8 @@ class PhysRegFile intRegFile[phys_reg->index()] = val; } - void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) + void + setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) { assert(phys_reg->isFloatPhysReg()); @@ -293,7 +297,8 @@ class PhysRegFile } /** Sets a vector register to the given value. */ - void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) + void + setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) { assert(phys_reg->isVectorPhysReg()); @@ -304,7 +309,8 @@ class PhysRegFile } /** Sets a vector register to the given value. */ - void setVecElem(PhysRegIdPtr phys_reg, const VecElem val) + void + setVecElem(PhysRegIdPtr phys_reg, const VecElem val) { assert(phys_reg->isVectorPhysElem()); @@ -316,7 +322,8 @@ class PhysRegFile } /** Sets a condition-code register to the given value. */ - void setCCReg(PhysRegIdPtr phys_reg, CCReg val) + void + setCCReg(PhysRegIdPtr phys_reg, CCReg val) { assert(phys_reg->isCCPhysReg()); @@ -338,12 +345,12 @@ class PhysRegFile */ IdRange getRegIds(RegClass cls); - /** - * Get the true physical register id. - * As many parts work with PhysRegIdPtr, we need to be able to produce - * the pointer out of just class and register idx. - */ - PhysRegIdPtr getTrueId(PhysRegIdPtr reg); + /** + * Get the true physical register id. + * As many parts work with PhysRegIdPtr, we need to be able to produce + * the pointer out of just class and register idx. + */ + PhysRegIdPtr getTrueId(PhysRegIdPtr reg); }; diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 1fbf565f5..510e96432 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -175,28 +175,38 @@ class O3ThreadContext : public ThreadContext virtual void clearArchRegs(); /** Reads an integer register. */ - virtual uint64_t readReg(int reg_idx) { + virtual RegVal + readReg(int reg_idx) + { return readIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index()); } - virtual uint64_t readIntReg(int reg_idx) { + virtual RegVal + readIntReg(int reg_idx) + { return readIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index()); } - virtual FloatRegBits readFloatRegBits(int reg_idx) { + virtual RegVal + readFloatRegBits(int reg_idx) + { return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, reg_idx)).index()); } - virtual const VecRegContainer& readVecReg(const RegId& id) const { + virtual const VecRegContainer & + readVecReg(const RegId& id) const + { return readVecRegFlat(flattenRegId(id).index()); } /** * Read vector register operand for modification, hierarchical indexing. */ - virtual VecRegContainer& getWritableVecReg(const RegId& id) { + virtual VecRegContainer & + getWritableVecReg(const RegId& id) + { return getWritableVecRegFlat(flattenRegId(id).index()); } @@ -259,24 +269,34 @@ class O3ThreadContext : public ThreadContext } /** Sets an integer register to a value. */ - virtual void setIntReg(int reg_idx, uint64_t val) { + virtual void + setIntReg(int reg_idx, RegVal val) + { setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); } - virtual void setFloatRegBits(int reg_idx, FloatRegBits val) { + virtual void + setFloatRegBits(int reg_idx, RegVal val) + { setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, reg_idx)).index(), val); } - virtual void setVecReg(const RegId& reg, const VecRegContainer& val) { + virtual void + setVecReg(const RegId& reg, const VecRegContainer& val) + { setVecRegFlat(flattenRegId(reg).index(), val); } - virtual void setVecElem(const RegId& reg, const VecElem& val) { + virtual void + setVecElem(const RegId& reg, const VecElem& val) + { setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } - virtual void setCCReg(int reg_idx, CCReg val) { + virtual void + setCCReg(int reg_idx, CCReg val) + { setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); } @@ -302,20 +322,20 @@ class O3ThreadContext : public ThreadContext { return cpu->microPC(thread->threadId()); } /** Reads a miscellaneous register. */ - virtual MiscReg readMiscRegNoEffect(int misc_reg) const + virtual RegVal readMiscRegNoEffect(int misc_reg) const { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ - virtual MiscReg readMiscReg(int misc_reg) + virtual RegVal readMiscReg(int misc_reg) { return cpu->readMiscReg(misc_reg, thread->threadId()); } /** Sets a misc. register. */ - virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); + virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val); /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual void setMiscReg(int misc_reg, const MiscReg &val); + virtual void setMiscReg(int misc_reg, const RegVal &val); virtual RegId flattenRegId(const RegId& regId) const; @@ -336,7 +356,8 @@ class O3ThreadContext : public ThreadContext virtual Counter readFuncExeInst() { return thread->funcExeInst; } /** Returns pointer to the quiesce event. */ - virtual EndQuiesceEvent *getQuiesceEvent() + virtual EndQuiesceEvent * + getQuiesceEvent() { return this->thread->quiesceEvent; } @@ -345,17 +366,18 @@ class O3ThreadContext : public ThreadContext * similar is currently writing to the thread context and doesn't want * reset all the state (see noSquashFromTC). */ - inline void conditionalSquash() + inline void + conditionalSquash() { if (!thread->trapPending && !thread->noSquashFromTC) cpu->squashFromTC(thread->threadId()); } - virtual uint64_t readIntRegFlat(int idx); - virtual void setIntRegFlat(int idx, uint64_t val); + virtual RegVal readIntRegFlat(int idx); + virtual void setIntRegFlat(int idx, RegVal val); - virtual FloatRegBits readFloatRegBitsFlat(int idx); - virtual void setFloatRegBitsFlat(int idx, FloatRegBits val); + virtual RegVal readFloatRegBitsFlat(int idx); + virtual void setFloatRegBitsFlat(int idx, RegVal val); virtual const VecRegContainer& readVecRegFlat(int idx) const; /** Read vector register operand for modification, flat indexing. */ @@ -363,7 +385,8 @@ class O3ThreadContext : public ThreadContext virtual void setVecRegFlat(int idx, const VecRegContainer& val); template <typename VecElem> - VecLaneT<VecElem, true> readVecLaneFlat(int idx, int lId) const + VecLaneT<VecElem, true> + readVecLaneFlat(int idx, int lId) const { return cpu->template readArchVecLane<VecElem>(idx, lId, thread->threadId()); diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index f4b5cb4f4..086d2cfeb 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -193,14 +193,14 @@ O3ThreadContext<Impl>::clearArchRegs() } template <class Impl> -uint64_t +RegVal O3ThreadContext<Impl>::readIntRegFlat(int reg_idx) { return cpu->readArchIntReg(reg_idx, thread->threadId()); } template <class Impl> -TheISA::FloatRegBits +RegVal O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx) { return cpu->readArchFloatRegBits(reg_idx, thread->threadId()); @@ -237,7 +237,7 @@ O3ThreadContext<Impl>::readCCRegFlat(int reg_idx) template <class Impl> void -O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) +O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val) { cpu->setArchIntReg(reg_idx, val, thread->threadId()); @@ -246,7 +246,7 @@ O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) template <class Impl> void -O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val) +O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, RegVal val) { cpu->setArchFloatRegBits(reg_idx, val, thread->threadId()); @@ -307,7 +307,7 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const template <class Impl> void -O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) +O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val) { cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); @@ -317,7 +317,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) #endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ template <class Impl> void -O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) +O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val) { cpu->setMiscReg(misc_reg, val, thread->threadId()); diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 1aababf35..aa6ee8ba3 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -60,9 +60,6 @@ class BaseSimpleCPU; class SimpleExecContext : public ExecContext { protected: - typedef TheISA::MiscReg MiscReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::CCReg CCReg; using VecRegContainer = TheISA::VecRegContainer; using VecElem = TheISA::VecElem; @@ -174,7 +171,8 @@ class SimpleExecContext : public ExecContext { { } /** Reads an integer register. */ - IntReg readIntRegOperand(const StaticInst *si, int idx) override + RegVal + readIntRegOperand(const StaticInst *si, int idx) override { numIntRegReads++; const RegId& reg = si->srcRegIdx(idx); @@ -183,7 +181,8 @@ class SimpleExecContext : public ExecContext { } /** Sets an integer register to a value. */ - void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override + void + setIntRegOperand(const StaticInst *si, int idx, RegVal val) override { numIntRegWrites++; const RegId& reg = si->destRegIdx(idx); @@ -193,7 +192,8 @@ class SimpleExecContext : public ExecContext { /** Reads a floating point register in its binary format, instead * of by value. */ - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override + RegVal + readFloatRegOperandBits(const StaticInst *si, int idx) override { numFpRegReads++; const RegId& reg = si->srcRegIdx(idx); @@ -203,8 +203,8 @@ class SimpleExecContext : public ExecContext { /** Sets the bits of a floating point register of single width * to a binary value. */ - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) override + void + setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override { numFpRegWrites++; const RegId& reg = si->destRegIdx(idx); @@ -213,7 +213,7 @@ class SimpleExecContext : public ExecContext { } /** Reads a vector register. */ - const VecRegContainer& + const VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override { numVecRegReads++; @@ -223,7 +223,7 @@ class SimpleExecContext : public ExecContext { } /** Reads a vector register for modification. */ - VecRegContainer& + VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override { numVecRegWrites++; @@ -233,8 +233,9 @@ class SimpleExecContext : public ExecContext { } /** Sets a vector register to a value. */ - void setVecRegOperand(const StaticInst *si, int idx, - const VecRegContainer& val) override + void + setVecRegOperand(const StaticInst *si, int idx, + const VecRegContainer& val) override { numVecRegWrites++; const RegId& reg = si->destRegIdx(idx); @@ -312,7 +313,8 @@ class SimpleExecContext : public ExecContext { /** @} */ /** Reads an element of a vector register. */ - VecElem readVecElemOperand(const StaticInst *si, int idx) const override + VecElem + readVecElemOperand(const StaticInst *si, int idx) const override { numVecRegReads++; const RegId& reg = si->destRegIdx(idx); @@ -321,8 +323,9 @@ class SimpleExecContext : public ExecContext { } /** Sets an element of a vector register to a value. */ - void setVecElemOperand(const StaticInst *si, int idx, - const VecElem val) override + void + setVecElemOperand(const StaticInst *si, int idx, + const VecElem val) override { numVecRegWrites++; const RegId& reg = si->destRegIdx(idx); @@ -330,7 +333,8 @@ class SimpleExecContext : public ExecContext { thread->setVecElem(reg, val); } - CCReg readCCRegOperand(const StaticInst *si, int idx) override + CCReg + readCCRegOperand(const StaticInst *si, int idx) override { numCCRegReads++; const RegId& reg = si->srcRegIdx(idx); @@ -338,7 +342,8 @@ class SimpleExecContext : public ExecContext { return thread->readCCReg(reg.index()); } - void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override + void + setCCRegOperand(const StaticInst *si, int idx, CCReg val) override { numCCRegWrites++; const RegId& reg = si->destRegIdx(idx); @@ -346,7 +351,8 @@ class SimpleExecContext : public ExecContext { thread->setCCReg(reg.index(), val); } - MiscReg readMiscRegOperand(const StaticInst *si, int idx) override + RegVal + readMiscRegOperand(const StaticInst *si, int idx) override { numIntRegReads++; const RegId& reg = si->srcRegIdx(idx); @@ -354,8 +360,9 @@ class SimpleExecContext : public ExecContext { return thread->readMiscReg(reg.index()); } - void setMiscRegOperand(const StaticInst *si, int idx, - const MiscReg &val) override + void + setMiscRegOperand(const StaticInst *si, int idx, + const RegVal &val) override { numIntRegWrites++; const RegId& reg = si->destRegIdx(idx); @@ -367,7 +374,8 @@ class SimpleExecContext : public ExecContext { * Reads a miscellaneous register, handling any architectural * side effects due to reading that register. */ - MiscReg readMiscReg(int misc_reg) override + RegVal + readMiscReg(int misc_reg) override { numIntRegReads++; return thread->readMiscReg(misc_reg); @@ -377,37 +385,43 @@ class SimpleExecContext : public ExecContext { * Sets a miscellaneous register, handling any architectural * side effects due to writing that register. */ - void setMiscReg(int misc_reg, const MiscReg &val) override + void + setMiscReg(int misc_reg, const RegVal &val) override { numIntRegWrites++; thread->setMiscReg(misc_reg, val); } - PCState pcState() const override + PCState + pcState() const override { return thread->pcState(); } - void pcState(const PCState &val) override + void + pcState(const PCState &val) override { thread->pcState(val); } - Fault readMem(Addr addr, uint8_t *data, unsigned int size, - Request::Flags flags) override + Fault + readMem(Addr addr, uint8_t *data, unsigned int size, + Request::Flags flags) override { return cpu->readMem(addr, data, size, flags); } - Fault initiateMemRead(Addr addr, unsigned int size, - Request::Flags flags) override + Fault + initiateMemRead(Addr addr, unsigned int size, + Request::Flags flags) override { return cpu->initiateMemRead(addr, size, flags); } - Fault writeMem(uint8_t *data, unsigned int size, Addr addr, - Request::Flags flags, uint64_t *res) override + Fault + writeMem(uint8_t *data, unsigned int size, Addr addr, + Request::Flags flags, uint64_t *res) override { return cpu->writeMem(data, size, addr, flags, res); } @@ -415,7 +429,8 @@ class SimpleExecContext : public ExecContext { /** * Sets the number of consecutive store conditional failures. */ - void setStCondFailures(unsigned int sc_failures) override + void + setStCondFailures(unsigned int sc_failures) override { thread->setStCondFailures(sc_failures); } @@ -423,7 +438,8 @@ class SimpleExecContext : public ExecContext { /** * Returns the number of consecutive store conditional failures. */ - unsigned int readStCondFailures() const override + unsigned int + readStCondFailures() const override { return thread->readStCondFailures(); } @@ -431,7 +447,8 @@ class SimpleExecContext : public ExecContext { /** * Executes a syscall specified by the callnum. */ - void syscall(int64_t callnum, Fault *fault) override + void + syscall(int64_t callnum, Fault *fault) override { if (FullSystem) panic("Syscall emulation isn't available in FS mode."); @@ -440,35 +457,32 @@ class SimpleExecContext : public ExecContext { } /** Returns a pointer to the ThreadContext. */ - ThreadContext *tcBase() override - { - return thread->getTC(); - } + ThreadContext *tcBase() override { return thread->getTC(); } /** * Somewhat Alpha-specific function that handles returning from an * error or interrupt. */ - Fault hwrei() override - { - return thread->hwrei(); - } + Fault hwrei() override { return thread->hwrei(); } /** * Check for special simulator handling of specific PAL calls. If * return value is false, actual PAL call will be suppressed. */ - bool simPalCheck(int palFunc) override + bool + simPalCheck(int palFunc) override { return thread->simPalCheck(palFunc); } - bool readPredicate() const override + bool + readPredicate() const override { return thread->readPredicate(); } - void setPredicate(bool val) override + void + setPredicate(bool val) override { thread->setPredicate(val); @@ -480,47 +494,52 @@ class SimpleExecContext : public ExecContext { /** * Invalidate a page in the DTLB <i>and</i> ITLB. */ - void demapPage(Addr vaddr, uint64_t asn) override + void + demapPage(Addr vaddr, uint64_t asn) override { thread->demapPage(vaddr, asn); } - void armMonitor(Addr address) override + void + armMonitor(Addr address) override { cpu->armMonitor(thread->threadId(), address); } - bool mwait(PacketPtr pkt) override + bool + mwait(PacketPtr pkt) override { return cpu->mwait(thread->threadId(), pkt); } - void mwaitAtomic(ThreadContext *tc) override + void + mwaitAtomic(ThreadContext *tc) override { cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb); } - AddressMonitor *getAddrMonitor() override + AddressMonitor * + getAddrMonitor() override { return cpu->getCpuAddrMonitor(thread->threadId()); } #if THE_ISA == MIPS_ISA - MiscReg readRegOtherThread(const RegId& reg, - ThreadID tid = InvalidThreadID) + RegVal + readRegOtherThread(const RegId& reg, ThreadID tid=InvalidThreadID) override { panic("Simple CPU models do not support multithreaded " "register access."); } - void setRegOtherThread(const RegId& reg, MiscReg val, - ThreadID tid = InvalidThreadID) override + void + setRegOtherThread(const RegId& reg, RegVal val, + ThreadID tid=InvalidThreadID) override { panic("Simple CPU models do not support multithreaded " "register access."); } - #endif }; diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 65491f27a..073f7ab2c 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -99,9 +99,6 @@ class SimpleThread : public ThreadState { protected: typedef TheISA::MachInst MachInst; - typedef TheISA::MiscReg MiscReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::CCReg CCReg; using VecRegContainer = TheISA::VecRegContainer; using VecElem = TheISA::VecElem; @@ -109,8 +106,8 @@ class SimpleThread : public ThreadState typedef ThreadContext::Status Status; protected: - FloatRegBits floatRegs[TheISA::NumFloatRegs]; - TheISA::IntReg intRegs[TheISA::NumIntRegs]; + RegVal floatRegs[TheISA::NumFloatRegs]; + RegVal intRegs[TheISA::NumIntRegs]; VecRegContainer vecRegs[TheISA::NumVecRegs]; #ifdef ISA_HAS_CC_REGS TheISA::CCReg ccRegs[TheISA::NumCCRegs]; @@ -240,7 +237,8 @@ class SimpleThread : public ThreadState // // New accessors for new decoder. // - uint64_t readIntReg(int reg_idx) + RegVal + readIntReg(int reg_idx) { int flatIndex = isa->flattenIntIndex(reg_idx); assert(flatIndex < TheISA::NumIntRegs); @@ -250,11 +248,12 @@ class SimpleThread : public ThreadState return regVal; } - FloatRegBits readFloatRegBits(int reg_idx) + RegVal + readFloatRegBits(int reg_idx) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); + RegVal regVal(readFloatRegBitsFlat(flatIndex)); DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", reg_idx, flatIndex, regVal); return regVal; @@ -368,7 +367,8 @@ class SimpleThread : public ThreadState #endif } - void setIntReg(int reg_idx, uint64_t val) + void + setIntReg(int reg_idx, RegVal val) { int flatIndex = isa->flattenIntIndex(reg_idx); assert(flatIndex < TheISA::NumIntRegs); @@ -377,7 +377,8 @@ class SimpleThread : public ThreadState setIntRegFlat(flatIndex, val); } - void setFloatRegBits(int reg_idx, FloatRegBits val) + void + setFloatRegBits(int reg_idx, RegVal val) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); @@ -389,7 +390,8 @@ class SimpleThread : public ThreadState reg_idx, flatIndex, val); } - void setVecReg(const RegId& reg, const VecRegContainer& val) + void + setVecReg(const RegId& reg, const VecRegContainer& val) { int flatIndex = isa->flattenVecIndex(reg.index()); assert(flatIndex < TheISA::NumVecRegs); @@ -398,7 +400,8 @@ class SimpleThread : public ThreadState reg.index(), flatIndex, val.print()); } - void setVecElem(const RegId& reg, const VecElem& val) + void + setVecElem(const RegId& reg, const VecElem& val) { int flatIndex = isa->flattenVecElemIndex(reg.index()); assert(flatIndex < TheISA::NumVecRegs); @@ -407,7 +410,8 @@ class SimpleThread : public ThreadState " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); } - void setCCReg(int reg_idx, CCReg val) + void + setCCReg(int reg_idx, CCReg val) { #ifdef ISA_HAS_CC_REGS int flatIndex = isa->flattenCCIndex(reg_idx); @@ -472,26 +476,26 @@ class SimpleThread : public ThreadState predicate = val; } - MiscReg - readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const + RegVal + readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const { return isa->readMiscRegNoEffect(misc_reg); } - MiscReg - readMiscReg(int misc_reg, ThreadID tid = 0) + RegVal + readMiscReg(int misc_reg, ThreadID tid=0) { return isa->readMiscReg(misc_reg, tc); } void - setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) + setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0) { return isa->setMiscRegNoEffect(misc_reg, val); } void - setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) + setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0) { return isa->setMiscReg(misc_reg, val, tc); } @@ -507,54 +511,59 @@ class SimpleThread : public ThreadState void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } - void syscall(int64_t callnum, Fault *fault) + void + syscall(int64_t callnum, Fault *fault) { process->syscall(callnum, tc, fault); } - uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } - void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } + RegVal readIntRegFlat(int idx) { return intRegs[idx]; } + void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } - FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } - void setFloatRegBitsFlat(int idx, FloatRegBits val) { - floatRegs[idx] = val; - } + RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } + void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } - const VecRegContainer& readVecRegFlat(const RegIndex& reg) const + const VecRegContainer & + readVecRegFlat(const RegIndex& reg) const { return vecRegs[reg]; } - VecRegContainer& getWritableVecRegFlat(const RegIndex& reg) + VecRegContainer & + getWritableVecRegFlat(const RegIndex& reg) { return vecRegs[reg]; } - void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) + void + setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) { vecRegs[reg] = val; } template <typename T> - VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const + VecLaneT<T, true> + readVecLaneFlat(const RegIndex& reg, int lId) const { return vecRegs[reg].laneView<T>(lId); } template <typename LD> - void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) + void + setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) { vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; } - const VecElem& readVecElemFlat(const RegIndex& reg, - const ElemIndex& elemIndex) const + const VecElem & + readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const { return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; } - void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, - const VecElem val) + void + setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, + const VecElem val) { vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; } diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index bf25cd65f..2d907a055 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -61,8 +61,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) // First loop through the integer registers. for (int i = 0; i < TheISA::NumIntRegs; ++i) { - TheISA::IntReg t1 = one->readIntReg(i); - TheISA::IntReg t2 = two->readIntReg(i); + RegVal t1 = one->readIntReg(i); + RegVal t2 = two->readIntReg(i); if (t1 != t2) panic("Int reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -70,8 +70,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) // Then loop through the floating point registers. for (int i = 0; i < TheISA::NumFloatRegs; ++i) { - TheISA::FloatRegBits t1 = one->readFloatRegBits(i); - TheISA::FloatRegBits t2 = two->readFloatRegBits(i); + RegVal t1 = one->readFloatRegBits(i); + RegVal t2 = two->readFloatRegBits(i); if (t1 != t2) panic("Float reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -87,8 +87,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) i, t1, t2); } for (int i = 0; i < TheISA::NumMiscRegs; ++i) { - TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); - TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); + RegVal t1 = one->readMiscRegNoEffect(i); + RegVal t2 = two->readMiscRegNoEffect(i); if (t1 != t2) panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -155,7 +155,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp) { using namespace TheISA; - FloatRegBits floatRegs[NumFloatRegs]; + RegVal floatRegs[NumFloatRegs]; for (int i = 0; i < NumFloatRegs; ++i) floatRegs[i] = tc.readFloatRegBitsFlat(i); // This is a bit ugly, but needed to maintain backwards @@ -168,7 +168,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp) } SERIALIZE_CONTAINER(vecRegs); - IntReg intRegs[NumIntRegs]; + RegVal intRegs[NumIntRegs]; for (int i = 0; i < NumIntRegs; ++i) intRegs[i] = tc.readIntRegFlat(i); SERIALIZE_ARRAY(intRegs, NumIntRegs); @@ -190,7 +190,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp) { using namespace TheISA; - FloatRegBits floatRegs[NumFloatRegs]; + RegVal floatRegs[NumFloatRegs]; // This is a bit ugly, but needed to maintain backwards // compatibility. arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); @@ -203,7 +203,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp) tc.setVecRegFlat(i, vecRegs[i]); } - IntReg intRegs[NumIntRegs]; + RegVal intRegs[NumIntRegs]; UNSERIALIZE_ARRAY(intRegs, NumIntRegs); for (int i = 0; i < NumIntRegs; ++i) tc.setIntRegFlat(i, intRegs[i]); diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index f9dfd8345..db88227d9 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -95,11 +95,7 @@ class ThreadContext { protected: typedef TheISA::MachInst MachInst; - typedef TheISA::IntReg IntReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::CCReg CCReg; - typedef TheISA::MiscReg MiscReg; using VecRegContainer = TheISA::VecRegContainer; using VecElem = TheISA::VecElem; public: @@ -208,9 +204,9 @@ class ThreadContext // // New accessors for new decoder. // - virtual uint64_t readIntReg(int reg_idx) = 0; + virtual RegVal readIntReg(int reg_idx) = 0; - virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; + virtual RegVal readFloatRegBits(int reg_idx) = 0; virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; @@ -248,9 +244,9 @@ class ThreadContext virtual CCReg readCCReg(int reg_idx) = 0; - virtual void setIntReg(int reg_idx, uint64_t val) = 0; + virtual void setIntReg(int reg_idx, RegVal val) = 0; - virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; + virtual void setFloatRegBits(int reg_idx, RegVal val) = 0; virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; @@ -278,24 +274,24 @@ class ThreadContext virtual MicroPC microPC() = 0; - virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0; + virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0; - virtual MiscReg readMiscReg(int misc_reg) = 0; + virtual RegVal readMiscReg(int misc_reg) = 0; - virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; + virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val) = 0; - virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual void setMiscReg(int misc_reg, const RegVal &val) = 0; virtual RegId flattenRegId(const RegId& regId) const = 0; - virtual uint64_t + virtual RegVal readRegOtherThread(const RegId& misc_reg, ThreadID tid) { return 0; } virtual void - setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid) + setRegOtherThread(const RegId& misc_reg, const RegVal &val, ThreadID tid) { } @@ -330,11 +326,11 @@ class ThreadContext * serialization code to access all registers. */ - virtual uint64_t readIntRegFlat(int idx) = 0; - virtual void setIntRegFlat(int idx, uint64_t val) = 0; + virtual RegVal readIntRegFlat(int idx) = 0; + virtual void setIntRegFlat(int idx, RegVal val) = 0; - virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; - virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; + virtual RegVal readFloatRegBitsFlat(int idx) = 0; + virtual void setFloatRegBitsFlat(int idx, RegVal val) = 0; virtual const VecRegContainer& readVecRegFlat(int idx) const = 0; virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0; @@ -454,10 +450,10 @@ class ProxyThreadContext : public ThreadContext // // New accessors for new decoder. // - uint64_t readIntReg(int reg_idx) + RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - FloatRegBits readFloatRegBits(int reg_idx) + RegVal readFloatRegBits(int reg_idx) { return actualTC->readFloatRegBits(reg_idx); } const VecRegContainer& readVecReg(const RegId& reg) const @@ -509,10 +505,10 @@ class ProxyThreadContext : public ThreadContext CCReg readCCReg(int reg_idx) { return actualTC->readCCReg(reg_idx); } - void setIntReg(int reg_idx, uint64_t val) + void setIntReg(int reg_idx, RegVal val) { actualTC->setIntReg(reg_idx, val); } - void setFloatRegBits(int reg_idx, FloatRegBits val) + void setFloatRegBits(int reg_idx, RegVal val) { actualTC->setFloatRegBits(reg_idx, val); } void setVecReg(const RegId& reg, const VecRegContainer& val) @@ -539,16 +535,16 @@ class ProxyThreadContext : public ThreadContext void setPredicate(bool val) { actualTC->setPredicate(val); } - MiscReg readMiscRegNoEffect(int misc_reg) const + RegVal readMiscRegNoEffect(int misc_reg) const { return actualTC->readMiscRegNoEffect(misc_reg); } - MiscReg readMiscReg(int misc_reg) + RegVal readMiscReg(int misc_reg) { return actualTC->readMiscReg(misc_reg); } - void setMiscRegNoEffect(int misc_reg, const MiscReg &val) + void setMiscRegNoEffect(int misc_reg, const RegVal &val) { return actualTC->setMiscRegNoEffect(misc_reg, val); } - void setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const RegVal &val) { return actualTC->setMiscReg(misc_reg, val); } RegId flattenRegId(const RegId& regId) const @@ -565,16 +561,16 @@ class ProxyThreadContext : public ThreadContext Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } - uint64_t readIntRegFlat(int idx) + RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); } - void setIntRegFlat(int idx, uint64_t val) + void setIntRegFlat(int idx, RegVal val) { actualTC->setIntRegFlat(idx, val); } - FloatRegBits readFloatRegBitsFlat(int idx) + RegVal readFloatRegBitsFlat(int idx) { return actualTC->readFloatRegBitsFlat(idx); } - void setFloatRegBitsFlat(int idx, FloatRegBits val) + void setFloatRegBitsFlat(int idx, RegVal val) { actualTC->setFloatRegBitsFlat(idx, val); } const VecRegContainer& readVecRegFlat(int id) const diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc index 0994f6dd4..396926f40 100644 --- a/src/dev/arm/generic_timer.cc +++ b/src/dev/arm/generic_timer.cc @@ -312,7 +312,7 @@ GenericTimer::createTimers(unsigned cpus) void -GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val) +GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val) { CoreTimers &core(getTimers(cpu)); @@ -417,7 +417,7 @@ GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val) } -MiscReg +RegVal GenericTimer::readMiscReg(int reg, unsigned cpu) { CoreTimers &core(getTimers(cpu)); @@ -508,16 +508,16 @@ GenericTimer::readMiscReg(int reg, unsigned cpu) void -GenericTimerISA::setMiscReg(int reg, MiscReg val) +GenericTimerISA::setMiscReg(int reg, RegVal val) { DPRINTF(Timer, "Setting %s := 0x%x\n", miscRegName[reg], val); parent.setMiscReg(reg, cpu, val); } -MiscReg +RegVal GenericTimerISA::readMiscReg(int reg) { - MiscReg value = parent.readMiscReg(reg, cpu); + RegVal value = parent.readMiscReg(reg, cpu); DPRINTF(Timer, "Reading %s as 0x%x\n", miscRegName[reg], value); return value; } diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh index b3a7e76ff..acd8b3960 100644 --- a/src/dev/arm/generic_timer.hh +++ b/src/dev/arm/generic_timer.hh @@ -223,8 +223,8 @@ class GenericTimer : public ClockedObject void unserialize(CheckpointIn &cp) override; public: - void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val); - ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu); + void setMiscReg(int misc_reg, unsigned cpu, RegVal val); + RegVal readMiscReg(int misc_reg, unsigned cpu); protected: struct CoreTimers { @@ -286,8 +286,8 @@ class GenericTimerISA : public ArmISA::BaseISADevice GenericTimerISA(GenericTimer &_parent, unsigned _cpu) : parent(_parent), cpu(_cpu) {} - void setMiscReg(int misc_reg, ArmISA::MiscReg val) override; - ArmISA::MiscReg readMiscReg(int misc_reg) override; + void setMiscReg(int misc_reg, RegVal val) override; + RegVal readMiscReg(int misc_reg) override; protected: GenericTimer &parent; diff --git a/src/gpu-compute/gpu_exec_context.cc b/src/gpu-compute/gpu_exec_context.cc index 013239757..76854f358 100644 --- a/src/gpu-compute/gpu_exec_context.cc +++ b/src/gpu-compute/gpu_exec_context.cc @@ -53,7 +53,7 @@ GPUExecContext::wavefront() return wf; } -TheGpuISA::MiscReg +RegVal GPUExecContext::readMiscReg(int opIdx) const { assert(gpuISA); @@ -61,7 +61,7 @@ GPUExecContext::readMiscReg(int opIdx) const } void -GPUExecContext::writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal) +GPUExecContext::writeMiscReg(int opIdx, RegVal operandVal) { assert(gpuISA); gpuISA->writeMiscReg(opIdx, operandVal); diff --git a/src/gpu-compute/gpu_exec_context.hh b/src/gpu-compute/gpu_exec_context.hh index c5f9929b9..4f67dba47 100644 --- a/src/gpu-compute/gpu_exec_context.hh +++ b/src/gpu-compute/gpu_exec_context.hh @@ -37,6 +37,7 @@ #define __GPU_EXEC_CONTEXT_HH__ #include "arch/gpu_isa.hh" +#include "base/types.hh" #include "config/the_gpu_isa.hh" class ComputeUnit; @@ -49,8 +50,8 @@ class GPUExecContext Wavefront* wavefront(); ComputeUnit* computeUnit(); - TheGpuISA::MiscReg readMiscReg(int opIdx) const; - void writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal); + RegVal readMiscReg(int opIdx) const; + void writeMiscReg(int opIdx, RegVal operandVal); protected: ComputeUnit *cu; diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc index dbf7d2628..9e07b0547 100644 --- a/src/gpu-compute/gpu_tlb.cc +++ b/src/gpu-compute/gpu_tlb.cc @@ -617,7 +617,7 @@ namespace X86ISA //The index is multiplied by the size of a MiscReg so that //any memory dependence calculations will not see these as //overlapping. - req->setPaddr(regNum * sizeof(MiscReg)); + req->setPaddr(regNum * sizeof(RegVal)); return NoFault; } else if (prefix == IntAddrPrefixIO) { // TODO If CPL > IOPL or in virtual mode, check the I/O permission @@ -630,7 +630,7 @@ namespace X86ISA if (IOPort == 0xCF8 && req->getSize() == 4) { req->setFlags(Request::MMAPPED_IPR); - req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); + req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal)); } else if ((IOPort & ~mask(2)) == 0xCFC) { req->setFlags(Request::UNCACHEABLE); diff --git a/src/sim/process.cc b/src/sim/process.cc index 5e9c2b5e7..62959b4c5 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -156,7 +156,7 @@ Process::Process(ProcessParams *params, EmulationPageTable *pTable, void Process::clone(ThreadContext *otc, ThreadContext *ntc, - Process *np, TheISA::IntReg flags) + Process *np, RegVal flags) { #ifndef CLONE_VM #define CLONE_VM 0 @@ -423,7 +423,7 @@ Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault) desc->doSyscall(callnum, this, tc, fault); } -IntReg +RegVal Process::getSyscallArg(ThreadContext *tc, int &i, int width) { return getSyscallArg(tc, i); diff --git a/src/sim/process.hh b/src/sim/process.hh index cb2a3e2be..c690e825e 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -73,10 +73,9 @@ class Process : public SimObject DrainState drain() override; virtual void syscall(int64_t callnum, ThreadContext *tc, Fault *fault); - virtual TheISA::IntReg getSyscallArg(ThreadContext *tc, int &i) = 0; - virtual TheISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width); - virtual void setSyscallArg(ThreadContext *tc, int i, - TheISA::IntReg val) = 0; + virtual RegVal getSyscallArg(ThreadContext *tc, int &i) = 0; + virtual RegVal getSyscallArg(ThreadContext *tc, int &i, int width); + virtual void setSyscallArg(ThreadContext *tc, int i, RegVal val) = 0; virtual void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value) = 0; virtual SyscallDesc *getDesc(int callnum) = 0; @@ -163,7 +162,7 @@ class Process : public SimObject ThreadContext *new_tc, bool alloc_page); virtual void clone(ThreadContext *old_tc, ThreadContext *new_tc, - Process *new_p, TheISA::IntReg flags); + Process *new_p, RegVal flags); // thread contexts associated with this process std::vector<ContextID> contextIds; diff --git a/src/sim/syscall_desc.cc b/src/sim/syscall_desc.cc index 3696c1719..841998da5 100644 --- a/src/sim/syscall_desc.cc +++ b/src/sim/syscall_desc.cc @@ -49,7 +49,7 @@ void SyscallDesc::doSyscall(int callnum, Process *process, ThreadContext *tc, Fault *fault) { - TheISA::IntReg arg[6] M5_VAR_USED; + RegVal arg[6] M5_VAR_USED; /** * Step through the first six parameters for the system call and diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index 91e115de0..3f06869aa 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -1275,8 +1275,8 @@ cloneFunc(SyscallDesc *desc, int callnum, Process *p, ThreadContext *tc) { int index = 0; - TheISA::IntReg flags = p->getSyscallArg(tc, index); - TheISA::IntReg newStack = p->getSyscallArg(tc, index); + RegVal flags = p->getSyscallArg(tc, index); + RegVal newStack = p->getSyscallArg(tc, index); Addr ptidPtr = p->getSyscallArg(tc, index); #if THE_ISA == RISCV_ISA or THE_ISA == ARM_ISA |