diff options
| -rw-r--r-- | arch/alpha/isa_desc | 6 | ||||
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.hh | 11 |
2 files changed, 17 insertions, 0 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 6a95b4e04..46fb306a4 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1854,6 +1854,9 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); + 0x20: copy_load({{EA = Ra;}}, + {{memAccessObj->copySrcTranslate(EA);}}, + IsMemRef, IsLoad, IsCopy); } format LoadOrPrefetch { @@ -1873,6 +1876,9 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); + 0x24: copy_store({{EA = Rb;}}, + {{memAccessObj->copy(EA);}}, + IsMemRef, IsStore, IsCopy); } format StoreCond { diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 2b881509c..4bdc69ad1 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -246,6 +246,17 @@ class SimpleCPU : public BaseCPU { // need to do this... } + + void copySrcTranslate(Addr src) + { + panic("Haven't implemented Copy Src translate yet in SimpleCPU\n"); + } + + void copy(Addr dest) + { + panic("Haven't implemented Copy yet in SimpleCPU\n"); + } + }; #endif // __SIMPLE_CPU_HH__ |