diff options
| -rw-r--r-- | src/arch/arm/miscregs.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 45233a764..d100efb8e 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -93,6 +93,10 @@ namespace ArmISA Bitfield<4, 0> mode; EndBitUnion(CPSR) + // This mask selects bits of the CPSR that actually go in the CondCodes + // integer register to allow renaming. + static const uint32_t CondCodesMask = 0xF80F0000; + BitUnion32(SCTLR) Bitfield<30> te; // Thumb Exception Enable Bitfield<29> afe; // Access flag enable |