diff options
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 8 | ||||
| -rw-r--r-- | src/arch/sparc/isa/formats/integerop.isa | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 304c97f2f..3c5236661 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -106,7 +106,7 @@ decode OP default Unknown::unknown() } } //SETHI (or NOP if rd == 0 and imm == 0) - 0x4: SetHi::sethi({{Rd = imm;}}); + 0x4: SetHi::sethi({{Rd.udw = imm;}}); 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); } @@ -535,15 +535,15 @@ decode OP default Unknown::unknown() 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 0x14: Trap::array32({{fault = new IllegalInstruction;}}); - 0x18: BasicOperate::alignaddress({{ + 0x18: BasicOperate::alignaddr({{ uint64_t sum = Rs1 + Rs2; - Frd = sum & ~7; + Rd = sum & ~7; Gsr = (Gsr & ~7) | (sum & 7); }}); 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 0x1A: BasicOperate::alignaddresslittle({{ uint64_t sum = Rs1 + Rs2; - Frd = sum & ~7; + Rd = sum & ~7; Gsr = (Gsr & ~7) | ((~sum + 1) & 7); }}); 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index 27616216e..83c7e6958 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -67,7 +67,7 @@ output header {{ { } - int32_t imm; + int64_t imm; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; |