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-rw-r--r--configs/example/se.py1
-rw-r--r--configs/ruby/Ruby.py5
-rw-r--r--src/arch/arm/vtophys.hh1
-rw-r--r--src/arch/mips/vtophys.hh1
-rw-r--r--src/arch/power/vtophys.hh1
-rw-r--r--src/arch/sparc/vtophys.hh4
-rw-r--r--src/cpu/inorder/thread_context.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context.hh2
-rw-r--r--src/cpu/simple_thread.hh2
-rw-r--r--src/kern/solaris/solaris.hh2
-rw-r--r--src/mem/ruby/system/RubyPort.cc3
-rw-r--r--src/mem/ruby/system/RubyPort.hh2
-rw-r--r--tests/configs/memtest-ruby.py4
-rw-r--r--tests/configs/o3-timing-mp-ruby.py2
-rw-r--r--tests/configs/o3-timing-ruby.py3
-rw-r--r--tests/configs/rubytest-ruby.py3
-rw-r--r--tests/configs/simple-atomic-mp-ruby.py2
-rw-r--r--tests/configs/simple-timing-mp-ruby.py3
-rw-r--r--tests/configs/simple-timing-ruby.py3
19 files changed, 13 insertions, 33 deletions
diff --git a/configs/example/se.py b/configs/example/se.py
index 1edd99e9b..35025a8ff 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -181,7 +181,6 @@ if options.ruby:
options.use_map = True
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
- system.system_port = system.ruby._sys_port_proxy.port
else:
system.system_port = system.membus.port
system.physmem.port = system.membus.port
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index b2342eed4..920eac019 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -105,6 +105,10 @@ def create_system(options, system, piobus = None, dma_devices = []):
# full-fledged controller
system.sys_port_proxy = sys_port_proxy
+ # Connect the system port for loading of binaries etc
+ system.system_port = system.sys_port_proxy.port
+
+
#
# Set the network classes based on the command line options
#
@@ -182,5 +186,4 @@ def create_system(options, system, piobus = None, dma_devices = []):
ruby.profiler = ruby_profiler
ruby.mem_size = total_mem_size
ruby._cpu_ruby_ports = cpu_sequencers
- ruby._sys_port_proxy = sys_port_proxy
ruby.random_seed = options.random_seed
diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh
index a85209a4a..12a6c6ec6 100644
--- a/src/arch/arm/vtophys.hh
+++ b/src/arch/arm/vtophys.hh
@@ -38,7 +38,6 @@
#include "arch/arm/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace ArmISA {
inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 37a7378a8..a3fbdd457 100644
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -38,7 +38,6 @@
#include "arch/mips/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace MipsISA {
Addr vtophys(Addr vaddr);
diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index a2582b296..51696d9b2 100644
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -40,7 +40,6 @@
#include "arch/power/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace PowerISA {
diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh
index f55967b53..7c1d23e80 100644
--- a/src/arch/sparc/vtophys.hh
+++ b/src/arch/sparc/vtophys.hh
@@ -36,13 +36,9 @@
#include "arch/sparc/pagetable.hh"
class ThreadContext;
-class FunctionalPort;
namespace SparcISA {
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
-
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 7fe0fb5ef..5a9cfce32 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -44,8 +44,6 @@ namespace Kernel {
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the InOrderCPU. It
* provides the interface for any external objects to access a
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index ff6ca0093..ffe828c94 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -40,8 +40,6 @@ namespace Kernel {
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the O3CPU. It
* provides the interface for any external objects to access a
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index f2132dc36..97964c0e8 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -57,8 +57,6 @@ class BaseCPU;
class FunctionProfile;
class ProfileNode;
-class PhysicalPort;
-class TranslatingPort;
namespace TheISA {
namespace Kernel {
diff --git a/src/kern/solaris/solaris.hh b/src/kern/solaris/solaris.hh
index da6ce84f7..9cd5af16f 100644
--- a/src/kern/solaris/solaris.hh
+++ b/src/kern/solaris/solaris.hh
@@ -34,8 +34,6 @@
#include "base/types.hh"
#include "kern/operatingsystem.hh"
-class TranslatingPort;
-
///
/// This class encapsulates the types, structures, constants,
/// functions, and syscall-number mappings specific to the Solaris
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index b60ca2a07..af414f17a 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -88,8 +88,7 @@ RubyPort::getPort(const std::string &if_name, int idx)
// RubyPort should only have one port to physical memory
assert (physMemPort == NULL);
- physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
- ruby_system, access_phys_mem);
+ physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this);
return physMemPort;
}
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 2ffdef3d9..6df713a13 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -155,7 +155,7 @@ class RubyPort : public MemObject
uint16_t m_port_id;
uint64_t m_request_cnt;
- M5Port* physMemPort;
+ PioPort* physMemPort;
/*! Vector of CPU Port attached to this Ruby port. */
typedef std::vector<M5Port*>::iterator CpuPortIter;
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 52eb52904..43031dd02 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -106,10 +106,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
#
ruby_port.access_phys_mem = False
-
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 2f8829db0..cff511bf8 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -46,6 +46,8 @@ for cpu in cpus:
# connect memory to membus
system.physmem.port = system.membus.port
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
# -----------------------
# run simulation
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index b967a5080..14b0ff1ab 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -43,4 +43,7 @@ system = System(cpu = cpu,
system.physmem.port = system.membus.port
cpu.connectAllPorts(system.membus)
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
+
root = Root(full_system = False, system = system)
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 2531a30c8..116afa2b6 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -102,9 +102,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
#
ruby_port.access_phys_mem = False
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index fe0311801..8b61fd1f2 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -47,6 +47,8 @@ for cpu in cpus:
# connect memory to membus
system.physmem.port = system.membus.port
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
# -----------------------
# run simulation
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index c57ffd1f2..9919cabcb 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -85,9 +85,6 @@ for (i, cpu) in enumerate(system.cpu):
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 46436d18c..4f812f209 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -81,9 +81,6 @@ assert(len(system.ruby._cpu_ruby_ports) == 1)
#
cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 00:42:00 +0000