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-rw-r--r--arch/alpha/isa_desc24
-rw-r--r--arch/alpha/isa_traits.hh2
-rwxr-xr-xarch/isa_parser.py2
-rw-r--r--cpu/pc_event.cc2
-rw-r--r--cpu/static_inst.hh6
-rw-r--r--sim/sim_events.cc2
-rw-r--r--util/emacs/m5-c-style.el39
7 files changed, 58 insertions, 19 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 53f279b4e..e9b93a895 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -26,7 +26,7 @@ let {{
#include "cpu/exec_context.hh"
#include "cpu/simple_cpu/simple_cpu.hh"
#include "cpu/full_cpu/spec_state.hh"
-#include "cpu/full_cpu/cpu.hh"
+#include "cpu/full_cpu/full_cpu.hh"
#include "cpu/exetrace.hh"
#include "sim/annotation.hh"
@@ -256,7 +256,7 @@ def template BasicDeclare {{
return fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
DynInst *memAccessObj __attribute__((unused)) = dynInst;
@@ -320,7 +320,7 @@ declare {{
return No_Fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
return No_Fault;
@@ -643,7 +643,7 @@ def template FloatingPointDeclare {{
return fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
Fault fault = No_Fault;
@@ -701,7 +701,7 @@ def template FloatingPointDeclare {{
return fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
Fault fault = No_Fault;
@@ -830,7 +830,7 @@ declare {{
Trace::InstRecord *traceData)
{ panic("attempt to execute eacomp"); }
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{ panic("attempt to execute eacomp"); }
};
@@ -852,7 +852,7 @@ declare {{
Trace::InstRecord *traceData)
{ panic("attempt to execute memacc"); }
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{ panic("attempt to execute memacc"); }
};
@@ -952,7 +952,7 @@ def template LoadStoreDeclare {{
return fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
DynInst *memAccessObj = dynInst;
@@ -1019,7 +1019,7 @@ def template PrefetchDeclare {{
return No_Fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
Addr EA;
@@ -1544,7 +1544,7 @@ declare {{
return Unimplemented_Opcode_Fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
// don't panic if this is a misspeculated instruction
@@ -1594,7 +1594,7 @@ declare {{
return No_Fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
if (!xc->spec_mode && !warned) {
@@ -1665,7 +1665,7 @@ declare {{
return Unimplemented_Opcode_Fault;
}
- Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData)
{
// don't panic if this is a misspeculated instruction
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 9840636e0..6b78722ad 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -33,7 +33,7 @@
#include "targetarch/faults.hh"
#include "base/misc.hh"
-class CPU;
+class FullCPU;
class IniFile;
#define TARGET_ALPHA
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 1c3cb6c4e..2e3c0df35 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -279,7 +279,7 @@ def p_specification(t):
* RCS %(local_rcs_id)s
*/
-#include "bitfield.hh" // required for bitfield support
+#include "base/bitfield.hh" // required for bitfield support
/////////////////////////////////////
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index a275c2c41..4a037663c 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -42,8 +42,8 @@
#include "targetarch/pmap.h"
#include "kern/tru64/kernel.hh"
#include "mem/functional_mem/memory_control.hh"
-#include "cpu/full_cpu/cpu.hh"
#include "sim/system.hh"
+#include "cpu/base_cpu.hh"
#include "cpu/full_cpu/bpred.hh"
#endif
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 343a3d9b7..644c7dfc4 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -43,7 +43,7 @@
class ExecContext;
class SpecExecContext;
class SimpleCPU;
-class CPU;
+class FullCPU;
class DynInst;
class SymbolTable;
@@ -295,9 +295,9 @@ class StaticInst : public StaticInstBase
Trace::InstRecord *traceData) = 0;
/**
- * Execute this instruction under detailed CPU model.
+ * Execute this instruction under detailed FullCPU model.
*/
- virtual Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+ virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
Trace::InstRecord *traceData) = 0;
/**
diff --git a/sim/sim_events.cc b/sim/sim_events.cc
index 98480e76b..b622cb14d 100644
--- a/sim/sim_events.cc
+++ b/sim/sim_events.cc
@@ -28,7 +28,7 @@
#include <string>
-#include "cpu/full_cpu/cpu.hh"
+#include "sim/param.hh"
#include "sim/eventq.hh"
#include "base/hostinfo.hh"
#include "sim/sim_events.hh"
diff --git a/util/emacs/m5-c-style.el b/util/emacs/m5-c-style.el
new file mode 100644
index 000000000..7f25e9f5f
--- /dev/null
+++ b/util/emacs/m5-c-style.el
@@ -0,0 +1,39 @@
+; Copyright (c) 2003 The Regents of The University of Michigan
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are
+; met: redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer;
+; redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution;
+; neither the name of the copyright holders nor the names of its
+; contributors may be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; Authors: Nathan Binkert
+; Steve Reinhardt
+
+(c-add-style "m5"
+ '((c-basic-offset . 4)
+ (c-offsets-alist . ((substatement-open . 0)
+ (inline-open . 0)
+ (block-open . -4)
+ (case-label . 2)
+ (label . 2)
+ (statement-case-intro . 2)
+ (statement-case-open . 2)
+ (access-label . -2)))))
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