diff options
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 8 | ||||
| -rw-r--r-- | src/arch/sparc/tlb.cc | 4 |
2 files changed, 5 insertions, 7 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 57e0857f1..e56e9d81d 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -479,10 +479,10 @@ decode OP default Unknown::unknown() 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); //0x12 should cause an illegal instruction exception 0x13: NoPriv::rdgsr({{ - if(Fprs<2:> == 0 || Pstate<4:> == 0) - Rd = Gsr; - else - fault = new FpDisabled; + fault = checkFpEnableFault(xc); + if (fault) + return fault; + Rd = Gsr; }}); //0x14-0x15 should cause an illegal instruction exception 0x16: Priv::rdsoftint({{Rd = Softint;}}); diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index ebc8c0e7a..293f667d6 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -668,8 +668,6 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) if (!implicit && asi != ASI_P && asi != ASI_S) { if (AsiIsLittle(asi)) panic("Little Endian ASIs not supported\n"); - if (AsiIsBlock(asi)) - panic("Block ASIs not supported\n"); if (AsiIsNoFault(asi)) panic("No Fault ASIs not supported\n"); @@ -688,7 +686,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) goto handleSparcErrorRegAccess; if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && - !AsiIsTwin(asi)) + !AsiIsTwin(asi) && !AsiIsBlock(asi)) panic("Accessing ASI %#X. Should we?\n", asi); } |