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-rw-r--r--src/arch/alpha/ev5.cc44
-rw-r--r--src/arch/alpha/ev5.hh7
-rw-r--r--src/arch/alpha/faults.cc4
-rw-r--r--src/arch/alpha/isa/fp.isa2
-rw-r--r--src/arch/alpha/system.cc2
-rw-r--r--src/arch/alpha/tlb.cc1
-rw-r--r--src/arch/alpha/tlb.hh4
-rw-r--r--src/arch/alpha/vtophys.cc2
-rwxr-xr-xsrc/arch/mips/mips_core_specific.cc4
-rwxr-xr-xsrc/arch/mips/system.cc2
-rw-r--r--src/kern/tru64/tru64_events.cc2
11 files changed, 35 insertions, 39 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 33306d6af..83900349e 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -44,9 +44,9 @@
#include "sim/debug.hh"
#include "sim/sim_exit.hh"
-#if FULL_SYSTEM
+using namespace AlphaISA;
-using namespace EV5;
+#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
@@ -146,13 +146,13 @@ SimpleThread::hwrei()
int
AlphaISA::MiscRegFile::getInstAsid()
{
- return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
+ return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
AlphaISA::MiscRegFile::getDataAsid()
{
- return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+ return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
#endif
@@ -168,7 +168,7 @@ AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
tc->setMiscRegNoEffect(i, 0);
}
- tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
+ tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
@@ -477,27 +477,27 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
ipr[idx] = val;
tc->getDTBPtr()->flushAddr(val,
- EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+ AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
break;
case AlphaISA::IPR_DTB_TAG: {
struct AlphaISA::TlbEntry entry;
// FIXME: granularity hints NYI...
- if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
+ if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- entry.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
+ entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
tc->getDTBPtr()->insert(val, entry);
@@ -508,20 +508,20 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
struct AlphaISA::TlbEntry entry;
// FIXME: granularity hints NYI...
- if (EV5::ITB_PTE_GH(val) != 0)
+ if (AlphaISA::ITB_PTE_GH(val) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- entry.ppn = EV5::ITB_PTE_PPN(val);
- entry.xre = EV5::ITB_PTE_XRE(val);
+ entry.ppn = AlphaISA::ITB_PTE_PPN(val);
+ entry.xre = AlphaISA::ITB_PTE_XRE(val);
entry.xwe = 0;
- entry.fonr = EV5::ITB_PTE_FONR(val);
- entry.fonw = EV5::ITB_PTE_FONW(val);
- entry.asma = EV5::ITB_PTE_ASMA(val);
- entry.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
+ entry.fonr = AlphaISA::ITB_PTE_FONR(val);
+ entry.fonw = AlphaISA::ITB_PTE_FONW(val);
+ entry.asma = AlphaISA::ITB_PTE_ASMA(val);
+ entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
@@ -547,7 +547,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
ipr[idx] = val;
tc->getITBPtr()->flushAddr(val,
- EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
+ AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
break;
default:
diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh
index 4dd225786..4fe5f1b71 100644
--- a/src/arch/alpha/ev5.hh
+++ b/src/arch/alpha/ev5.hh
@@ -36,10 +36,7 @@
#include "config/alpha_tlaser.hh"
#include "arch/alpha/isa_traits.hh"
-namespace EV5 {
-
-//It seems like a safe assumption EV5 only applies to alpha
-using namespace AlphaISA;
+namespace AlphaISA {
#if ALPHA_TLASER
const uint64_t AsnMask = ULL(0x7f);
@@ -120,6 +117,6 @@ inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
const Addr PalBase = 0x4000;
const Addr PalMax = 0x10000;
-/* namespace EV5 */ }
+} // namespace AlphaISA
#endif // __ARCH_ALPHA_EV5_HH__
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 20591b357..7417ada5f 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -148,8 +148,8 @@ void DtbFault::invoke(ThreadContext * tc)
// set MM_STAT register flags
tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
- (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
- | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
+ (((AlphaISA::Opcode(tc->getInst()) & 0x3f) << 11)
+ | ((AlphaISA::Ra(tc->getInst()) & 0x1f) << 6)
| (flags & 0x3f)));
// set VA_FORM register with faulting formatted address
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 773e7d10c..8b13f8dd7 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
- if (!EV5::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
+ if (!AlphaISA::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
fault = new FloatEnableFault;
}
return fault;
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index f8fea4fee..63efef4a0 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -190,7 +190,7 @@ AlphaSystem::setAlphaAccess(Addr access)
{
Addr addr = 0;
if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
- virtPort.write(addr, htog(EV5::Phys2K0Seg(access)));
+ virtPort.write(addr, htog(AlphaISA::Phys2K0Seg(access)));
} else
panic("could not find m5AlphaAccess\n");
}
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 60502ebdb..2694cf38f 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -43,7 +43,6 @@
#include "cpu/thread_context.hh"
using namespace std;
-using namespace EV5;
namespace AlphaISA {
///////////////////////////////////////////////////////////////////////
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index f94d06ccd..98f845e21 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -88,8 +88,8 @@ namespace AlphaISA
// static helper functions... really EV5 VM traits
static bool validVirtualAddress(Addr vaddr) {
// unimplemented bits must be all 0 or all 1
- Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
- return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
+ Addr unimplBits = vaddr & AlphaISA::VAddrUnImplMask;
+ return (unimplBits == 0) || (unimplBits == AlphaISA::VAddrUnImplMask);
}
static Fault checkCacheability(RequestPtr &req, bool itb = false);
diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc
index 6ffbea181..439af3bd7 100644
--- a/src/arch/alpha/vtophys.cc
+++ b/src/arch/alpha/vtophys.cc
@@ -92,7 +92,7 @@ AlphaISA::vtophys(ThreadContext *tc, Addr addr)
Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code
//so I put it back in. Perhaps something to do with gdb debugging?
- if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
+ if (AlphaISA::PcPAL(vaddr) && (vaddr < AlphaISA::PalMax)) {
paddr = vaddr & ~ULL(1);
} else {
if (AlphaISA::IsK0Seg(vaddr)) {
diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc
index a17ebcdf3..80d856b0c 100755
--- a/src/arch/mips/mips_core_specific.cc
+++ b/src/arch/mips/mips_core_specific.cc
@@ -113,13 +113,13 @@ MipsISA::processInterrupts(CPU *cpu)
/*int
MipsISA::MiscRegFile::getInstAsid()
{
- return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
+ return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
MipsISA::MiscRegFile::getDataAsid()
{
- return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+ return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}*/
diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc
index bf86bb030..73bc33161 100755
--- a/src/arch/mips/system.cc
+++ b/src/arch/mips/system.cc
@@ -185,7 +185,7 @@ MipsSystem::setMipsAccess(Addr access)
{
Addr addr = 0;
if (consoleSymtab->findAddress("m5MipsAccess", addr)) {
- // virtPort.write(addr, htog(EV5::Phys2K0Seg(access)));
+ // virtPort.write(addr, htog(AlphaISA::Phys2K0Seg(access)));
} else
panic("could not find m5MipsAccess\n");
}
diff --git a/src/kern/tru64/tru64_events.cc b/src/kern/tru64/tru64_events.cc
index c798c3ced..9fa770c4d 100644
--- a/src/kern/tru64/tru64_events.cc
+++ b/src/kern/tru64/tru64_events.cc
@@ -61,7 +61,7 @@ BadAddrEvent::process(ThreadContext *tc)
tc->getPhysPort()->getPeerAddressRanges(resp, snoop);
for(iter = resp.begin(); iter != resp.end(); iter++)
{
- if (*iter == (TheISA::K0Seg2Phys(a0) & EV5::PAddrImplMask))
+ if (*iter == (TheISA::K0Seg2Phys(a0) & AlphaISA::PAddrImplMask))
found = true;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 17:11:31 +0000