diff options
| -rw-r--r-- | src/arch/alpha/ev5.cc | 11 | ||||
| -rw-r--r-- | src/arch/alpha/utility.hh | 7 | ||||
| -rw-r--r-- | src/arch/arm/utility.hh | 7 | ||||
| -rw-r--r-- | src/arch/mips/utility.cc | 11 | ||||
| -rw-r--r-- | src/arch/mips/utility.hh | 3 | ||||
| -rw-r--r-- | src/arch/power/utility.hh | 7 | ||||
| -rw-r--r-- | src/arch/sparc/utility.hh | 7 | ||||
| -rw-r--r-- | src/arch/x86/utility.hh | 7 |
8 files changed, 0 insertions, 60 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 676d7a713..29910caa6 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -80,17 +80,6 @@ initCPU(ThreadContext *tc, int cpuId) delete reset; } -template <class CPU> -void -zeroRegisters(CPU *cpu) -{ - // Insure ISA semantics - // (no longer very clean due to the change in setIntReg() in the - // cpu model. Consider changing later.) - cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatReg(ZeroReg, 0); -} - //////////////////////////////////////////////////////////////////////// // // diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index bf585fdab..46af1217e 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -58,13 +58,6 @@ inUserMode(ThreadContext *tc) return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; } -/** - * Function to insure ISA semantics about 0 registers. - * @param tc The thread context. - */ -template <class TC> -void zeroRegisters(TC *tc); - // Alpha IPR register accessors inline bool PcPAL(Addr addr) { return addr & 0x3; } inline void startupCPU(ThreadContext *tc, int cpuId) diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 4d1348abc..538c83173 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -95,13 +95,6 @@ testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code) } } -/** - * Function to insure ISA semantics about 0 registers. - * @param tc The thread context. - */ -template <class TC> -void zeroRegisters(TC *tc); - inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(); diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 495845d7f..24c451d3e 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -217,17 +217,6 @@ isSnan(void *val_ptr, int size) } } -template <class CPU> -void -zeroRegisters(CPU *cpu) -{ - // Insure ISA semantics - // (no longer very clean due to the change in setIntReg() in the - // cpu model. Consider changing later.) - cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatReg(ZeroReg, 0); -} - void startupCPU(ThreadContext *tc, int cpuId) { diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index dde386cbc..0cd066f3e 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -87,9 +87,6 @@ inUserMode(ThreadContext *tc) } } -template <class CPU> -void zeroRegisters(CPU *cpu); - //////////////////////////////////////////////////////////////////////// // // Translation stuff diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh index 1a13d1e40..b41533e65 100644 --- a/src/arch/power/utility.hh +++ b/src/arch/power/utility.hh @@ -49,13 +49,6 @@ buildRetPC(const PCState &curPC, const PCState &callPC) return retPC; } -/** - * Function to ensure ISA semantics about 0 registers. - * @param tc The thread context. - */ -template <class TC> -void zeroRegisters(TC *tc); - inline void startupCPU(ThreadContext *tc, int cpuId) { diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index ae5799699..48476cb04 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -62,13 +62,6 @@ inUserMode(ThreadContext *tc) return !(pstate.priv || hpstate.hpriv); } -/** - * Function to insure ISA semantics about 0 registers. - * @param tc The thread context. - */ -template <class TC> -void zeroRegisters(TC *tc); - void initCPU(ThreadContext *tc, int cpuId); inline void diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 87d5cbb6c..c88a4c777 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -69,13 +69,6 @@ namespace X86ISA } } - /** - * Function to insure ISA semantics about 0 registers. - * @param tc The thread context. - */ - template <class TC> - void zeroRegisters(TC *tc); - void initCPU(ThreadContext *tc, int cpuId); void startupCPU(ThreadContext *tc, int cpuId); |