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-rw-r--r--src/arch/alpha/decoder.cc2
-rw-r--r--src/arch/alpha/decoder.hh8
-rw-r--r--src/arch/arm/decoder.cc2
-rw-r--r--src/arch/arm/decoder.hh5
-rw-r--r--src/arch/generic/SConscript31
-rw-r--r--src/arch/generic/decode_cache.cc (renamed from src/cpu/decode_cache.cc)70
-rw-r--r--src/arch/generic/decode_cache.hh63
-rw-r--r--src/arch/mips/decoder.cc2
-rw-r--r--src/arch/mips/decoder.hh6
-rw-r--r--src/arch/power/decoder.cc2
-rw-r--r--src/arch/power/decoder.hh8
-rw-r--r--src/arch/sparc/decoder.cc2
-rw-r--r--src/arch/sparc/decoder.hh6
-rw-r--r--src/arch/x86/decoder.cc21
-rw-r--r--src/arch/x86/decoder.hh13
-rw-r--r--src/cpu/SConscript1
-rw-r--r--src/cpu/decode_cache.hh107
17 files changed, 224 insertions, 125 deletions
diff --git a/src/arch/alpha/decoder.cc b/src/arch/alpha/decoder.cc
index 8cabe515d..e5a7663ff 100644
--- a/src/arch/alpha/decoder.cc
+++ b/src/arch/alpha/decoder.cc
@@ -33,6 +33,6 @@
namespace AlphaISA
{
-DecodeCache Decoder::defaultCache;
+GenericISA::BasicDecodeCache Decoder::defaultCache;
}
diff --git a/src/arch/alpha/decoder.hh b/src/arch/alpha/decoder.hh
index 4233c2d44..ef2f5856c 100644
--- a/src/arch/alpha/decoder.hh
+++ b/src/arch/alpha/decoder.hh
@@ -31,11 +31,13 @@
#ifndef __ARCH_ALPHA_DECODER_HH__
#define __ARCH_ALPHA_DECODER_HH__
+#include "arch/generic/decode_cache.hh"
#include "arch/types.hh"
-#include "cpu/decode_cache.hh"
-#include "cpu/static_inst_fwd.hh"
+#include "cpu/static_inst.hh"
#include "sim/full_system.hh"
+class ThreadContext;
+
namespace AlphaISA
{
@@ -99,7 +101,7 @@ class Decoder
protected:
/// A cache of decoded instruction objects.
- static DecodeCache defaultCache;
+ static GenericISA::BasicDecodeCache defaultCache;
public:
StaticInstPtr decodeInst(ExtMachInst mach_inst);
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 65badbc49..4001f7597 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -38,7 +38,7 @@
namespace ArmISA
{
-DecodeCache Decoder::defaultCache;
+GenericISA::BasicDecodeCache Decoder::defaultCache;
void
Decoder::process()
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index dd51fd082..a5f2c88a5 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -35,8 +35,9 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
+#include "arch/generic/decode_cache.hh"
#include "base/types.hh"
-#include "cpu/decode_cache.hh"
+#include "cpu/static_inst.hh"
class ThreadContext;
@@ -122,7 +123,7 @@ class Decoder
protected:
/// A cache of decoded instruction objects.
- static DecodeCache defaultCache;
+ static GenericISA::BasicDecodeCache defaultCache;
public:
StaticInstPtr decodeInst(ExtMachInst mach_inst);
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
new file mode 100644
index 000000000..f2edc805d
--- /dev/null
+++ b/src/arch/generic/SConscript
@@ -0,0 +1,31 @@
+# Copyright (c) 2012 Google
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+Import('*')
+
+Source('decode_cache.cc')
diff --git a/src/cpu/decode_cache.cc b/src/arch/generic/decode_cache.cc
index 636bf9284..7211ba355 100644
--- a/src/cpu/decode_cache.cc
+++ b/src/arch/generic/decode_cache.cc
@@ -28,86 +28,32 @@
* Authors: Gabe Black
*/
+#include "arch/generic/decode_cache.hh"
#include "arch/decoder.hh"
-#include "arch/isa_traits.hh"
#include "arch/types.hh"
-#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/static_inst.hh"
-void
-DecodeCache::DecodePages::update(PageIt recentest)
+namespace GenericISA
{
- recent[1] = recent[0];
- recent[0] = recentest;
-}
-
-void
-DecodeCache::DecodePages::addPage(Addr addr, DecodePage *page)
-{
- Addr page_addr = addr & ~(TheISA::PageBytes - 1);
- typename PageMap::value_type to_insert(page_addr, page);
- update(pageMap.insert(to_insert).first);
-}
-
-DecodeCache::DecodePages::DecodePages()
-{
- recent[0] = recent[1] = pageMap.end();
-}
-
-DecodeCache::DecodePage *
-DecodeCache::DecodePages::getPage(Addr addr)
-{
- Addr page_addr = addr & ~(TheISA::PageBytes - 1);
-
- // Check against recent lookups.
- if (recent[0] != pageMap.end()) {
- if (recent[0]->first == page_addr)
- return recent[0]->second;
- if (recent[1] != pageMap.end() &&
- recent[1]->first == page_addr) {
- update(recent[1]);
- // recent[1] has just become recent[0].
- return recent[0]->second;
- }
- }
-
- // Actually look in the has_map.
- PageIt it = pageMap.find(page_addr);
- if (it != pageMap.end()) {
- update(it);
- return it->second;
- }
-
- // Didn't find an existing page, so add a new one.
- DecodePage *newPage = new DecodePage;
- addPage(page_addr, newPage);
- return newPage;
-}
StaticInstPtr
-DecodeCache::decode(TheISA::Decoder *decoder,
- ExtMachInst mach_inst, Addr addr)
+BasicDecodeCache::decode(TheISA::Decoder *decoder,
+ TheISA::ExtMachInst mach_inst, Addr addr)
{
- // Try to find a matching address based table of instructions.
- DecodePage *page = decodePages.getPage(addr);
-
- // Use the table to decode the instruction. It will fall back to other
- // mechanisms if it needs to.
- Addr offset = addr & (TheISA::PageBytes - 1);
- StaticInstPtr si = page->insts[offset];
+ StaticInstPtr &si = decodePages.lookup(addr);
if (si && (si->machInst == mach_inst))
return si;
- InstMap::iterator iter = instMap.find(mach_inst);
+ DecodeCache::InstMap::iterator iter = instMap.find(mach_inst);
if (iter != instMap.end()) {
si = iter->second;
- page->insts[offset] = si;
return si;
}
si = decoder->decodeInst(mach_inst);
instMap[mach_inst] = si;
- page->insts[offset] = si;
return si;
}
+
+} // namespace GenericISA
diff --git a/src/arch/generic/decode_cache.hh b/src/arch/generic/decode_cache.hh
new file mode 100644
index 000000000..c6bce7226
--- /dev/null
+++ b/src/arch/generic/decode_cache.hh
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_GENERIC_DECODE_CACHE_HH__
+#define __ARCH_GENERIC_DECODE_CACHE_HH__
+
+#include "arch/types.hh"
+#include "config/the_isa.hh"
+#include "cpu/decode_cache.hh"
+#include "cpu/static_inst_fwd.hh"
+
+namespace TheISA
+{
+ class Decoder;
+}
+
+namespace GenericISA
+{
+
+class BasicDecodeCache
+{
+ private:
+ DecodeCache::InstMap instMap;
+ DecodeCache::AddrMap<StaticInstPtr> decodePages;
+
+ public:
+ /// Decode a machine instruction.
+ /// @param mach_inst The binary instruction to decode.
+ /// @retval A pointer to the corresponding StaticInst object.
+ StaticInstPtr decode(TheISA::Decoder * const decoder,
+ TheISA::ExtMachInst mach_inst, Addr addr);
+};
+
+} // namespace GenericISA
+
+#endif // __ARCH_GENERIC_DECODE_CACHE_HH__
diff --git a/src/arch/mips/decoder.cc b/src/arch/mips/decoder.cc
index 45b1f7184..dd4ba2be1 100644
--- a/src/arch/mips/decoder.cc
+++ b/src/arch/mips/decoder.cc
@@ -33,6 +33,6 @@
namespace MipsISA
{
-DecodeCache Decoder::defaultCache;
+GenericISA::BasicDecodeCache Decoder::defaultCache;
}
diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 95385961d..4857eb353 100644
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -31,11 +31,11 @@
#ifndef __ARCH_MIPS_DECODER_HH__
#define __ARCH_MIPS_DECODER_HH__
+#include "arch/generic/decode_cache.hh"
#include "arch/mips/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "cpu/decode_cache.hh"
-#include "cpu/static_inst_fwd.hh"
+#include "cpu/static_inst.hh"
class ThreadContext;
@@ -99,7 +99,7 @@ class Decoder
protected:
/// A cache of decoded instruction objects.
- static DecodeCache defaultCache;
+ static GenericISA::BasicDecodeCache defaultCache;
public:
StaticInstPtr decodeInst(ExtMachInst mach_inst);
diff --git a/src/arch/power/decoder.cc b/src/arch/power/decoder.cc
index 96fd9297b..1a6a3b38f 100644
--- a/src/arch/power/decoder.cc
+++ b/src/arch/power/decoder.cc
@@ -33,6 +33,6 @@
namespace PowerISA
{
-DecodeCache Decoder::defaultCache;
+GenericISA::BasicDecodeCache Decoder::defaultCache;
}
diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index c45473a90..60fc8ca75 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -31,9 +31,11 @@
#ifndef __ARCH_POWER_DECODER_HH__
#define __ARCH_POWER_DECODER_HH__
+#include "arch/generic/decode_cache.hh"
#include "arch/types.hh"
-#include "cpu/decode_cache.hh"
-#include "cpu/static_inst_fwd.hh"
+#include "cpu/static_inst.hh"
+
+class ThreadContext;
namespace PowerISA
{
@@ -105,7 +107,7 @@ class Decoder
}
protected:
/// A cache of decoded instruction objects.
- static DecodeCache defaultCache;
+ static GenericISA::BasicDecodeCache defaultCache;
public:
StaticInstPtr decodeInst(ExtMachInst mach_inst);
diff --git a/src/arch/sparc/decoder.cc b/src/arch/sparc/decoder.cc
index e8769a573..a7f7704ad 100644
--- a/src/arch/sparc/decoder.cc
+++ b/src/arch/sparc/decoder.cc
@@ -33,6 +33,6 @@
namespace SparcISA
{
-DecodeCache Decoder::defaultCache;
+GenericISA::BasicDecodeCache Decoder::defaultCache;
}
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index 999a605a7..ea0793286 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -31,10 +31,10 @@
#ifndef __ARCH_SPARC_DECODER_HH__
#define __ARCH_SPARC_DECODER_HH__
+#include "arch/generic/decode_cache.hh"
#include "arch/sparc/registers.hh"
#include "arch/types.hh"
-#include "cpu/decode_cache.hh"
-#include "cpu/static_inst_fwd.hh"
+#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
class ThreadContext;
@@ -109,7 +109,7 @@ class Decoder
protected:
/// A cache of decoded instruction objects.
- static DecodeCache defaultCache;
+ static GenericISA::BasicDecodeCache defaultCache;
public:
StaticInstPtr decodeInst(ExtMachInst mach_inst);
diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
index d7199fa82..5fb2dcaf4 100644
--- a/src/arch/x86/decoder.cc
+++ b/src/arch/x86/decoder.cc
@@ -408,6 +408,25 @@ Decoder::State Decoder::doImmediateState()
return nextState;
}
-DecodeCache Decoder::defaultCache;
+DecodeCache::InstMap Decoder::instMap;
+DecodeCache::AddrMap<StaticInstPtr> Decoder::decodePages;
+
+StaticInstPtr
+Decoder::decode(ExtMachInst mach_inst, Addr addr)
+{
+ StaticInstPtr &si = decodePages.lookup(addr);
+ if (si && (si->machInst == mach_inst))
+ return si;
+
+ DecodeCache::InstMap::iterator iter = instMap.find(mach_inst);
+ if (iter != instMap.end()) {
+ si = iter->second;
+ return si;
+ }
+
+ si = decodeInst(mach_inst);
+ instMap[mach_inst] = si;
+ return si;
+}
}
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 300e2238c..725d443d6 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -40,7 +40,7 @@
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/decode_cache.hh"
-#include "cpu/static_inst_fwd.hh"
+#include "cpu/static_inst.hh"
#include "debug/Decoder.hh"
class ThreadContext;
@@ -218,8 +218,9 @@ class Decoder
}
protected:
- /// A cache of decoded instruction objects.
- static DecodeCache defaultCache;
+ /// Caching for decoded instruction objects.
+ static DecodeCache::InstMap instMap;
+ static DecodeCache::AddrMap<StaticInstPtr> decodePages;
public:
StaticInstPtr decodeInst(ExtMachInst mach_inst);
@@ -227,11 +228,7 @@ class Decoder
/// Decode a machine instruction.
/// @param mach_inst The binary instruction to decode.
/// @retval A pointer to the corresponding StaticInst object.
- StaticInstPtr
- decode(ExtMachInst mach_inst, Addr addr)
- {
- return defaultCache.decode(this, mach_inst, addr);
- }
+ StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
StaticInstPtr
decode(X86ISA::PCState &nextPC)
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 4b327f8a1..e1ba59b8b 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -108,7 +108,6 @@ SimObject('NativeTrace.py')
Source('activity.cc')
Source('base.cc')
Source('cpuevent.cc')
-Source('decode_cache.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
diff --git a/src/cpu/decode_cache.hh b/src/cpu/decode_cache.hh
index 473340586..34387419f 100644
--- a/src/cpu/decode_cache.hh
+++ b/src/cpu/decode_cache.hh
@@ -35,56 +35,95 @@
#include "arch/types.hh"
#include "base/hashmap.hh"
#include "config/the_isa.hh"
-#include "cpu/static_inst.hh"
+#include "cpu/static_inst_fwd.hh"
namespace TheISA
{
class Decoder;
}
-class DecodeCache
+namespace DecodeCache
{
- private:
- typedef TheISA::ExtMachInst ExtMachInst;
- /// Hash of decoded instructions.
- typedef m5::hash_map<ExtMachInst, StaticInstPtr> InstMap;
- InstMap instMap;
- struct DecodePage {
- StaticInstPtr insts[TheISA::PageBytes];
+/// Hash for decoded instructions.
+typedef m5::hash_map<TheISA::ExtMachInst, StaticInstPtr> InstMap;
+
+/// A sparse map from an Addr to a Value, stored in page chunks.
+template<class Value>
+class AddrMap
+{
+ protected:
+ // A pages worth of cache entries.
+ struct CachePage {
+ Value items[TheISA::PageBytes];
};
+ // A map of cache pages which allows a sparse mapping.
+ typedef typename m5::hash_map<Addr, CachePage *> PageMap;
+ typedef typename PageMap::iterator PageIt;
+ // Mini cache of recent lookups.
+ PageIt recent[2];
+ PageMap pageMap;
+
+ /// Update the mini cache of recent lookups.
+ /// @param recentest The most recent result;
+ void
+ update(PageIt recentest)
+ {
+ recent[1] = recent[0];
+ recent[0] = recentest;
+ }
- /// A store of DecodePages. Basically a slightly smarter hash_map.
- class DecodePages
+ /// Attempt to find the CacheePage which goes with a particular
+ /// address. First check the small cache of recent results, then
+ /// actually look in the hash_map.
+ /// @param addr The address to look up.
+ CachePage *
+ getPage(Addr addr)
{
- protected:
- typedef typename m5::hash_map<Addr, DecodePage *> PageMap;
- typedef typename PageMap::iterator PageIt;
- PageIt recent[2];
- PageMap pageMap;
+ Addr page_addr = addr & ~(TheISA::PageBytes - 1);
- /// Update the small cache of recent lookups.
- /// @param recentest The most recent result;
- void update(PageIt recentest);
- void addPage(Addr addr, DecodePage *page);
+ // Check against recent lookups.
+ if (recent[0] != pageMap.end()) {
+ if (recent[0]->first == page_addr)
+ return recent[0]->second;
+ if (recent[1] != pageMap.end() &&
+ recent[1]->first == page_addr) {
+ update(recent[1]);
+ // recent[1] has just become recent[0].
+ return recent[0]->second;
+ }
+ }
- public:
- /// Constructor
- DecodePages();
+ // Actually look in the has_map.
+ PageIt it = pageMap.find(page_addr);
+ if (it != pageMap.end()) {
+ update(it);
+ return it->second;
+ }
- /// Attempt to find the DecodePage which goes with a particular
- /// address. First check the small cache of recent results, then
- /// actually look in the hash_map.
- /// @param addr The address to look up.
- DecodePage *getPage(Addr addr);
- } decodePages;
+ // Didn't find an existing page, so add a new one.
+ CachePage *newPage = new CachePage;
+ page_addr = page_addr & ~(TheISA::PageBytes - 1);
+ typename PageMap::value_type to_insert(page_addr, newPage);
+ update(pageMap.insert(to_insert).first);
+ return newPage;
+ }
public:
- /// Decode a machine instruction.
- /// @param mach_inst The binary instruction to decode.
- /// @retval A pointer to the corresponding StaticInst object.
- StaticInstPtr decode(TheISA::Decoder * const decoder,
- ExtMachInst mach_inst, Addr addr);
+ /// Constructor
+ AddrMap()
+ {
+ recent[0] = recent[1] = pageMap.end();
+ }
+
+ Value &
+ lookup(Addr addr)
+ {
+ CachePage *page = getPage(addr);
+ return page->items[addr & (TheISA::PageBytes - 1)];
+ }
};
+} // namespace DecodeCache
+
#endif // __CPU_DECODE_CACHE_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 14:37:34 +0000