diff options
| -rw-r--r-- | src/arch/generic/BaseTLB.py | 10 | ||||
| -rw-r--r-- | src/arch/generic/tlb.hh | 6 |
2 files changed, 11 insertions, 5 deletions
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py index 6a8a9727f..b98b99356 100644 --- a/src/arch/generic/BaseTLB.py +++ b/src/arch/generic/BaseTLB.py @@ -1,4 +1,5 @@ # Copyright (c) 2008 The Hewlett-Packard Development Company +# Copyright (c) 2018 Metempsy Technology Consulting # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -25,10 +26,15 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Gabe Black +# Ivan Pizarro -from m5.SimObject import SimObject +from m5.params import * +from MemObject import MemObject -class BaseTLB(SimObject): +class BaseTLB(MemObject): type = 'BaseTLB' abstract = True cxx_header = "arch/generic/tlb.hh" + # Ports to connect with other TLB levels + slave = VectorSlavePort("Port closer to the CPU side") + master = MasterPort("Port closer to memory side") diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh index 89180341c..91f8f867b 100644 --- a/src/arch/generic/tlb.hh +++ b/src/arch/generic/tlb.hh @@ -44,17 +44,17 @@ #define __ARCH_GENERIC_TLB_HH__ #include "base/logging.hh" +#include "mem/mem_object.hh" #include "mem/request.hh" -#include "sim/sim_object.hh" class ThreadContext; class BaseMasterPort; -class BaseTLB : public SimObject +class BaseTLB : public MemObject { protected: BaseTLB(const Params *p) - : SimObject(p) + : MemObject(p) {} public: |