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-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini10
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini8
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini8
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini22
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json41
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini28
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini22
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini28
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt2
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini22
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini22
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr8
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini22
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr4
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini10
-rw-r--r--tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini6
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini9
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt695
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini9
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt1130
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini14
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt621
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini14
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt845
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini14
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt623
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini9
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt1151
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini9
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt1091
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini3
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini9
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt1093
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini2
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini2
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini9
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt1056
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini9
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt1199
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr2
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini9
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt1464
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini9
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt1186
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini2
-rw-r--r--tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini2
-rw-r--r--tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini3
-rw-r--r--tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini7
-rw-r--r--tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini2
-rw-r--r--tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini2
-rw-r--r--tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini3
-rw-r--r--tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini7
-rw-r--r--tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini3
-rw-r--r--tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini7
-rw-r--r--tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini30
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini13
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini13
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr2
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr2
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr2
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr2
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini2
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr2
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini13
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest/config.ini13
-rw-r--r--tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini2
-rw-r--r--tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini2
-rw-r--r--tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini2
-rw-r--r--tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini2
-rw-r--r--tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini2
-rwxr-xr-xtests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr2
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini2
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr2
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini2
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr2
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini2
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr2
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini2
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr2
-rw-r--r--tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini2
-rwxr-xr-xtests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr2
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini2
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini3
-rw-r--r--tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini7
-rw-r--r--tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini3
-rw-r--r--tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini7
144 files changed, 6746 insertions, 6172 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 9073173b3..0273820c3 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -34,6 +34,8 @@ readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -108,7 +110,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -150,7 +151,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -242,7 +242,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -284,7 +283,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -418,7 +416,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -455,7 +452,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -490,6 +486,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -559,6 +556,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 2611d2bca..aa9e19faa 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -11,4 +11,4 @@ info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
-Exiting @ tick 1869358498000 because m5_exit instruction encountered
+Exiting @ tick 1869357988000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 89e440df7..1095edb8d 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -34,6 +34,8 @@ readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -108,7 +110,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -150,7 +151,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -201,7 +201,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -236,6 +235,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -344,7 +344,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -379,6 +378,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 29ef5c756..4a2adcc51 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -10,4 +10,4 @@ Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1829332273500 because m5_exit instruction encountered
+Exiting @ tick 1829331993500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index c94aa8f96..77849776c 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -34,6 +34,8 @@ readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 0500c7948..f5633e63a 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -34,6 +34,8 @@ readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -104,7 +106,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -146,7 +147,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -197,7 +197,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -232,6 +231,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -340,7 +340,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -375,6 +374,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
index c979f0275..59c5ae050 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
@@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -146,7 +148,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -224,7 +225,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -337,7 +337,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -372,6 +371,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -434,7 +434,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -469,6 +468,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -637,6 +637,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
+thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@@ -1024,8 +1025,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
+thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@@ -1071,6 +1073,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
index 1eb19f804..f56eeb549 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
@@ -64,7 +64,9 @@
"symbolfile": "",
"readfile": "/z/atgutier/gem5/gem5-commit/tests/halt.sh",
"have_large_asid_64": false,
+ "thermal_model": null,
"phys_addr_range_64": 40,
+ "work_begin_exit_count": 0,
"have_lpae": false,
"cxx_class": "LinuxArmSystem",
"load_offset": 2147483648,
@@ -523,10 +525,6 @@
"freq": 20000,
"type": "RealViewOsc"
},
- "type": "SubSystem",
- "eventq_index": 0,
- "cxx_class": "SubSystem",
- "path": "system.realview.mcc",
"osc_clcd": {
"position": 0,
"name": "osc_clcd",
@@ -541,6 +539,24 @@
"freq": 42105,
"type": "RealViewOsc"
},
+ "thermal_domain": null,
+ "eventq_index": 0,
+ "cxx_class": "SubSystem",
+ "path": "system.realview.mcc",
+ "temp_crtl": {
+ "system": "system",
+ "position": 0,
+ "name": "temp_crtl",
+ "parent": "system.realview.realview_io",
+ "dcc": 0,
+ "site": 0,
+ "eventq_index": 0,
+ "cxx_class": "RealViewTemperatureSensor",
+ "device": 0,
+ "path": "system.realview.mcc.temp_crtl",
+ "type": "RealViewTemperatureSensor"
+ },
+ "type": "SubSystem",
"osc_system_bus": {
"position": 0,
"name": "osc_system_bus",
@@ -572,6 +588,7 @@
"freq": 25000,
"type": "RealViewOsc"
},
+ "thermal_domain": null,
"osc_sys": {
"position": 0,
"name": "osc_sys",
@@ -1139,6 +1156,7 @@
"type": "IsaFake",
"ret_data16": 65535
},
+ "point_of_coherency": true,
"snoop_filter": null,
"forward_latency": 4,
"clk_domain": "system.clk_domain",
@@ -1200,11 +1218,10 @@
"role": "MASTER"
},
"type": "Cache",
- "forward_snoops": false,
"writeback_clean": false,
"hit_latency": 50,
- "tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
+ "tgts_per_mshr": 12,
"addr_ranges": [
"2147483648:2415919103"
],
@@ -1381,6 +1398,7 @@
"role": "SLAVE"
},
"name": "toL2Bus",
+ "point_of_coherency": false,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
@@ -1451,11 +1469,10 @@
"role": "MASTER"
},
"type": "Cache",
- "forward_snoops": true,
"writeback_clean": true,
"hit_latency": 2,
- "tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
+ "tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
],
@@ -1544,11 +1561,10 @@
"role": "MASTER"
},
"type": "Cache",
- "forward_snoops": true,
"writeback_clean": false,
"hit_latency": 20,
- "tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
+ "tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
],
@@ -1627,11 +1643,10 @@
"role": "MASTER"
},
"type": "Cache",
- "forward_snoops": true,
"writeback_clean": false,
"hit_latency": 2,
- "tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
+ "tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
],
@@ -1690,7 +1705,7 @@
],
"gic_cpu_addr": 738205696,
"work_cpus_ckpt_count": 0,
- "work_begin_exit_count": 0,
+ "thermal_components": [],
"machine_type": "VExpress_EMM",
"flags_addr": 469827632,
"path": "system",
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index f038e832c..010d82106 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -146,7 +148,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -224,7 +225,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
@@ -337,7 +337,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
@@ -397,6 +396,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -465,7 +465,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -543,7 +542,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
@@ -656,7 +654,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
@@ -716,6 +713,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -778,7 +776,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -815,7 +812,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -850,6 +846,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -1018,6 +1015,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
+thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@@ -1405,8 +1403,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
+thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@@ -1452,6 +1451,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@@ -1675,6 +1684,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index c979f0275..59c5ae050 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -146,7 +148,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -224,7 +225,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -337,7 +337,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -372,6 +371,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -434,7 +434,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -469,6 +468,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -637,6 +637,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
+thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@@ -1024,8 +1025,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
+thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@@ -1071,6 +1073,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 527014097..5946c71cf 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -142,7 +144,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -220,7 +221,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
@@ -333,7 +333,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
@@ -393,6 +392,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -457,7 +457,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -535,7 +534,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
@@ -648,7 +646,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
@@ -708,6 +705,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -770,7 +768,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -807,7 +804,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -842,6 +838,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -1074,6 +1071,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
+thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@@ -1461,8 +1459,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
+thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@@ -1508,6 +1507,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@@ -1731,6 +1740,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index b7a9648fc..abcd4eac1 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1082,6 +1082,7 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks
system.cpu0.l2cache.writebacks::total 231848 # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1793 # number of ReadExReq MSHR hits
@@ -2016,6 +2017,7 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks
system.cpu1.l2cache.writebacks::total 26072 # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 73 # number of ReadExReq MSHR hits
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index f7f13cbec..56d82517d 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -142,7 +144,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -220,7 +221,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -333,7 +333,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -368,6 +367,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -430,7 +430,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -465,6 +464,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -697,6 +697,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
+thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@@ -1084,8 +1085,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
+thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@@ -1131,6 +1133,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index c304518f2..76353e776 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -146,7 +148,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -224,7 +225,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -526,7 +526,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -563,7 +562,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -598,6 +596,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -766,6 +765,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
+thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@@ -1153,8 +1153,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
+thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@@ -1200,6 +1201,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@@ -1423,6 +1434,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
index 6291714a8..e0323518d 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
@@ -38,3 +38,11 @@ warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
index 87f5d9e1f..fd51e6096 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -142,7 +144,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -220,7 +221,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -518,7 +518,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -555,7 +554,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -590,6 +588,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -822,6 +821,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
+thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@@ -1209,8 +1209,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
+thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@@ -1256,6 +1257,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@@ -1479,6 +1490,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
index d2f2052ec..3d09242ab 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
@@ -75,7 +75,3 @@ warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 7b732e972..66e9b1e33 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -34,6 +34,8 @@ num_work_ids=16
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -144,7 +146,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -196,7 +197,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -233,7 +233,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -301,7 +300,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -338,7 +336,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -373,6 +370,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -855,7 +853,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -890,6 +887,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index ce3929150..47c10392c 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -34,6 +34,8 @@ num_work_ids=16
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -140,7 +142,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -192,7 +193,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -229,7 +229,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -297,7 +296,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -334,7 +332,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -369,6 +366,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -851,7 +849,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@@ -886,6 +883,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index edd8d3427..f63f35994 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -24,6 +24,8 @@ readfile=/z/atgutier/gem5/gem5-commit/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -209,6 +211,7 @@ clk_domain=drivesys.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -953,6 +956,8 @@ readfile=/z/atgutier/gem5/gem5-commit/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -1138,6 +1143,7 @@ clk_domain=testsys.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
index a97df4eeb..b45f7c576 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -120,11 +122,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 60fdb36fc..d32749ad1 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -13,30 +13,30 @@ sim_insts 6413 # Nu
sim_ops 6413 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 23296 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
-system.physmem.bytes_read::total 34112 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 34048 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 619096973 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 287437880 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 906534853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 619096973 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 619096973 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 619096973 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 287437880 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 906534853 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 533 # Number of read requests accepted
+system.physmem.num_reads::total 532 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 619619139 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 288472822 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 908091961 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 619619139 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 619619139 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 619619139 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 288472822 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 908091961 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 532 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::6 1 # Pe
system.physmem.perBankRdBursts::7 5 # Per bank write bursts
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdBursts::9 1 # Per bank write bursts
-system.physmem.perBankRdBursts::10 22 # Per bank write bursts
+system.physmem.perBankRdBursts::10 21 # Per bank write bursts
system.physmem.perBankRdBursts::11 29 # Per bank write bursts
system.physmem.perBankRdBursts::12 19 # Per bank write bursts
system.physmem.perBankRdBursts::13 127 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 37524500 # Total gap between requests
+system.physmem.totGap 37389500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 533 # Read request sizes (log2)
+system.physmem.readPktSize::6 532 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 444 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -186,42 +186,42 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 388.626506 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 254.752349 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 332.370925 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19 22.89% 44.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 11 13.25% 57.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 11 13.25% 71.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2 2.41% 73.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 5 6.02% 79.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2 2.41% 81.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 7 8.43% 90.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8 9.64% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation
-system.physmem.totQLat 3516000 # Total ticks spent queuing
-system.physmem.totMemAccLat 13509750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6596.62 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 387.902439 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 251.688412 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 333.441746 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 19 23.17% 23.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18 21.95% 45.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 11 13.41% 58.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 10 12.20% 70.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1 1.22% 71.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6 7.32% 79.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4 4.88% 84.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 5 6.10% 90.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8 9.76% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation
+system.physmem.totQLat 3129000 # Total ticks spent queuing
+system.physmem.totMemAccLat 13104000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5881.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25346.62 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 906.53 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24631.58 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 908.09 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 906.53 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 908.09 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 7.08 # Data bus utilization in percentage
-system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads
+system.physmem.busUtil 7.09 # Data bus utilization in percentage
+system.physmem.busUtilRead 7.09 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 438 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 70402.44 # Average gap between requests
-system.physmem.pageHitRate 82.18 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 70281.02 # Average gap between requests
+system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
@@ -231,55 +231,59 @@ system.physmem_0.actBackEnergy 21404070 # En
system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 105750 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 16000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 20470410 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 886500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 25449690 # Total energy per rank (pJ)
-system.physmem_1.averagePower 810.370642 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1337750 # Time in different power states
+system.physmem_1.actBackEnergy 20432790 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 920250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 25465305 # Total energy per rank (pJ)
+system.physmem_1.averagePower 810.835582 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 1481500 # Time in different power states
system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 29041000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 1942 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1197 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 362 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1557 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 406 # Number of BTB hits
+system.cpu.branchPred.lookups 2009 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1611 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 378 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 26.075787 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 225 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 23.463687 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 338 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 325 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1372 # DTB read hits
+system.cpu.dtb.read_hits 1378 # DTB read hits
system.cpu.dtb.read_misses 11 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1383 # DTB read accesses
-system.cpu.dtb.write_hits 884 # DTB write hits
+system.cpu.dtb.read_accesses 1389 # DTB read accesses
+system.cpu.dtb.write_hits 885 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 887 # DTB write accesses
-system.cpu.dtb.data_hits 2256 # DTB hits
+system.cpu.dtb.write_accesses 888 # DTB write accesses
+system.cpu.dtb.data_hits 2263 # DTB hits
system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2270 # DTB accesses
-system.cpu.itb.fetch_hits 2673 # ITB hits
+system.cpu.dtb.data_accesses 2277 # DTB accesses
+system.cpu.itb.fetch_hits 2687 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2690 # ITB accesses
+system.cpu.itb.fetch_accesses 2704 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -293,80 +297,115 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 75258 # number of cpu cycles simulated
+system.cpu.numCycles 74988 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6413 # Number of instructions committed
system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1090 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1148 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 11.735225 # CPI: cycles per instruction
-system.cpu.ipc 0.085214 # IPC: instructions per cycle
-system.cpu.tickCycles 12565 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 62693 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 11.693123 # CPI: cycles per instruction
+system.cpu.ipc 0.085520 # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
+system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction
+system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction
+system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction
+system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction
+system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::total 6413 # Class of committed instruction
+system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 104.289845 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1974 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.680473 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.715976 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 104.289845 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.025461 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.025461 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 104.135823 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.025424 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025424 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1974 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1974 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1974 # number of overall hits
-system.cpu.dcache.overall_hits::total 1974 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 1980 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1980 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1980 # number of overall hits
+system.cpu.dcache.overall_hits::total 1980 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -375,14 +414,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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@@ -391,82 +430,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169
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@@ -475,48 +514,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63950.413223 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63950.413223 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68932.291667 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68932.291667 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.001873 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.043274 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 533 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.001876 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.043315 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 533 99.81% 99.81% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 532 99.81% 99.81% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 460 # Transaction distribution
+system.membus.trans_dist::ReadResp 459 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 460 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 533 # Request fanout histogram
+system.membus.snoop_fanout::samples 532 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 533 # Request fanout histogram
-system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 532 # Request fanout histogram
+system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2833750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2826750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 78826b5e1..a3681b4ff 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index dbdf20650..c617feb20 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21972500 # Number of ticks simulated
-final_tick 21972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 22019000 # Number of ticks simulated
+final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 66596 # Simulator instruction rate (inst/s)
host_op_rate 66584 # Simulator op (including micro ops) rate (op/s)
@@ -13,37 +13,37 @@ sim_insts 6385 # Nu
sim_ops 6385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 31040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 902946865 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 503902606 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1406849471 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 902946865 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 902946865 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 902946865 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 503902606 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1406849471 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 483 # Number of read requests accepted
+system.physmem.num_reads::total 485 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 906853172 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 502838458 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1409691630 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 906853172 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 906853172 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 906853172 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 502838458 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1409691630 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 485 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 483 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30912 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30912 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 68 # Per bank write bursts
+system.physmem.perBankRdBursts::0 69 # Per bank write bursts
system.physmem.perBankRdBursts::1 32 # Per bank write bursts
-system.physmem.perBankRdBursts::2 32 # Per bank write bursts
+system.physmem.perBankRdBursts::2 33 # Per bank write bursts
system.physmem.perBankRdBursts::3 47 # Per bank write bursts
system.physmem.perBankRdBursts::4 42 # Per bank write bursts
system.physmem.perBankRdBursts::5 20 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 21835000 # Total gap between requests
+system.physmem.totGap 21881000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 483 # Read request sizes (log2)
+system.physmem.readPktSize::6 485 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -187,98 +187,102 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 352 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 228.419611 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.406987 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 353.684211 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 230.878571 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 321.867393 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 20 26.32% 50.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9 11.84% 61.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 11 14.47% 76.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4 5.26% 81.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1 1.32% 82.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 3.95% 86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 10 13.16% 61.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 10 13.16% 75.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5 6.58% 81.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 2.63% 84.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation
-system.physmem.totQLat 3936250 # Total ticks spent queuing
-system.physmem.totMemAccLat 12992500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2415000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8149.59 # Average queueing delay per DRAM burst
+system.physmem.totQLat 4444750 # Total ticks spent queuing
+system.physmem.totMemAccLat 13538500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9164.43 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26899.59 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1406.85 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27914.43 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1409.69 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1406.85 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1409.69 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.99 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.99 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.01 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 392 # Number of row buffer hits during reads
+system.physmem.readRowHits 394 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45207.04 # Average gap between requests
-system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 45115.46 # Average gap between requests
+system.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1638000 # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 13783005 # Total energy per rank (pJ)
-system.physmem_0.averagePower 870.551397 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 281750 # Time in different power states
+system.physmem_0.totalEnergy 13798605 # Total energy per rank (pJ)
+system.physmem_0.averagePower 871.536712 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 297750 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10134315 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 609750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 13503900 # Total energy per rank (pJ)
-system.physmem_1.averagePower 852.922785 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 945500 # Time in different power states
+system.physmem_1.actBackEnergy 10085580 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 657000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 13486815 # Total energy per rank (pJ)
+system.physmem_1.averagePower 851.440341 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 1024500 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14380750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2618 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1561 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 431 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2031 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 757 # Number of BTB hits
+system.cpu.branchPred.lookups 2849 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2197 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 713 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 37.272280 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 391 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 32.453345 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 25 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 436 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 2066 # DTB read hits
-system.cpu.dtb.read_misses 43 # DTB read misses
+system.cpu.dtb.read_hits 2261 # DTB read hits
+system.cpu.dtb.read_misses 48 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2109 # DTB read accesses
-system.cpu.dtb.write_hits 1060 # DTB write hits
+system.cpu.dtb.read_accesses 2309 # DTB read accesses
+system.cpu.dtb.write_hits 1039 # DTB write hits
system.cpu.dtb.write_misses 28 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1088 # DTB write accesses
-system.cpu.dtb.data_hits 3126 # DTB hits
-system.cpu.dtb.data_misses 71 # DTB misses
+system.cpu.dtb.write_accesses 1067 # DTB write accesses
+system.cpu.dtb.data_hits 3300 # DTB hits
+system.cpu.dtb.data_misses 76 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3197 # DTB accesses
-system.cpu.itb.fetch_hits 2136 # ITB hits
-system.cpu.itb.fetch_misses 29 # ITB misses
+system.cpu.dtb.data_accesses 3376 # DTB accesses
+system.cpu.itb.fetch_hits 2293 # ITB hits
+system.cpu.itb.fetch_misses 27 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2165 # ITB accesses
+system.cpu.itb.fetch_accesses 2320 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -292,235 +296,235 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 43946 # number of cpu cycles simulated
+system.cpu.numCycles 44039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8425 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 15219 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2618 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1148 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 944 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 705 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2136 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14373 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.058860 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.441925 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 8533 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 16533 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2849 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 5068 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 654 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2293 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14799 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.117170 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.500450 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11578 80.55% 80.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 318 2.21% 82.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 240 1.67% 84.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 228 1.59% 86.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 264 1.84% 87.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 210 1.46% 89.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 253 1.76% 91.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 143 0.99% 92.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1139 7.92% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11815 79.84% 79.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 299 2.02% 81.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 232 1.57% 83.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 256 1.73% 85.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 292 1.97% 87.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 232 1.57% 88.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 283 1.91% 90.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 144 0.97% 91.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1246 8.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14373 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.059573 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.346311 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8351 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 3116 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2327 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 180 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 399 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 208 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13836 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 399 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8502 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1476 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 647 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2338 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1011 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 13352 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full
+system.cpu.fetch.rateDist::total 14799 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.064693 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.375417 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8370 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 3320 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 14994 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8529 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1727 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 614 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2478 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1003 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 14444 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 10012 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 16699 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 16690 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 10925 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 17884 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5435 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 599 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2560 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 12265 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10237 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5909 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3249 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14373 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.712238 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.437631 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 6348 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2839 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 13053 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6694 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3672 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 14799 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.728157 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.465404 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10470 72.84% 72.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1281 8.91% 81.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 885 6.16% 87.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 672 4.68% 92.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 490 3.41% 96.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 330 2.30% 98.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 178 1.24% 99.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10757 72.69% 72.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1297 8.76% 81.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 917 6.20% 87.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 680 4.59% 92.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 523 3.53% 95.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 348 2.35% 98.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 194 1.31% 99.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14373 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14799 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 20 14.93% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 73 54.48% 69.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 41 30.60% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 19 13.77% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 82 59.42% 73.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 37 26.81% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 6864 67.05% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2247 21.95% 89.05% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1121 10.95% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7177 66.60% 66.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.63% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.65% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2482 23.03% 89.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1112 10.32% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10237 # Type of FU issued
-system.cpu.iq.rate 0.232945 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 134 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013090 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 34976 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 18212 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9377 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 10776 # Type of FU issued
+system.cpu.iq.rate 0.244692 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 138 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012806 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 36485 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 19785 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9739 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10358 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10901 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1375 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 419 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1654 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 428 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 399 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1377 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 12377 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2560 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 21 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 9833 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2109 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1371 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 296 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 13164 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 289 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 10291 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 82 # number of nop insts executed
-system.cpu.iew.exec_refs 3199 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1559 # Number of branches executed
-system.cpu.iew.exec_stores 1090 # Number of stores executed
-system.cpu.iew.exec_rate 0.223752 # Inst execution rate
-system.cpu.iew.wb_sent 9541 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9387 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5006 # num instructions producing a value
-system.cpu.iew.wb_consumers 6861 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.213603 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.729631 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 5982 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 84 # number of nop insts executed
+system.cpu.iew.exec_refs 3386 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1641 # Number of branches executed
+system.cpu.iew.exec_stores 1077 # Number of stores executed
+system.cpu.iew.exec_rate 0.233679 # Inst execution rate
+system.cpu.iew.wb_sent 9945 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9749 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5139 # num instructions producing a value
+system.cpu.iew.wb_consumers 7002 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.221372 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.733933 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 6711 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 358 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13303 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.481245 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.398957 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13565 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.471950 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.389989 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10861 81.64% 81.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1165 8.76% 90.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 487 3.66% 94.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 203 1.53% 95.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 129 0.97% 96.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 82 0.62% 97.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 98 0.74% 97.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 84 0.63% 98.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 194 1.46% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11138 82.11% 82.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1158 8.54% 90.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 134 0.99% 96.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 84 0.62% 97.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13303 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13565 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6402 # Number of instructions committed
system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -566,102 +570,102 @@ system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
-system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 25142 # The number of ROB reads
-system.cpu.rob.rob_writes 25845 # The number of ROB writes
-system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29573 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 26135 # The number of ROB reads
+system.cpu.rob.rob_writes 27477 # The number of ROB writes
+system.cpu.timesIdled 253 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 29240 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6385 # Number of Instructions Simulated
system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 6.882694 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.882694 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.145292 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.145292 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12434 # number of integer regfile reads
-system.cpu.int_regfile_writes 7099 # number of integer regfile writes
+system.cpu.cpi 6.897259 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.897259 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.144985 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.144985 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12924 # number of integer regfile reads
+system.cpu.int_regfile_writes 7434 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 109.593222 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2292 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.248555 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.901734 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 109.593222 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.026756 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.026756 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 109.409218 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.026711 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.026711 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5805 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5805 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1786 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1786 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2292 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2292 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2292 # number of overall hits
-system.cpu.dcache.overall_hits::total 2292 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits
+system.cpu.dcache.overall_hits::total 2405 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses
-system.cpu.dcache.overall_misses::total 524 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 12170500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 12170500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35821975 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35821975 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35821975 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35821975 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1951 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses
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@@ -670,138 +674,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173
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-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65385.483871 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65385.483871 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72212.871287 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72212.871287 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65385.483871 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70127.167630 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67083.850932 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65385.483871 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70127.167630 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67083.850932 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67562.500000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67562.500000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66883.012821 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66883.012821 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72237.623762 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72237.623762 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 412 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 484 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.002066 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.045455 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 483 99.79% 99.79% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 484 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 411 # Transaction distribution
+system.membus.trans_dist::ReadResp 413 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 411 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 966 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 966 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 483 # Request fanout histogram
+system.membus.snoop_fanout::samples 485 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 483 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 483 # Request fanout histogram
-system.membus.reqLayer0.occupancy 588000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 485 # Request fanout histogram
+system.membus.reqLayer0.occupancy 590500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2567750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2579250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 1e89f2405..5f2701c66 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
index c48b9e2ab..b9631a6d8 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
index 22fffb44f..ccfdd3697 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 72c6ff442..7127384c1 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
index 22fffb44f..ccfdd3697 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index f83b6e49b..072c6d45b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
index 22fffb44f..ccfdd3697 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 7e20448ad..2fd013908 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
index 22fffb44f..ccfdd3697 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index b3071363a..2d08f440e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
index 22fffb44f..ccfdd3697 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 11ab1d0ac..68b35910c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index 8e21534df..654daf7a1 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -120,11 +122,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -135,7 +144,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -560,7 +568,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -611,7 +618,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -646,6 +652,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -711,6 +718,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index eadf1b794..8e060c84e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 20075000 # Number of ticks simulated
-final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 20320000 # Number of ticks simulated
+final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 31344 # Simulator instruction rate (inst/s)
host_op_rate 31334 # Simulator op (including micro ops) rate (op/s)
@@ -13,30 +13,30 @@ sim_insts 2585 # Nu
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 14272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
-system.physmem.bytes_read::total 19712 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 14272 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 19840 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 710933998 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 270983811 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 981917808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 710933998 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 710933998 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 710933998 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 270983811 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 981917808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 308 # Number of read requests accepted
+system.physmem.num_reads::total 310 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 708661417 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 267716535 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 976377953 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 708661417 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 708661417 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 708661417 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 267716535 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 976377953 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 310 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 19712 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 19840 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 19712 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 19840 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@@ -52,7 +52,7 @@ system.physmem.perBankRdBursts::7 47 # Pe
system.physmem.perBankRdBursts::8 68 # Per bank write bursts
system.physmem.perBankRdBursts::9 2 # Per bank write bursts
system.physmem.perBankRdBursts::10 15 # Per bank write bursts
-system.physmem.perBankRdBursts::11 14 # Per bank write bursts
+system.physmem.perBankRdBursts::11 16 # Per bank write bursts
system.physmem.perBankRdBursts::12 18 # Per bank write bursts
system.physmem.perBankRdBursts::13 52 # Per bank write bursts
system.physmem.perBankRdBursts::14 15 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 19987000 # Total gap between requests
+system.physmem.totGap 20232000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 308 # Read request sizes (log2)
+system.physmem.readPktSize::6 310 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -187,41 +187,41 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 430.829268 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 282.802413 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 330.088769 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 282.076610 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 329.225077 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 6 14.63% 68.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 4 9.76% 78.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3 7.32% 78.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation
-system.physmem.totQLat 1568250 # Total ticks spent queuing
-system.physmem.totMemAccLat 7343250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5091.72 # Average queueing delay per DRAM burst
+system.physmem.totQLat 1648500 # Total ticks spent queuing
+system.physmem.totMemAccLat 7461000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5317.74 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23841.72 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 981.92 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24067.74 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 976.38 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 981.92 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 976.38 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 7.67 # Data bus utilization in percentage
-system.physmem.busUtilRead 7.67 # Data bus utilization in percentage for reads
+system.physmem.busUtil 7.63 # Data bus utilization in percentage
+system.physmem.busUtilRead 7.63 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 258 # Number of row buffer hits during reads
+system.physmem.readRowHits 259 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.55 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 64892.86 # Average gap between requests
-system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 65264.52 # Average gap between requests
+system.physmem.pageHitRate 83.55 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ)
@@ -231,55 +231,59 @@ system.physmem_0.actBackEnergy 10605420 # En
system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ)
system.physmem_0.averagePower 803.889152 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 534250 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 681250 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy 1193400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10488285 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 13297980 # Total energy per rank (pJ)
-system.physmem_1.averagePower 839.916627 # Core power per rank (mW)
+system.physmem_1.totalEnergy 13290180 # Total energy per rank (pJ)
+system.physmem_1.averagePower 839.423970 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 787 # Number of BP lookups
-system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 164 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 560 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 60 # Number of BTB hits
+system.cpu.branchPred.lookups 794 # Number of BP lookups
+system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 54 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 10.714286 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 9.608541 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 144 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 83 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 0 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 83 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 32 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 506 # DTB read hits
-system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.read_hits 510 # DTB read hits
+system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 513 # DTB read accesses
+system.cpu.dtb.read_accesses 518 # DTB read accesses
system.cpu.dtb.write_hits 307 # DTB write hits
system.cpu.dtb.write_misses 6 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 313 # DTB write accesses
-system.cpu.dtb.data_hits 813 # DTB hits
-system.cpu.dtb.data_misses 13 # DTB misses
+system.cpu.dtb.data_hits 817 # DTB hits
+system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 826 # DTB accesses
-system.cpu.itb.fetch_hits 965 # ITB hits
+system.cpu.dtb.data_accesses 831 # DTB accesses
+system.cpu.itb.fetch_hits 975 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 978 # ITB accesses
+system.cpu.itb.fetch_accesses 988 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -293,40 +297,75 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 40150 # number of cpu cycles simulated
+system.cpu.numCycles 40640 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2585 # Number of instructions committed
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 581 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 603 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 15.531915 # CPI: cycles per instruction
-system.cpu.ipc 0.064384 # IPC: instructions per cycle
-system.cpu.tickCycles 5369 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 34781 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 15.721470 # CPI: cycles per instruction
+system.cpu.ipc 0.063607 # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction
+system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction
+system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction
+system.cpu.op_class_0::IntDiv 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::FloatMult 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdMult 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdShift 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 72.26% # Class of committed instruction
+system.cpu.op_class_0::MemRead 419 16.21% 88.47% # Class of committed instruction
+system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::total 2585 # Class of committed instruction
+system.cpu.tickCycles 5416 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 35224 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 48.313800 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 689 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 48.513757 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 693 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 8.105882 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 8.152941 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 48.313800 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.011795 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.011795 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 48.513757 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.011844 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.011844 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1671 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1671 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 438 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 438 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 1679 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1679 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 442 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 442 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 689 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 689 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 689 # number of overall hits
-system.cpu.dcache.overall_hits::total 689 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 693 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 693 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 693 # number of overall hits
+system.cpu.dcache.overall_hits::total 693 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
@@ -335,38 +374,38 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n
system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses
system.cpu.dcache.overall_misses::total 104 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4723000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4723500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3258500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7981500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 499 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 499 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 7982000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7982000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7982000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7982000 # number of overall miss cycles
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -391,82 +430,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
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@@ -475,84 +514,84 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
@@ -567,16 +606,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -587,28 +626,28 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
@@ -623,74 +662,74 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution
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system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
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system.membus.trans_dist::ReadExResp 27 # Transaction distribution
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 308 # Request fanout histogram
-system.membus.reqLayer0.occupancy 359500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 310 # Request fanout histogram
+system.membus.reqLayer0.occupancy 363500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1638750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 8.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1649000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 8.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 7d0044f86..4281491aa 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -160,7 +169,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -509,7 +517,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -560,7 +567,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -595,6 +601,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -660,6 +667,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index c35fecd4e..619c657d2 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 12363500 # Number of ticks simulated
-final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 12409500 # Number of ticks simulated
+final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 12168 # Simulator instruction rate (inst/s)
host_op_rate 12166 # Simulator op (including micro ops) rate (op/s)
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu
system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 968010677 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 440004853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1408015530 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 968010677 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 968010677 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 968010677 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 440004853 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1408015530 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 964422418 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 438373827 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1402796245 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 964422418 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 964422418 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 964422418 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 438373827 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1402796245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 272 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 12267000 # Total gap between requests
+system.physmem.totGap 12313000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 152 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 81 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -200,27 +200,27 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By
system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation
-system.physmem.totQLat 1685750 # Total ticks spent queuing
-system.physmem.totMemAccLat 6785750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1652750 # Total ticks spent queuing
+system.physmem.totMemAccLat 6752750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6197.61 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6076.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24947.61 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1408.02 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24826.29 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1402.80 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1408.02 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1402.80 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.00 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.00 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.96 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 226 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45099.26 # Average gap between requests
+system.physmem.avgGap 45268.38 # Average gap between requests
system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ)
@@ -250,36 +250,40 @@ system.physmem_1.memoryStateTime::REF 260000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 890 # Number of BP lookups
-system.cpu.branchPred.condPredicted 443 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 195 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 616 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 164 # Number of BTB hits
+system.cpu.branchPred.lookups 1003 # Number of BP lookups
+system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 688 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 176 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 26.623377 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 186 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 25.581395 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 101 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 3 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 98 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 719 # DTB read hits
-system.cpu.dtb.read_misses 10 # DTB read misses
+system.cpu.dtb.read_hits 712 # DTB read hits
+system.cpu.dtb.read_misses 13 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 729 # DTB read accesses
-system.cpu.dtb.write_hits 347 # DTB write hits
-system.cpu.dtb.write_misses 16 # DTB write misses
+system.cpu.dtb.read_accesses 725 # DTB read accesses
+system.cpu.dtb.write_hits 349 # DTB write hits
+system.cpu.dtb.write_misses 17 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 363 # DTB write accesses
-system.cpu.dtb.data_hits 1066 # DTB hits
-system.cpu.dtb.data_misses 26 # DTB misses
+system.cpu.dtb.write_accesses 366 # DTB write accesses
+system.cpu.dtb.data_hits 1061 # DTB hits
+system.cpu.dtb.data_misses 30 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 1092 # DTB accesses
-system.cpu.itb.fetch_hits 802 # ITB hits
-system.cpu.itb.fetch_misses 35 # ITB misses
+system.cpu.dtb.data_accesses 1091 # DTB accesses
+system.cpu.itb.fetch_hits 878 # ITB hits
+system.cpu.itb.fetch_misses 32 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 837 # ITB accesses
+system.cpu.itb.fetch_accesses 910 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -293,233 +297,234 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 24728 # number of cpu cycles simulated
+system.cpu.numCycles 24820 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 4265 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 5512 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 890 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 350 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1015 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 436 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 4371 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 6065 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 1003 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 400 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1173 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1206 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles 1146 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 802 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 146 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 6733 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.818654 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.224131 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 878 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 6955 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.872035 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.274710 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 5799 86.13% 86.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 30 0.45% 86.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 91 1.35% 87.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 76 1.13% 89.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 118 1.75% 90.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 72 1.07% 91.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 40 0.59% 92.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 56 0.83% 93.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 451 6.70% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 5922 85.15% 85.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 27 0.39% 85.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 100 1.44% 86.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 87 1.25% 88.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 141 2.03% 90.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 81 1.16% 91.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 46 0.66% 92.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 76 1.09% 93.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 475 6.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 6733 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.035992 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.222905 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5190 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 505 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 865 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 28 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 145 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 132 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 6955 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.040411 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.244359 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5210 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 623 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 919 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 4839 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 145 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 5257 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 5285 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 327 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 824 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 7 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 4680 # Number of instructions processed by rename
+system.cpu.rename.RunCycles 881 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenamedOperands 3347 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5277 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5270 # Number of integer rename lookups
+system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RenamedOperands 3638 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5669 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5662 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 1579 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 1870 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 52 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 418 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
+system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 846 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 4078 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 4387 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 3608 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 32 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 1696 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 859 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 3758 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 28 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 6733 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.535868 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.279819 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 6955 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.540331 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.279888 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 5352 79.49% 79.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 449 6.67% 86.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 318 4.72% 90.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 240 3.56% 94.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 185 2.75% 97.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 110 1.63% 98.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 49 0.73% 99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 21 0.31% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 5508 79.19% 79.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 469 6.74% 85.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 342 4.92% 90.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 254 3.65% 94.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 193 2.77% 97.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 103 1.48% 98.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 56 0.81% 99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 6733 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 6955 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6 8.70% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 39 56.52% 65.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 24 34.78% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 31 50.82% 60.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 24 39.34% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 2482 68.79% 68.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.03% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 757 20.98% 89.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 368 10.20% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 2627 69.90% 69.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.03% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 757 20.14% 90.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 3608 # Type of FU issued
-system.cpu.iq.rate 0.145907 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 69 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019124 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 14037 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 5777 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 3273 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 3758 # Type of FU issued
+system.cpu.iq.rate 0.151410 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 61 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 14547 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 3670 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 3812 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 380 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 431 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 124 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 145 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 4365 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 29 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 418 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 297 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 846 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 20 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 120 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 140 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 3509 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 730 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 99 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 3634 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 727 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 281 # number of nop insts executed
+system.cpu.iew.exec_nop 307 # number of nop insts executed
system.cpu.iew.exec_refs 1093 # number of memory reference insts executed
-system.cpu.iew.exec_branches 570 # Number of branches executed
-system.cpu.iew.exec_stores 363 # Number of stores executed
-system.cpu.iew.exec_rate 0.141904 # Inst execution rate
-system.cpu.iew.wb_sent 3329 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 3279 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1560 # num instructions producing a value
-system.cpu.iew.wb_consumers 1998 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.132603 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.780781 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 1787 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_branches 599 # Number of branches executed
+system.cpu.iew.exec_stores 366 # Number of stores executed
+system.cpu.iew.exec_rate 0.146414 # Inst execution rate
+system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 3425 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1633 # num instructions producing a value
+system.cpu.iew.wb_consumers 2097 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.137994 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 122 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 6402 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.402374 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.273029 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 6540 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.393884 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.249766 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 5545 86.61% 86.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 194 3.03% 89.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 304 4.75% 94.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 116 1.81% 96.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 62 0.97% 97.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 60 0.94% 98.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 35 0.55% 98.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 20 0.31% 98.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 66 1.03% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 5669 86.68% 86.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 198 3.03% 89.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 318 4.86% 94.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 63 0.96% 97.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 37 0.57% 98.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 6402 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 6540 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -565,101 +570,101 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
-system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached
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-system.cpu.rob.rob_writes 9060 # The number of ROB writes
-system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 17995 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 10930 # The number of ROB reads
+system.cpu.rob.rob_writes 9815 # The number of ROB writes
+system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 17865 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 10.359447 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 10.359447 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.096530 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.096530 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 4249 # number of integer regfile reads
-system.cpu.int_regfile_writes 2511 # number of integer regfile writes
+system.cpu.cpi 10.397989 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 10.397989 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.096172 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.096172 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 4383 # number of integer regfile reads
+system.cpu.int_regfile_writes 2640 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
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system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
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+system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
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-system.cpu.dcache.ReadReq_hits::total 503 # number of ReadReq hits
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 5672000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5672000 # number of WriteReq miss cycles
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-system.cpu.dcache.overall_miss_latency::total 12255000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 68848.314607 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 68848.314607 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 68848.314607 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.444444 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits
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+system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
@@ -668,82 +673,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4810000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 6661000 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 90.143737 # Cycle average of tags in use
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system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id
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-system.cpu.icache.overall_avg_miss_latency::total 74957.996000 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
@@ -752,48 +757,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 118.927175 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.302552 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 28.624623 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002756 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
@@ -814,16 +819,16 @@ system.cpu.l2cache.overall_misses::cpu.data 85 #
system.cpu.l2cache.overall_misses::total 272 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses)
@@ -850,16 +855,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -882,16 +887,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 85
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
@@ -906,16 +911,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -971,9 +976,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 272 # Request fanout histogram
-system.membus.reqLayer0.occupancy 335500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1441000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 11.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 2db41bef8..164e856da 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -151,6 +153,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index 8e85722f1..214f11946 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
index f6a02f021..1c18978fa 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 95074a37b..2ad2eb8ea 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index f6a02f021..1c18978fa 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 7ee7deae6..c78531ccf 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index f6a02f021..1c18978fa 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 8190e6bb4..18d7c2ab4 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
index f6a02f021..1c18978fa 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 4edb3028e..538bb6cd3 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index f6a02f021..1c18978fa 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 16a0ec4c3..ea2d2a5a5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -181,7 +181,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -216,6 +215,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -281,6 +281,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
index 98b98ce6b..0858c144d 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -122,11 +124,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -137,7 +146,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -598,7 +606,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -711,7 +718,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -746,6 +752,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -811,6 +818,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index 586c80689..02dbcdc04 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 29949500 # Number of ticks simulated
-final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 29977500 # Number of ticks simulated
+final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 167534 # Simulator instruction rate (inst/s)
host_op_rate 196036 # Simulator op (including micro ops) rate (op/s)
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 651155033 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 247652406 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 898807439 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 651155033 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 651155033 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 651155033 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 247652406 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 898807439 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 421 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 29858000 # Total gap between requests
+system.physmem.totGap 29886000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -188,31 +188,31 @@ system.physmem.wrQLenPdf::62 0 # Wh
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 287.393665 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 328.869570 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 6.45% 74.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
-system.physmem.totQLat 2201000 # Total ticks spent queuing
-system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2113500 # Total ticks spent queuing
+system.physmem.totMemAccLat 10007250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5020.19 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 23770.19 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 898.81 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 898.81 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 7.03 # Data bus utilization in percentage
-system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
+system.physmem.busUtil 7.02 # Data bus utilization in percentage
+system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
@@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 70921.62 # Average gap between requests
+system.physmem.avgGap 70988.12 # Average gap between requests
system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
@@ -241,24 +241,28 @@ system.physmem_1.preEnergy 70125 # En
system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ)
-system.physmem_1.averagePower 784.282403 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states
+system.physmem_1.actBackEnergy 15745680 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ)
+system.physmem_1.averagePower 784.269066 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 1912 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 347 # Number of BTB hits
+system.cpu.branchPred.lookups 1949 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 316 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 8 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 125 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -377,44 +381,79 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 59899 # number of cpu cycles simulated
+system.cpu.numCycles 59955 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4605 # Number of instructions committed
system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 13.007383 # CPI: cycles per instruction
-system.cpu.ipc 0.076879 # IPC: instructions per cycle
-system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 13.019544 # CPI: cycles per instruction
+system.cpu.ipc 0.076808 # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction
+system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction
+system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction
+system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction
+system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::total 5391 # Class of committed instruction
+system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits
-system.cpu.dcache.overall_hits::total 1893 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1894 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1894 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1894 # number of overall hits
+system.cpu.dcache.overall_hits::total 1894 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
@@ -423,42 +462,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
system.cpu.dcache.overall_misses::total 182 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 6977500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 6977500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5011500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5011500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 11989000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 11989000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 11989000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 11989000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2076 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2076 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2076 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2076 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098882 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.098882 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.087669 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.087669 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.087669 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.087669 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65873.626374 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -483,82 +522,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6370500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6370500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3194000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3194000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9564500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9564500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9564500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9564500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088564 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088564 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.070328 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.070328 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 3 # number of replacements
-system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 4 # number of replacements
+system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
-system.cpu.icache.overall_hits::total 1920 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
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@@ -567,62 +606,62 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
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+system.cpu.l2cache.overall_miss_rate::total 0.914712 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -711,76 +750,76 @@ system.cpu.l2cache.demand_mshr_misses::total 421
system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19465500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19465500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4696000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4696000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19465500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 26861000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19465500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 26861000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.944272 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.897655 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.897655 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 942 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 30272 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 469 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.102345 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.303426 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 421 89.77% 89.77% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 48 10.23% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
@@ -803,9 +842,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 421 # Request fanout histogram
-system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2236750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 0ad30e5d6..db680b227 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -147,11 +149,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.checker]
type=O3Checker
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 8c3704b45..b78b358b1 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 17170000 # Number of ticks simulated
-final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 17232500 # Number of ticks simulated
+final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 9367 # Simulator instruction rate (inst/s)
host_op_rate 10970 # Simulator op (including micro ops) rate (op/s)
@@ -13,35 +13,35 @@ sim_insts 4592 # Nu
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25344 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 25408 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 396 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1025043681 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 451019220 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1476062900 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1025043681 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1025043681 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1025043681 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 451019220 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1476062900 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 396 # Number of read requests accepted
+system.physmem.num_reads::total 397 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 397 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 90 # Per bank write bursts
+system.physmem.perBankRdBursts::0 89 # Per bank write bursts
system.physmem.perBankRdBursts::1 45 # Per bank write bursts
system.physmem.perBankRdBursts::2 20 # Per bank write bursts
system.physmem.perBankRdBursts::3 43 # Per bank write bursts
@@ -50,10 +50,10 @@ system.physmem.perBankRdBursts::5 32 # Pe
system.physmem.perBankRdBursts::6 35 # Per bank write bursts
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
-system.physmem.perBankRdBursts::9 8 # Per bank write bursts
+system.physmem.perBankRdBursts::9 9 # Per bank write bursts
system.physmem.perBankRdBursts::10 28 # Per bank write bursts
system.physmem.perBankRdBursts::11 42 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10 # Per bank write bursts
system.physmem.perBankRdBursts::13 6 # Per bank write bursts
system.physmem.perBankRdBursts::14 0 # Per bank write bursts
system.physmem.perBankRdBursts::15 6 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 17097000 # Total gap between requests
+system.physmem.totGap 17147000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 396 # Read request sizes (log2)
+system.physmem.readPktSize::6 397 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -187,78 +187,82 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 389.079365 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 252.523009 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 343.171701 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6 9.52% 58.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 8 12.70% 71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
-system.physmem.totQLat 3045250 # Total ticks spent queuing
-system.physmem.totMemAccLat 10470250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7690.03 # Average queueing delay per DRAM burst
+system.physmem.totQLat 3287250 # Total ticks spent queuing
+system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26440.03 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1476.06 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1476.06 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.53 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.53 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.52 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 330 # Number of row buffer hits during reads
+system.physmem.readRowHits 331 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 43174.24 # Average gap between requests
-system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 43191.44 # Average gap between requests
+system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 10798650 # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 14433105 # Total energy per rank (pJ)
-system.physmem_0.averagePower 911.108972 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states
+system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ)
+system.physmem_0.averagePower 910.249171 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 16183750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ)
-system.physmem_1.averagePower 807.028896 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 672250 # Time in different power states
+system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ)
+system.physmem_1.averagePower 808.014211 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2537 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1577 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 453 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2106 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 814 # Number of BTB hits
+system.cpu.branchPred.lookups 2837 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 865 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 38.651472 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 14 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 251 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -496,235 +500,236 @@ system.cpu.itb.inst_accesses 0 # IT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 34341 # number of cpu cycles simulated
+system.cpu.numCycles 34466 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 11733 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2537 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1135 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4671 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 955 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 292 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13078 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.059336 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.422082 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10515 80.40% 80.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 260 1.99% 82.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 215 1.64% 84.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 219 1.67% 85.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 267 2.04% 87.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 312 2.39% 90.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 142 1.09% 91.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 157 1.20% 92.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 991 7.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13078 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.073877 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.341662 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6351 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4223 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2063 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 119 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 322 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11299 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 322 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6564 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 644 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2338 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1962 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 10655 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full
+system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2142 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2037 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 10847 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 48852 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 11762 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups
+system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 52722 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5353 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 42 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2118 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1531 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 40 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 9695 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 7975 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4363 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 10837 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13078 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.609803 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.341106 # Number of insts issued each cycle
+system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 12413 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9890 75.62% 75.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1180 9.02% 84.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 762 5.83% 90.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 451 3.45% 93.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 329 2.52% 96.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 278 2.13% 98.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 115 0.88% 99.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13078 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 67 44.08% 50.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4886 61.27% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1833 22.98% 84.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1246 15.62% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 7975 # Type of FU issued
-system.cpu.iq.rate 0.232230 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 152 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019060 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 29132 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 14007 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7313 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 8103 # Type of FU issued
+system.cpu.iq.rate 0.235101 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 145 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8084 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1091 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 593 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 322 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 611 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 9750 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2118 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1531 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 274 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9 # number of nop insts executed
-system.cpu.iew.exec_refs 2933 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1435 # Number of branches executed
-system.cpu.iew.exec_stores 1197 # Number of stores executed
-system.cpu.iew.exec_rate 0.224251 # Inst execution rate
-system.cpu.iew.wb_sent 7436 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7345 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3459 # num instructions producing a value
-system.cpu.iew.wb_consumers 6763 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.213884 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.511459 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 4371 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs 2923 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1492 # Number of branches executed
+system.cpu.iew.exec_stores 1151 # Number of stores executed
+system.cpu.iew.exec_rate 0.226716 # Inst execution rate
+system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7439 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3504 # num instructions producing a value
+system.cpu.iew.wb_consumers 6831 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 298 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12306 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.437023 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.282384 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10254 83.33% 83.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 882 7.17% 90.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 420 3.41% 93.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 223 1.81% 95.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 112 0.91% 96.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 213 1.73% 98.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 51 0.41% 98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 40 0.33% 99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12306 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4592 # Number of instructions committed
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -770,103 +775,103 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
-system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 21787 # The number of ROB reads
-system.cpu.rob.rob_writes 20281 # The number of ROB writes
-system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 21263 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 22311 # The number of ROB reads
+system.cpu.rob.rob_writes 21303 # The number of ROB writes
+system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4592 # Number of Instructions Simulated
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.478441 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.478441 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.133718 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.133718 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 7637 # number of integer regfile reads
-system.cpu.int_regfile_writes 4176 # number of integer regfile writes
+system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 7659 # number of integer regfile reads
+system.cpu.int_regfile_writes 4270 # number of integer regfile writes
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
@@ -875,16 +880,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
@@ -893,210 +898,214 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id
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+system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75458.181818 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75458.181818 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78327.380952 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78327.380952 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76467.581047 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76467.581047 # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1105,119 +1114,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18001000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18001000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5459000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5459000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18001000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8372000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 26373000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18001000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8372000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 26373000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65458.181818 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65458.181818 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69101.265823 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69101.265823 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 441 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 587 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 221500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 222995 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 354 # Transaction distribution
+system.membus.trans_dist::ReadResp 355 # Transaction distribution
system.membus.trans_dist::ReadExReq 42 # Transaction distribution
system.membus.trans_dist::ReadExResp 42 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 396 # Request fanout histogram
+system.membus.snoop_fanout::samples 397 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 396 # Request fanout histogram
-system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 397 # Request fanout histogram
+system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2097000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 12.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index a8b793687..4403ba687 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index fe4c1d834..a846c7a0c 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 18741000 # Number of ticks simulated
-final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 18821000 # Number of ticks simulated
+final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 9099 # Simulator instruction rate (inst/s)
host_op_rate 10656 # Simulator op (including micro ops) rate (op/s)
@@ -13,34 +13,34 @@ sim_insts 4592 # Nu
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 18432 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28224 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 18432 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 18432 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 288 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28352 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 441 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 983512086 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 430286538 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 92204258 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1506002881 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 983512086 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 983512086 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 983512086 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 430286538 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 92204258 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1506002881 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 442 # Number of read requests accepted
+system.physmem.num_reads::total 443 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 443 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 442 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 28288 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 28288 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@@ -48,7 +48,7 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu
system.physmem.perBankRdBursts::0 101 # Per bank write bursts
system.physmem.perBankRdBursts::1 48 # Per bank write bursts
system.physmem.perBankRdBursts::2 19 # Per bank write bursts
-system.physmem.perBankRdBursts::3 44 # Per bank write bursts
+system.physmem.perBankRdBursts::3 45 # Per bank write bursts
system.physmem.perBankRdBursts::4 19 # Per bank write bursts
system.physmem.perBankRdBursts::5 37 # Per bank write bursts
system.physmem.perBankRdBursts::6 46 # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 18727500 # Total gap between requests
+system.physmem.totGap 18779500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 442 # Read request sizes (log2)
+system.physmem.readPktSize::6 443 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -94,10 +94,10 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
@@ -191,77 +191,82 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 425.650794 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 288.378165 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 357.476918 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 21 33.33% 44.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 5 7.94% 76.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
-system.physmem.totQLat 3434000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11721500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2210000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7769.23 # Average queueing delay per DRAM burst
+system.physmem.totQLat 3401243 # Total ticks spent queuing
+system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26519.23 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1509.42 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1509.42 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.79 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.79 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.77 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 370 # Number of row buffer hits during reads
+system.physmem.readRowHits 371 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.71 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 42369.91 # Average gap between requests
-system.physmem.pageHitRate 83.71 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 42391.65 # Average gap between requests
+system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 10786680 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 37500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 14457615 # Total energy per rank (pJ)
-system.physmem_0.averagePower 913.160587 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states
+system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ)
+system.physmem_0.averagePower 912.921838 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 9859005 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 851250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 12737220 # Total energy per rank (pJ)
-system.physmem_1.averagePower 804.498342 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2184750 # Time in different power states
+system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ)
+system.physmem_1.averagePower 811.289436 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 13949750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2341 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1389 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 447 # Number of BTB hits
+system.cpu.branchPred.lookups 2438 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 449 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 53.341289 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 150 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -380,84 +385,84 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 37483 # number of cpu cycles simulated
+system.cpu.numCycles 37643 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 6059 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 11274 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2341 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 8204 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 363 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 3834 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 177 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 15601 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.845843 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.199579 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9385 60.16% 60.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2463 15.79% 75.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 526 3.37% 79.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3227 20.68% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 15601 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.062455 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.300776 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5749 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4322 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5029 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 9880 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 1586 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6811 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1118 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2339 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 4089 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 875 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 417 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full
+system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 5178 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 4187 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 772 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 9259 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 40331 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 9781 # Number of integer rename lookups
+system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 41158 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3765 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 1800 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1272 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 8358 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3018 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 7856 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 15601 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.458176 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.848338 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 11391 73.01% 73.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1965 12.60% 85.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1598 10.24% 95.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 601 3.85% 99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 46 0.29% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
@@ -465,147 +470,147 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 15601 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 413 28.70% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 475 33.01% 61.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 551 38.29% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4480 62.67% 62.67% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1582 22.13% 84.92% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1078 15.08% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 7148 # Type of FU issued
-system.cpu.iq.rate 0.190700 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1439 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.201315 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31476 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 11405 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 6562 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 7234 # Type of FU issued
+system.cpu.iq.rate 0.192174 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8559 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 773 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 334 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 385 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 8410 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 1800 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1272 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 6751 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1398 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 14 # number of nop insts executed
-system.cpu.iew.exec_refs 2419 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1275 # Number of branches executed
-system.cpu.iew.exec_stores 1021 # Number of stores executed
-system.cpu.iew.exec_rate 0.180108 # Inst execution rate
-system.cpu.iew.wb_sent 6621 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 6578 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2993 # num instructions producing a value
-system.cpu.iew.wb_consumers 5408 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.175493 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.553439 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 2586 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 13 # number of nop insts executed
+system.cpu.iew.exec_refs 2451 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1299 # Number of branches executed
+system.cpu.iew.exec_stores 1030 # Number of stores executed
+system.cpu.iew.exec_rate 0.181282 # Inst execution rate
+system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 6637 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2986 # num instructions producing a value
+system.cpu.iew.wb_consumers 5424 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 15057 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.357176 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.003286 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 12412 82.43% 82.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1386 9.21% 91.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 592 3.93% 95.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 296 1.97% 97.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 173 1.15% 98.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 78 0.52% 99.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 45 0.30% 99.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 32 0.21% 99.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 15057 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4592 # Number of instructions committed
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -652,122 +657,122 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 22821 # The number of ROB reads
-system.cpu.rob.rob_writes 16478 # The number of ROB writes
-system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 21882 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 23088 # The number of ROB reads
+system.cpu.rob.rob_writes 16743 # The number of ROB writes
+system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4592 # Number of Instructions Simulated
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.162674 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.162674 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.122509 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.122509 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 6723 # number of integer regfile reads
-system.cpu.int_regfile_writes 3755 # number of integer regfile writes
+system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads
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system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.cc_regfile_reads 23977 # number of cc regfile reads
-system.cpu.cc_regfile_writes 2903 # number of cc regfile writes
-system.cpu.misc_regfile_reads 2611 # number of misc regfile reads
+system.cpu.cc_regfile_reads 24229 # number of cc regfile reads
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system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.dcache.tags.replacements 1 # number of replacements
-system.cpu.dcache.tags.tagsinuse 84.551975 # Cycle average of tags in use
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system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.342657 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.tags.occ_percent::total 0.165141 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id
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-system.cpu.dcache.tags.data_accesses 4677 # Number of data accesses
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-system.cpu.dcache.ReadReq_hits::total 1166 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses
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system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
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-system.cpu.dcache.demand_hits::total 1888 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1888 # number of overall hits
-system.cpu.dcache.overall_hits::total 1888 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
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-system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 357 # number of overall misses
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-system.cpu.dcache.WriteReq_miss_latency::total 7727500 # number of WriteReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 18417000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 18417000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 18417000 # number of overall miss cycles
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-system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.overall_miss_latency::total 18287500 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124625 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.124625 # miss rate for ReadReq accesses
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+system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
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-system.cpu.dcache.demand_miss_rate::total 0.159020 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.159020 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.159020 # miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 64394.578313 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40458.115183 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 40458.115183 # average WriteReq miss latency
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 63949.101796 # average ReadReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 51588.235294 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 51588.235294 # average overall miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 51082.402235 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 846 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu.dcache.writebacks::total 1 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 213 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
@@ -776,122 +781,122 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144
system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6989000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2447000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9436000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9436000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9436000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9436000 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077327 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.064143 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.064143 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67854.368932 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67854.368932 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59682.926829 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59682.926829 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency
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+system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 43 # number of replacements
-system.cpu.icache.tags.tagsinuse 137.647063 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 3470 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 11.722973 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 44 # number of replacements
+system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 137.647063 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.268842 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.268842 # Average percentage of cache occupancy
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@@ -918,84 +923,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1018,123 +1023,123 @@ system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53
system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses
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system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
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system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter.
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system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
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+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 636 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 924 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 452 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.582857 # Request fanout histogram
+system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 454 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 897 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.549610 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.582523 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 443 49.61% 49.61% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 409 45.80% 95.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 41 4.59% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 445 49.61% 49.61% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 893 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 286500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 444499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 410 # Transaction distribution
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system.membus.trans_dist::ReadExReq 30 # Transaction distribution
system.membus.trans_dist::ReadExResp 30 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution
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-system.membus.pkt_count::total 882 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28160 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution
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+system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 442 # Request fanout histogram
+system.membus.snoop_fanout::samples 443 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 442 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 443 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 442 # Request fanout histogram
-system.membus.reqLayer0.occupancy 559944 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 443 # Request fanout histogram
+system.membus.reqLayer0.occupancy 561444 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2320000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2329257 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 12.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 49256c4fe..60fb7fd34 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -401,6 +403,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index 7af27520b..40d4f88c7 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -251,6 +253,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 21e554bfb..3fd071b25 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -90,7 +92,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -168,7 +169,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -281,7 +281,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -316,6 +315,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -381,6 +381,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 578d96f53..900efeb02 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 27cfa20b6..15e66dc76 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 22454000 # Number of ticks simulated
-final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000023 # Number of seconds simulated
+sim_ticks 22532000 # Number of ticks simulated
+final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 22135 # Simulator instruction rate (inst/s)
host_op_rate 22134 # Simulator op (including micro ops) rate (op/s)
@@ -13,30 +13,30 @@ sim_insts 4999 # Nu
sim_ops 4999 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 29952 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 934889107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 399038033 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1333927140 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 934889107 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 934889107 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 934889107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 399038033 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1333927140 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 468 # Number of read requests accepted
+system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 934493165 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 397656666 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1332149831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 934493165 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 934493165 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 934493165 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 397656666 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1332149831 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 469 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 468 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 29952 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 29952 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@@ -52,7 +52,7 @@ system.physmem.perBankRdBursts::7 53 # Pe
system.physmem.perBankRdBursts::8 59 # Per bank write bursts
system.physmem.perBankRdBursts::9 76 # Per bank write bursts
system.physmem.perBankRdBursts::10 43 # Per bank write bursts
-system.physmem.perBankRdBursts::11 20 # Per bank write bursts
+system.physmem.perBankRdBursts::11 21 # Per bank write bursts
system.physmem.perBankRdBursts::12 51 # Per bank write bursts
system.physmem.perBankRdBursts::13 29 # Per bank write bursts
system.physmem.perBankRdBursts::14 77 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 22367000 # Total gap between requests
+system.physmem.totGap 22446500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 468 # Read request sizes (log2)
+system.physmem.readPktSize::6 469 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -186,79 +186,82 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 264.077670 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 182.760997 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 252.156180 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 28 27.18% 27.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 32 31.07% 58.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 20 19.42% 77.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 9 8.74% 86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4 3.88% 90.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2 1.94% 92.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1 0.97% 93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 0.97% 94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6 5.83% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation
-system.physmem.totQLat 4465750 # Total ticks spent queuing
-system.physmem.totMemAccLat 13240750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2340000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9542.20 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 257.207547 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 176.154447 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 250.139569 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 32 30.19% 30.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 32 30.19% 60.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 19 17.92% 78.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 9 8.49% 86.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 3.77% 90.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 1.89% 94.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6 5.66% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation
+system.physmem.totQLat 4611250 # Total ticks spent queuing
+system.physmem.totMemAccLat 13405000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9832.09 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28292.20 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1333.93 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28582.09 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1332.15 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1333.93 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1332.15 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.42 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.42 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.41 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.41 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 355 # Number of row buffer hits during reads
+system.physmem.readRowHits 353 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 47792.74 # Average gap between requests
-system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 47860.34 # Average gap between requests
+system.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 9540945 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 12417360 # Total energy per rank (pJ)
-system.physmem_0.averagePower 784.295595 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states
+system.physmem_0.actBackEnergy 9591390 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1086000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 12431355 # Total energy per rank (pJ)
+system.physmem_0.averagePower 785.179536 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2005750 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 13485750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 13559250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 506520 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 276375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2160600 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 529200 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 288750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2176200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 14777865 # Total energy per rank (pJ)
-system.physmem_1.averagePower 933.387968 # Core power per rank (mW)
+system.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ)
+system.physmem_1.averagePower 936.587399 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2026 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1358 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 403 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1632 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 603 # Number of BTB hits
+system.cpu.branchPred.lookups 2183 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 587 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 36.948529 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 244 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 269 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 2 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 267 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -279,234 +282,234 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
-system.cpu.numCycles 44909 # number of cpu cycles simulated
+system.cpu.numCycles 45065 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8846 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12312 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2026 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4822 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 824 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12986 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2183 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing
system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 254 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14285 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.861883 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.130483 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 2047 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14454 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.898436 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.187928 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11018 77.13% 77.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1489 10.42% 87.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 118 0.83% 88.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 170 1.19% 89.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 281 1.97% 91.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 100 0.70% 92.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 134 0.94% 93.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 151 1.06% 94.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 824 5.77% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11097 76.77% 76.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1507 10.43% 87.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 110 0.76% 87.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 162 1.12% 89.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 279 1.93% 91.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 99 0.68% 91.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 140 0.97% 92.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 158 1.09% 93.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 902 6.24% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14285 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.045113 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.274154 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8398 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2675 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2714 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 372 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 164 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 14454 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.048441 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.288162 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8443 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2703 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2773 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 182 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11356 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 372 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8537 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 540 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2681 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 10925 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.decode.DecodedInsts 12006 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8593 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 592 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2745 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1156 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11571 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full
+system.cpu.rename.LQFullEvents 175 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 6515 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 12681 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 13573 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13340 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3223 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 14 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2297 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 3648 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 13 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2471 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 8637 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 7943 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3648 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1606 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14285 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.556038 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.275658 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 9030 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8122 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4040 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2024 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 14454 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.561921 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.290505 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10995 76.97% 76.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1332 9.32% 86.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 734 5.14% 91.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 438 3.07% 94.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 349 2.44% 96.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 91 0.64% 99.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 50 0.35% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11129 77.00% 77.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1334 9.23% 86.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 725 5.02% 91.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 461 3.19% 94.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 340 2.35% 96.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 284 1.96% 98.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 111 0.77% 99.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 51 0.35% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14285 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14454 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 112 63.64% 67.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 58 32.95% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 117 64.64% 68.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4723 59.46% 59.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2145 27.00% 86.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1068 13.45% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4782 58.88% 58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2272 27.97% 86.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 7943 # Type of FU issued
-system.cpu.iq.rate 0.176869 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 176 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.022158 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30363 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12303 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7281 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8122 # Type of FU issued
+system.cpu.iq.rate 0.180229 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 181 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.022285 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30894 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 13087 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7350 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8117 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8301 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1162 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1336 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 372 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10138 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 138 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2297 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10642 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2471 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 57 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7674 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2046 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 269 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7800 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2128 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1490 # number of nop insts executed
-system.cpu.iew.exec_refs 3099 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1356 # Number of branches executed
-system.cpu.iew.exec_stores 1053 # Number of stores executed
-system.cpu.iew.exec_rate 0.170879 # Inst execution rate
-system.cpu.iew.wb_sent 7358 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7283 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2837 # num instructions producing a value
-system.cpu.iew.wb_consumers 4202 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.162172 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.675155 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 4500 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 1602 # number of nop insts executed
+system.cpu.iew.exec_refs 3177 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1369 # Number of branches executed
+system.cpu.iew.exec_stores 1049 # Number of stores executed
+system.cpu.iew.exec_rate 0.173083 # Inst execution rate
+system.cpu.iew.wb_sent 7447 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7352 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2874 # num instructions producing a value
+system.cpu.iew.wb_consumers 4285 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.163142 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.670712 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 4995 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13494 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.417964 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.246672 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13572 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.415561 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.228101 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11340 84.04% 84.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 862 6.39% 90.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 508 3.76% 94.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 248 1.84% 96.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 152 1.13% 97.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 167 1.24% 98.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 61 0.45% 98.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 39 0.29% 99.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 117 0.87% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11381 83.86% 83.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 886 6.53% 90.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 519 3.82% 94.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 254 1.87% 96.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 162 1.19% 97.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 163 1.20% 98.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 62 0.46% 98.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 41 0.30% 99.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 104 0.77% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13494 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13572 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5640 # Number of instructions committed
system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -552,101 +555,101 @@ system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5640 # Class of committed instruction
-system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 23504 # The number of ROB reads
-system.cpu.rob.rob_writes 21078 # The number of ROB writes
-system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 30624 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 24090 # The number of ROB reads
+system.cpu.rob.rob_writes 22160 # The number of ROB writes
+system.cpu.timesIdled 263 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 30611 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4999 # Number of Instructions Simulated
system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.983597 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.983597 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.111314 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.111314 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10422 # number of integer regfile reads
-system.cpu.int_regfile_writes 5065 # number of integer regfile writes
+system.cpu.cpi 9.014803 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.110929 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 10573 # number of integer regfile reads
+system.cpu.int_regfile_writes 5151 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 160 # number of misc regfile reads
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 90.103369 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2304 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 16.457143 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 90.103369 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.021998 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.021998 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5766 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5766 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1748 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1748 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2304 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2304 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2304 # number of overall hits
-system.cpu.dcache.overall_hits::total 2304 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 164 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 164 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits
+system.cpu.dcache.overall_hits::total 2393 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 509 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 509 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 509 # number of overall misses
-system.cpu.dcache.overall_misses::total 509 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11628500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11628500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35643499 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35643499 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35643499 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35643499 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 512 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11867500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11867500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 24012499 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 24012499 # number of WriteReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 35879999 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 35879999 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 35879999 # number of overall miss cycles
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+system.cpu.dcache.ReadReq_accesses::total 2004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2813 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2813 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2813 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2813 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085774 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.085774 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083333 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.083333 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.180946 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.180946 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.180946 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.180946 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70905.487805 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70905.487805 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70026.520629 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70026.520629 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 70026.520629 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 70026.520629 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.176248 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.176248 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.176248 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.176248 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71062.874251 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71062.874251 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69601.446377 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69601.446377 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70078.123047 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
@@ -655,82 +658,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 140
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@@ -741,54 +744,54 @@ system.cpu.icache.fast_writes 0 # nu
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@@ -869,111 +872,111 @@ system.cpu.l2cache.fast_writes 0 # nu
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-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 261000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 418 # Transaction distribution
+system.membus.trans_dist::ReadResp 419 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 418 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 936 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 936 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 468 # Request fanout histogram
+system.membus.snoop_fanout::samples 469 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 468 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 468 # Request fanout histogram
-system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 469 # Request fanout histogram
+system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2487500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2494000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index d92d6b0d8..45a38b492 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 5053dfd9a..ff42947ce 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
index 22fffb44f..ccfdd3697 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index d2fab27ec..86ced7654 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index 5f8967148..0500fc3ab 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -146,11 +148,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index dcd8c1e4d..70134ae11 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 19923000 # Number of ticks simulated
-final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 19908000 # Number of ticks simulated
+final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 56421 # Simulator instruction rate (inst/s)
host_op_rate 56413 # Simulator op (including micro ops) rate (op/s)
@@ -14,29 +14,29 @@ sim_ops 5792 # Nu
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28352 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 444 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 444 # Number of read requests accepted
+system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 443 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1102672293 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 321478802 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1424151095 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1102672293 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1102672293 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1102672293 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 321478802 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1424151095 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 445 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::1 42 # Pe
system.physmem.perBankRdBursts::2 55 # Per bank write bursts
system.physmem.perBankRdBursts::3 58 # Per bank write bursts
system.physmem.perBankRdBursts::4 53 # Per bank write bursts
-system.physmem.perBankRdBursts::5 61 # Per bank write bursts
+system.physmem.perBankRdBursts::5 62 # Per bank write bursts
system.physmem.perBankRdBursts::6 52 # Per bank write bursts
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 9 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 19783500 # Total gap between requests
+system.physmem.totGap 19857500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 444 # Read request sizes (log2)
+system.physmem.readPktSize::6 445 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@@ -187,41 +187,41 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 340.210526 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 203.437950 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 338.690117 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 26 34.21% 34.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17 22.37% 56.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8 10.53% 67.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4 5.26% 72.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 341.894737 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 206.686426 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 337.291153 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 25 32.89% 32.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17 22.37% 55.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 10 13.16% 68.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3 3.95% 72.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation
-system.physmem.totQLat 3746750 # Total ticks spent queuing
-system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst
+system.physmem.totQLat 3759500 # Total ticks spent queuing
+system.physmem.totMemAccLat 12103250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8448.31 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27198.31 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1430.58 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1430.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.14 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.14 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.18 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.18 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.78 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 359 # Number of row buffer hits during reads
+system.physmem.readRowHits 360 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 44557.43 # Average gap between requests
-system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 44623.60 # Average gap between requests
+system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ)
@@ -241,24 +241,28 @@ system.physmem_1.preEnergy 37125 # En
system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 7628310 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ)
-system.physmem_1.averagePower 748.283278 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states
+system.physmem_1.actBackEnergy 7632585 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ)
+system.physmem_1.averagePower 748.316438 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2359 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1936 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 404 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1982 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 725 # Number of BTB hits
+system.cpu.branchPred.lookups 2407 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2054 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 691 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 36.579213 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 33.641675 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 226 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 35 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 130 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 19 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 111 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -279,235 +283,235 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
-system.cpu.numCycles 39847 # number of cpu cycles simulated
+system.cpu.numCycles 39817 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13188 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2359 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3750 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 839 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 147 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1822 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12019 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.097263 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.493815 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1856 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 289 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 11892 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.123613 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.518960 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9698 80.69% 80.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 176 1.46% 82.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 221 1.84% 83.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 153 1.27% 85.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 238 1.98% 87.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 147 1.22% 88.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 274 2.28% 90.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 116 0.97% 91.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 996 8.29% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9557 80.36% 80.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 166 1.40% 81.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 217 1.82% 83.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 147 1.24% 84.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 245 2.06% 86.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 147 1.24% 88.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 275 2.31% 90.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 148 1.24% 91.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 990 8.32% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 1924 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 271 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 317 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 11892 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.060452 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.335585 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 7298 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2243 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 1948 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 323 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11315 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 469 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 271 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7350 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 927 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 518 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1884 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1069 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 10932 # Number of instructions processed by rename
+system.cpu.decode.DecodedInsts 11471 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 450 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7466 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 447 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 1898 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1006 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11040 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 1028 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 9574 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 17720 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 17694 # Number of integer rename lookups
+system.cpu.rename.SQFullEvents 965 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 9709 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 17887 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 17861 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 4576 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 4711 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 362 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 1935 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1629 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10141 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 354 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 1936 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1591 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8840 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4412 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3358 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8811 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3468 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12019 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.735502 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.540494 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 11892 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.740918 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.536831 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8914 74.17% 74.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 959 7.98% 82.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 649 5.40% 87.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 465 3.87% 91.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 426 3.54% 94.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 281 2.34% 97.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 228 1.90% 99.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 65 0.54% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8764 73.70% 73.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 985 8.28% 81.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 659 5.54% 87.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 457 3.84% 91.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 433 3.64% 95.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 285 2.40% 97.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 215 1.81% 99.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 62 0.52% 99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12019 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 11892 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 13 6.47% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 95 47.26% 53.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 93 46.27% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 12 6.35% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 87 46.03% 52.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 90 47.62% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5519 62.43% 62.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1819 20.58% 83.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5533 62.80% 62.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1812 20.57% 83.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1464 16.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8840 # Type of FU issued
-system.cpu.iq.rate 0.221849 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 201 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 14587 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8120 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8811 # Type of FU issued
+system.cpu.iq.rate 0.221287 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 189 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.021450 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 29694 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 14646 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8112 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9007 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8966 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 974 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 975 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 583 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 545 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 271 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 843 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 716 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10204 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 1935 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1629 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 1936 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1591 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 72 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 254 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 326 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1707 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8460 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1699 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 351 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3121 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1355 # Number of branches executed
-system.cpu.iew.exec_stores 1414 # Number of stores executed
-system.cpu.iew.exec_rate 0.212939 # Inst execution rate
-system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8147 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 4452 # num instructions producing a value
-system.cpu.iew.wb_consumers 7114 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs 3077 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1357 # Number of branches executed
+system.cpu.iew.exec_stores 1378 # Number of stores executed
+system.cpu.iew.exec_rate 0.212472 # Inst execution rate
+system.cpu.iew.wb_sent 8239 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8139 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 4434 # num instructions producing a value
+system.cpu.iew.wb_consumers 7122 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.204410 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.622578 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 265 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11324 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.511480 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.378975 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11191 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.517559 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.381685 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9160 80.89% 80.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 847 7.48% 88.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 528 4.66% 93.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 216 1.91% 94.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 182 1.61% 96.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 106 0.94% 97.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 122 1.08% 98.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 53 0.47% 99.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 110 0.97% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9014 80.55% 80.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 859 7.68% 88.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 529 4.73% 92.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 217 1.94% 94.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 185 1.65% 96.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 107 0.96% 97.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 121 1.08% 98.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 49 0.44% 99.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 110 0.98% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11324 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11191 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -554,83 +558,83 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 21420 # The number of ROB reads
-system.cpu.rob.rob_writes 21108 # The number of ROB writes
-system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 21317 # The number of ROB reads
+system.cpu.rob.rob_writes 21174 # The number of ROB writes
+system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 27925 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 13452 # number of integer regfile reads
-system.cpu.int_regfile_writes 7138 # number of integer regfile writes
+system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 13370 # number of integer regfile reads
+system.cpu.int_regfile_writes 7150 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.025146 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5395 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5395 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1492 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1492 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2213 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2213 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2213 # number of overall hits
-system.cpu.dcache.overall_hits::total 2213 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 108 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 108 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 433 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses
-system.cpu.dcache.overall_misses::total 433 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits
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+system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits
+system.cpu.dcache.overall_hits::total 2199 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 324 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 324 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses
+system.cpu.dcache.overall_misses::total 437 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 7807000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 7807000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 23805496 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 23805496 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 31612496 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 31612496 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 31612496 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 31612496 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1590 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1590 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2646 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2646 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2646 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2646 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067500 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.067500 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071069 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.071069 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.309751 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.309751 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.165781 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.165781 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.165781 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.165781 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69088.495575 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69088.495575 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73473.753086 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73473.753086 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72339.807780 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
@@ -639,98 +643,98 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
@@ -739,54 +743,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -869,108 +873,108 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47
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system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 446 98.24% 98.24% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 8 1.76% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 154500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 397 # Transaction distribution
+system.membus.trans_dist::ReadResp 396 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 444 # Request fanout histogram
+system.membus.snoop_fanout::samples 445 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 444 # Request fanout histogram
-system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 445 # Request fanout histogram
+system.membus.reqLayer0.occupancy 553500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2342750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 11.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2338750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index ba8c1a81b..ae31c4fe2 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -151,6 +153,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 69aa27452..bf044682b 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -150,6 +152,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index d164e90c1..0ce55f79c 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
index 22fffb44f..ccfdd3697 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index d3f83cbb3..75416425d 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -180,7 +180,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -215,6 +214,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -280,6 +280,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 32ecb514b..81a7b3677 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -151,11 +153,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 0cc3ebf21..9accffb70 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
-sim_ticks 20818000 # Number of ticks simulated
-final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 21273500 # Number of ticks simulated
+final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 39176 # Simulator instruction rate (inst/s)
host_op_rate 70969 # Simulator op (including micro ops) rate (op/s)
@@ -13,48 +13,48 @@ sim_insts 5380 # Nu
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26560 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 415 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 415 # Number of read requests accepted
+system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 833337251 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 418172844 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1251510095 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 833337251 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 833337251 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 833337251 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 418172844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1251510095 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 416 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 416 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 26624 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 26624 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 32 # Per bank write bursts
+system.physmem.perBankRdBursts::0 31 # Per bank write bursts
system.physmem.perBankRdBursts::1 1 # Per bank write bursts
-system.physmem.perBankRdBursts::2 6 # Per bank write bursts
+system.physmem.perBankRdBursts::2 5 # Per bank write bursts
system.physmem.perBankRdBursts::3 8 # Per bank write bursts
-system.physmem.perBankRdBursts::4 50 # Per bank write bursts
-system.physmem.perBankRdBursts::5 46 # Per bank write bursts
+system.physmem.perBankRdBursts::4 51 # Per bank write bursts
+system.physmem.perBankRdBursts::5 44 # Per bank write bursts
system.physmem.perBankRdBursts::6 21 # Per bank write bursts
-system.physmem.perBankRdBursts::7 33 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25 # Per bank write bursts
-system.physmem.perBankRdBursts::9 72 # Per bank write bursts
-system.physmem.perBankRdBursts::10 63 # Per bank write bursts
+system.physmem.perBankRdBursts::7 37 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23 # Per bank write bursts
+system.physmem.perBankRdBursts::9 71 # Per bank write bursts
+system.physmem.perBankRdBursts::10 64 # Per bank write bursts
system.physmem.perBankRdBursts::11 16 # Per bank write bursts
system.physmem.perBankRdBursts::12 2 # Per bank write bursts
-system.physmem.perBankRdBursts::13 17 # Per bank write bursts
+system.physmem.perBankRdBursts::13 19 # Per bank write bursts
system.physmem.perBankRdBursts::14 6 # Per bank write bursts
system.physmem.perBankRdBursts::15 17 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 20722000 # Total gap between requests
+system.physmem.totGap 21151500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 415 # Read request sizes (log2)
+system.physmem.readPktSize::6 416 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -92,9 +92,9 @@ system.physmem.writePktSize::5 0 # Wr
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -186,308 +186,313 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 96 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 252 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 164.484740 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 262.126687 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 35 36.46% 36.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 26 27.08% 63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 15 15.62% 79.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 6 6.25% 85.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 3.12% 88.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3 3.12% 91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2 2.08% 93.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 1.04% 94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5 5.21% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 96 # Bytes accessed per row activation
-system.physmem.totQLat 4745000 # Total ticks spent queuing
-system.physmem.totMemAccLat 12526250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 162.086023 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 265.276929 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 37 38.14% 38.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 25 25.77% 63.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 18 18.56% 82.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 2.06% 89.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4 4.12% 93.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation
+system.physmem.totQLat 4187000 # Total ticks spent queuing
+system.physmem.totMemAccLat 11987000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2080000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10064.90 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28814.90 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1251.51 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1251.51 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 9.97 # Data bus utilization in percentage
-system.physmem.busUtilRead 9.97 # Data bus utilization in percentage for reads
+system.physmem.busUtil 9.78 # Data bus utilization in percentage
+system.physmem.busUtilRead 9.78 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 309 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 74.28 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 49932.53 # Average gap between requests
-system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 959400 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 50844.95 # Average gap between requests
+system.physmem.pageHitRate 74.28 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 920400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 13105245 # Total energy per rank (pJ)
-system.physmem_0.averagePower 827.743250 # Core power per rank (mW)
+system.physmem_0.totalEnergy 13042875 # Total energy per rank (pJ)
+system.physmem_0.averagePower 823.803884 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 423360 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 231000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1536600 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 14021235 # Total energy per rank (pJ)
-system.physmem_1.averagePower 885.598295 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 271750 # Time in different power states
+system.physmem_1.totalEnergy 13993950 # Total energy per rank (pJ)
+system.physmem_1.averagePower 883.874941 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 262750 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 3234 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3234 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 514 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2557 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 881 # Number of BTB hits
+system.cpu.branchPred.lookups 3510 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2934 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 0 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 34.454439 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 86 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 413 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 93 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 2934 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 493 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 41637 # number of cpu cycles simulated
+system.cpu.numCycles 42548 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14637 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3234 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1161 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9674 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines 2075 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 22725 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.149527 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.648759 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 11447 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 15916 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3510 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 906 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 9652 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1329 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1405 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 2036 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 23302 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.230495 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.752458 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 18699 82.28% 82.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 221 0.97% 83.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 146 0.64% 83.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 231 1.02% 84.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 214 0.94% 85.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 258 1.14% 86.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 336 1.48% 88.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 205 0.90% 89.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2415 10.63% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 19034 81.68% 81.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 165 0.71% 82.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 157 0.67% 83.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 234 1.00% 84.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 217 0.93% 85.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 212 0.91% 85.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 264 1.13% 87.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 172 0.74% 87.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2847 12.22% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3206 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 406 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 24310 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 11710 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1815 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1004 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3327 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4290 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 23005 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 71 # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents 4163 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 26169 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57126 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 32219 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 23302 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.082495 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.374072 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 11533 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 7244 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3404 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 664 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 26617 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 664 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 11798 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1942 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1135 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 3557 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4206 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 25098 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents 4073 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 61205 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 35038 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 15106 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 1472 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2371 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1574 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 20 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 20445 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 17161 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10724 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 15317 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 22725 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.755160 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.702113 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 25 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 1412 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2736 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1550 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 21864 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 18142 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 143 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 16726 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 23302 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.778560 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.752623 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17737 78.05% 78.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1126 4.95% 83.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 880 3.87% 86.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 631 2.78% 89.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 810 3.56% 93.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 590 2.60% 95.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 568 2.50% 98.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 280 1.23% 99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 103 0.45% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 18136 77.83% 77.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1211 5.20% 83.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 861 3.69% 86.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 568 2.44% 89.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 833 3.57% 92.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 596 2.56% 95.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 620 2.66% 97.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 343 1.47% 99.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 134 0.58% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 22725 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 23302 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 151 71.23% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 43 20.28% 91.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 18 8.49% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 211 76.17% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 50 18.05% 94.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 16 5.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 13707 79.87% 79.89% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 4 0.02% 79.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2071 12.07% 92.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 14465 79.73% 79.74% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2325 12.82% 92.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1337 7.37% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 17161 # Type of FU issued
-system.cpu.iq.rate 0.412157 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 212 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 31202 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 15767 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 18142 # Type of FU issued
+system.cpu.iq.rate 0.426389 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 277 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.015268 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 59998 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 34032 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 16436 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 17366 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 18413 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 220 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 190 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1318 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1683 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 639 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 615 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 579 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1449 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 20471 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2371 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1574 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 660 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 16265 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1913 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 896 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 664 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1478 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 139 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 21887 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2736 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1550 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 138 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 682 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 801 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 17060 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1082 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3175 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1626 # Number of branches executed
-system.cpu.iew.exec_stores 1262 # Number of stores executed
-system.cpu.iew.exec_rate 0.390638 # Inst execution rate
-system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 15771 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 10637 # num instructions producing a value
-system.cpu.iew.wb_consumers 16589 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs 3326 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1722 # Number of branches executed
+system.cpu.iew.exec_stores 1245 # Number of stores executed
+system.cpu.iew.exec_rate 0.400959 # Inst execution rate
+system.cpu.iew.wb_sent 16760 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 16440 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 11045 # num instructions producing a value
+system.cpu.iew.wb_consumers 17238 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.386387 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.640736 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 12139 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 565 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 20943 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.465406 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.357230 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 652 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 21245 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.458790 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.350767 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 17686 84.45% 84.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 994 4.75% 89.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 561 2.68% 91.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 764 3.65% 95.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 370 1.77% 97.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 129 0.62% 97.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 114 0.54% 98.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70 0.33% 98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 255 1.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 17995 84.70% 84.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 991 4.66% 89.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 576 2.71% 92.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 726 3.42% 95.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 383 1.80% 97.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 128 0.60% 97.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 121 0.57% 98.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 72 0.34% 98.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 253 1.19% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 20943 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 21245 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -533,307 +538,307 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
-system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 41158 # The number of ROB reads
-system.cpu.rob.rob_writes 42744 # The number of ROB writes
-system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 253 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 42878 # The number of ROB reads
+system.cpu.rob.rob_writes 45859 # The number of ROB writes
+system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 19246 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 20872 # number of integer regfile reads
-system.cpu.int_regfile_writes 12651 # number of integer regfile writes
+system.cpu.cpi 7.908550 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.908550 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.126445 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.126445 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 21687 # number of integer regfile reads
+system.cpu.int_regfile_writes 13280 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
-system.cpu.cc_regfile_reads 8081 # number of cc regfile reads
-system.cpu.cc_regfile_writes 4880 # number of cc regfile writes
-system.cpu.misc_regfile_reads 7277 # number of misc regfile reads
+system.cpu.cc_regfile_reads 8296 # number of cc regfile reads
+system.cpu.cc_regfile_writes 5092 # number of cc regfile writes
+system.cpu.misc_regfile_reads 7660 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 18.582734 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 81.534494 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.019906 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.019906 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5305 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5305 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1525 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1525 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2383 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2383 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2383 # number of overall hits
-system.cpu.dcache.overall_hits::total 2383 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 200 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 200 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 200 # number of overall misses
-system.cpu.dcache.overall_misses::total 200 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9653500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9653500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 6433000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 16086500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 16086500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 16086500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 16086500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1648 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1648 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18669500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4722500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4722500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18669500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10010000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 28679500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18669500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10010000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 28679500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996390 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997596 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997602 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997596 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71045.454545 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71045.454545 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69317.028986 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69317.028986 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73758.064516 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997602 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67398.916968 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67398.916968 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73789.062500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73789.062500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 277 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 554 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17728 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 834 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 417 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.002398 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.048970 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 416 99.76% 99.76% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 417 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 415500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 338 # Transaction distribution
-system.membus.trans_dist::ReadExReq 77 # Transaction distribution
-system.membus.trans_dist::ReadExResp 77 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 338 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 830 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 830 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 830 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 26560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 341 # Transaction distribution
+system.membus.trans_dist::ReadExReq 75 # Transaction distribution
+system.membus.trans_dist::ReadExResp 75 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 341 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 832 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 415 # Request fanout histogram
+system.membus.snoop_fanout::samples 416 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 415 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 415 # Request fanout histogram
-system.membus.reqLayer0.occupancy 500000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 416 # Request fanout histogram
+system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2216750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 10.6 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 10.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index 54a08b276..4a2074e15 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -184,6 +186,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index a9f89f42a..f585dbbc0 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
index 22fffb44f..ccfdd3697 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index ea6813a1a..ca3cb5481 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -94,7 +96,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -146,7 +147,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -214,7 +214,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -249,6 +248,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -314,6 +314,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
index 13061b3ec..99297fbad 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
@@ -29,6 +29,8 @@ multi_thread=true
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=2
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
index 7854782f4..ffcf45f3b 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000025 # Number of seconds simulated
-sim_ticks 24794500 # Number of ticks simulated
-final_tick 24794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000026 # Number of seconds simulated
+sim_ticks 25580500 # Number of ticks simulated
+final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50796 # Simulator instruction rate (inst/s)
host_op_rate 50792 # Simulator op (including micro ops) rate (op/s)
@@ -13,50 +13,50 @@ sim_insts 12770 # Nu
sim_ops 12770 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 40320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22080 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 40320 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 40320 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 630 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 345 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1626167094 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 890520075 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2516687169 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1626167094 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1626167094 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1626167094 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 890520075 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2516687169 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 975 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 39680 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory
+system.physmem.bytes_read::total 61504 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 39680 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 39680 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 620 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 341 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 961 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1551181564 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 853149860 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2404331424 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1551181564 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1551181564 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1551181564 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 853149860 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2404331424 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 962 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 962 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 61568 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 61568 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 85 # Per bank write bursts
-system.physmem.perBankRdBursts::1 151 # Per bank write bursts
+system.physmem.perBankRdBursts::0 83 # Per bank write bursts
+system.physmem.perBankRdBursts::1 150 # Per bank write bursts
system.physmem.perBankRdBursts::2 78 # Per bank write bursts
system.physmem.perBankRdBursts::3 59 # Per bank write bursts
system.physmem.perBankRdBursts::4 86 # Per bank write bursts
-system.physmem.perBankRdBursts::5 49 # Per bank write bursts
+system.physmem.perBankRdBursts::5 46 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdBursts::7 50 # Per bank write bursts
-system.physmem.perBankRdBursts::8 43 # Per bank write bursts
-system.physmem.perBankRdBursts::9 39 # Per bank write bursts
-system.physmem.perBankRdBursts::10 29 # Per bank write bursts
+system.physmem.perBankRdBursts::8 41 # Per bank write bursts
+system.physmem.perBankRdBursts::9 37 # Per bank write bursts
+system.physmem.perBankRdBursts::10 28 # Per bank write bursts
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
system.physmem.perBankRdBursts::13 120 # Per bank write bursts
-system.physmem.perBankRdBursts::14 68 # Per bank write bursts
-system.physmem.perBankRdBursts::15 37 # Per bank write bursts
+system.physmem.perBankRdBursts::14 67 # Per bank write bursts
+system.physmem.perBankRdBursts::15 36 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 24650000 # Total gap between requests
+system.physmem.totGap 25549500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 975 # Read request sizes (log2)
+system.physmem.readPktSize::6 962 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,14 +90,14 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 354 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 350 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 315 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
@@ -186,100 +186,104 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 215 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 283.088372 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 180.093050 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 284.959526 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 71 33.02% 33.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 62 28.84% 61.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 23 10.70% 72.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 14 6.51% 79.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 10 4.65% 83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 14 6.51% 90.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5 2.33% 92.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3 1.40% 93.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 13 6.05% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 215 # Bytes accessed per row activation
-system.physmem.totQLat 13049000 # Total ticks spent queuing
-system.physmem.totMemAccLat 31330250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13383.59 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 281.722488 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 176.924618 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 290.527007 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 69 33.01% 33.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 64 30.62% 63.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 20 9.57% 73.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 12 5.74% 78.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 11 5.26% 84.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 8 3.83% 88.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 9 4.31% 92.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 4 1.91% 94.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 12 5.74% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation
+system.physmem.totQLat 12704750 # Total ticks spent queuing
+system.physmem.totMemAccLat 30742250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4810000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13206.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 32133.59 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2516.69 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31956.60 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2406.83 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2516.69 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2406.83 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 19.66 # Data bus utilization in percentage
-system.physmem.busUtilRead 19.66 # Data bus utilization in percentage for reads
+system.physmem.busUtil 18.80 # Data bus utilization in percentage
+system.physmem.busUtilRead 18.80 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 2.38 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 751 # Number of row buffer hits during reads
+system.physmem.readRowHits 743 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 77.23 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 25282.05 # Average gap between requests
-system.physmem.pageHitRate 77.03 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4531800 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 26558.73 # Average gap between requests
+system.physmem.pageHitRate 77.23 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 824040 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 449625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4453800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 16120170 # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 23622915 # Total energy per rank (pJ)
-system.physmem_0.averagePower 998.485338 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
+system.physmem_0.totalEnergy 23400705 # Total energy per rank (pJ)
+system.physmem_0.averagePower 990.768140 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 694500 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 22869500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2854800 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 733320 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 400125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2683200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 15614010 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 495000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 21576195 # Total energy per rank (pJ)
-system.physmem_1.averagePower 912.216256 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 727500 # Time in different power states
+system.physmem_1.actBackEnergy 15873930 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 21463005 # Total energy per rank (pJ)
+system.physmem_1.averagePower 908.727388 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 326750 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 22158250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 22525750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 6577 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3752 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1243 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 4859 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 1038 # Number of BTB hits
+system.cpu.branchPred.lookups 4883 # Number of BP lookups
+system.cpu.branchPred.condPredicted 2924 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 790 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 3812 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 1143 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 21.362420 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1078 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 29.984260 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 681 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 53 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 814 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 150 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 664 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4547 # DTB read hits
-system.cpu.dtb.read_misses 85 # DTB read misses
+system.cpu.dtb.read_hits 4166 # DTB read hits
+system.cpu.dtb.read_misses 75 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4632 # DTB read accesses
-system.cpu.dtb.write_hits 2078 # DTB write hits
-system.cpu.dtb.write_misses 69 # DTB write misses
+system.cpu.dtb.read_accesses 4241 # DTB read accesses
+system.cpu.dtb.write_hits 1988 # DTB write hits
+system.cpu.dtb.write_misses 49 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2147 # DTB write accesses
-system.cpu.dtb.data_hits 6625 # DTB hits
-system.cpu.dtb.data_misses 154 # DTB misses
+system.cpu.dtb.write_accesses 2037 # DTB write accesses
+system.cpu.dtb.data_hits 6154 # DTB hits
+system.cpu.dtb.data_misses 124 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 6779 # DTB accesses
-system.cpu.itb.fetch_hits 5175 # ITB hits
+system.cpu.dtb.data_accesses 6278 # DTB accesses
+system.cpu.itb.fetch_hits 3823 # ITB hits
system.cpu.itb.fetch_misses 51 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5226 # ITB accesses
+system.cpu.itb.fetch_accesses 3874 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -294,312 +298,312 @@ system.cpu.itb.data_acv 0 # DT
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 49590 # number of cpu cycles simulated
+system.cpu.numCycles 51162 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 1137 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 37512 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6577 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 2116 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 11769 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1328 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5175 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 779 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 28288 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.326075 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.708941 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 749 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 28166 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 4883 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1974 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 9785 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 559 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 3823 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 26518 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.062146 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.446390 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 21788 77.02% 77.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 562 1.99% 79.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 445 1.57% 80.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 567 2.00% 82.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 586 2.07% 84.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 389 1.38% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 492 1.74% 87.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 554 1.96% 89.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2905 10.27% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21410 80.74% 80.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 517 1.95% 82.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 399 1.50% 84.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 426 1.61% 85.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 581 2.19% 87.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 343 1.29% 89.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 470 1.77% 91.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 262 0.99% 92.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2110 7.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 28288 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.132628 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.756443 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38487 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 11291 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 4912 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 546 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1060 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 470 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 278 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 30785 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 643 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1060 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 39027 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4538 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1512 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 4932 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5227 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 29058 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 481 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 927 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 3808 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 21804 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 36221 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 36203 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 26518 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.095442 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.550526 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35549 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 11706 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 4004 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 486 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 721 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 379 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 24714 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 389 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 721 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 35923 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4419 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1518 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 4115 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5770 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 23686 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 47 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 451 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 687 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 4626 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 17749 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 29662 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 29644 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 12650 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 60 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2095 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2679 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1390 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2734 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1411 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads.
-system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 25901 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21580 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 13182 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 7478 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 28288 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.762868 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.484406 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 8595 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 57 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 1784 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2582 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1268 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads 1972 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1081 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads.
+system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 21922 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 19305 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 9201 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4899 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 26518 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.727996 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.455439 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 20144 71.21% 71.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 2630 9.30% 80.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1862 6.58% 87.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1311 4.63% 91.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1169 4.13% 95.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 655 2.32% 98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 329 1.16% 99.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 136 0.48% 99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 52 0.18% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 19215 72.46% 72.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 2319 8.75% 81.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1762 6.64% 87.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1149 4.33% 92.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1009 3.80% 95.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 611 2.30% 98.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 303 1.14% 99.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 94 0.35% 99.79% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 28288 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 26518 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 37 11.97% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 189 61.17% 73.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 83 26.86% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 25 8.33% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 8.33% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 8.33% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.33% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 198 66.00% 74.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 77 25.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7104 66.24% 66.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2483 23.15% 89.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1132 10.56% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 6801 65.70% 65.72% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.73% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2445 23.62% 89.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1101 10.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10724 # Type of FU issued
+system.cpu.iq.FU_type_0::total 10352 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7199 66.31% 66.33% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.34% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.34% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2532 23.32% 89.68% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1120 10.32% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 5921 66.13% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.17% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.17% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead 2023 22.60% 88.79% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1004 11.21% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 10856 # Type of FU issued
-system.cpu.iq.FU_type::total 21580 0.00% 0.00% # Type of FU issued
-system.cpu.iq.rate 0.435168 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 153 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 156 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 309 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.007090 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.007229 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.014319 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 71845 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 39156 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19068 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total 8953 # Type of FU issued
+system.cpu.iq.FU_type::total 19305 0.00% 0.00% # Type of FU issued
+system.cpu.iq.rate 0.377331 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 140 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.008288 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.007252 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.015540 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 65432 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 31184 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 17495 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21863 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 19579 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 93 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1494 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 525 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1397 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 403 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 275 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 81 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1549 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 25 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 546 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads 787 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 216 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 273 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 280 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1060 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2492 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 405 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 26102 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 214 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5413 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2801 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 387 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 43 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 158 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1006 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1164 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20390 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2303 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2335 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4638 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2770 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 755 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 22107 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 169 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 4554 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2349 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 22 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 722 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 639 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 771 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 18606 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0 2294 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1 1956 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4250 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 699 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 75 # number of nop insts executed
-system.cpu.iew.exec_nop::1 74 # number of nop insts executed
-system.cpu.iew.exec_nop::total 149 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3395 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3403 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 6798 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1585 # Number of branches executed
-system.cpu.iew.exec_branches::1 1614 # Number of branches executed
-system.cpu.iew.exec_branches::total 3199 # Number of branches executed
-system.cpu.iew.exec_stores::0 1092 # Number of stores executed
-system.cpu.iew.exec_stores::1 1068 # Number of stores executed
-system.cpu.iew.exec_stores::total 2160 # Number of stores executed
-system.cpu.iew.exec_rate 0.411172 # Inst execution rate
-system.cpu.iew.wb_sent::0 9687 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9764 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 19451 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9532 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9556 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19088 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 5025 # num instructions producing a value
-system.cpu.iew.wb_producers::1 5077 # num instructions producing a value
-system.cpu.iew.wb_producers::total 10102 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6671 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6701 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 13372 # num instructions consuming a value
-system.cpu.iew.wb_rate::0 0.192216 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.192700 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.384916 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.753260 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.757648 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.755459 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 13275 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop::0 68 # number of nop insts executed
+system.cpu.iew.exec_nop::1 67 # number of nop insts executed
+system.cpu.iew.exec_nop::total 135 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3353 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 2946 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6299 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1561 # Number of branches executed
+system.cpu.iew.exec_branches::1 1400 # Number of branches executed
+system.cpu.iew.exec_branches::total 2961 # Number of branches executed
+system.cpu.iew.exec_stores::0 1059 # Number of stores executed
+system.cpu.iew.exec_stores::1 990 # Number of stores executed
+system.cpu.iew.exec_stores::total 2049 # Number of stores executed
+system.cpu.iew.exec_rate 0.363668 # Inst execution rate
+system.cpu.iew.wb_sent::0 9443 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 8345 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 17788 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9266 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 8249 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 17515 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 4880 # num instructions producing a value
+system.cpu.iew.wb_producers::1 4386 # num instructions producing a value
+system.cpu.iew.wb_producers::total 9266 # num instructions producing a value
+system.cpu.iew.wb_consumers::0 6580 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 5911 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 12491 # num instructions consuming a value
+system.cpu.iew.wb_rate::0 0.181111 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.161233 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.342344 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.741641 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.742006 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.741814 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 9276 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 976 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 28256 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.453143 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.335890 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 642 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 26498 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.483206 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.376058 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23155 81.95% 81.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 2552 9.03% 90.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1012 3.58% 94.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 380 1.34% 95.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 269 0.95% 96.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 177 0.63% 97.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 194 0.69% 98.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 173 0.61% 98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 344 1.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 21430 80.87% 80.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 2543 9.60% 90.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 900 3.40% 93.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 463 1.75% 95.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 308 1.16% 96.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 165 0.62% 97.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 178 0.67% 98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 141 0.53% 98.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 370 1.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 28256 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 26498 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6402 # Number of instructions committed
system.cpu.commit.committedInsts::1 6402 # Number of instructions committed
system.cpu.commit.committedInsts::total 12804 # Number of instructions committed
@@ -701,25 +705,25 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::total 6402 # Class of committed instruction
system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events 344 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 128366 # The number of ROB reads
-system.cpu.rob.rob_writes 54620 # The number of ROB writes
-system.cpu.timesIdled 375 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 21302 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 370 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 113336 # The number of ROB reads
+system.cpu.rob.rob_writes 45860 # The number of ROB writes
+system.cpu.timesIdled 410 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 24644 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6385 # Number of Instructions Simulated
system.cpu.committedInsts::1 6385 # Number of Instructions Simulated
system.cpu.committedInsts::total 12770 # Number of Instructions Simulated
system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0 7.766641 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 7.766641 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.883320 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.128756 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.128756 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.257512 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 25695 # number of integer regfile reads
-system.cpu.int_regfile_writes 14528 # number of integer regfile writes
+system.cpu.cpi::0 8.012843 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 8.012843 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 4.006421 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.124800 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.124800 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.249599 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 23495 # number of integer regfile reads
+system.cpu.int_regfile_writes 13160 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
@@ -727,300 +731,300 @@ system.cpu.misc_regfile_writes 2 # nu
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 213.419877 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 4643 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 345 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.457971 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 216.394211 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 4263 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 341 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 12.501466 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 213.419877 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.052104 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.052104 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.084229 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 11689 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 11689 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 3618 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3618 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1025 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1025 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 4643 # number of demand (read+write) hits
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-system.cpu.l2cache.demand_avg_miss_latency::total 82332.820513 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80734.126984 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85252.173913 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82332.820513 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.996891 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86291.095890 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86291.095890 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79729.032258 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79729.032258 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86382.653061 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86382.653061 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79729.032258 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86343.567251 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82080.561331 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79729.032258 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86343.567251 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82080.561331 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1029,113 +1033,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 144 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 144 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 630 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 630 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 201 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 201 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 630 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 630 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10598000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10598000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44562500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44562500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15364000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15364000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44562500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25962000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 70524500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44562500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25962000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 70524500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 620 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 620 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 196 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 196 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 620 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 620 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 962 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11138500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11138500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43232000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43232000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14981000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14981000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43232000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26119500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 69351500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43232000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26119500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 69351500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996835 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995185 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.996891 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73597.222222 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73597.222222 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70734.126984 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70734.126984 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76437.810945 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76437.810945 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70734.126984 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75252.173913 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72332.820513 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70734.126984 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75252.173913 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72332.820513 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.996891 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76291.095890 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76291.095890 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69729.032258 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69729.032258 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76433.673469 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76433.673469 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 985 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 972 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 833 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 144 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 144 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 632 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 201 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1272 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 690 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40960 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22080 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 63040 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp 818 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 623 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 196 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1936 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40320 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 62144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.002047 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.045222 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 965 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.002073 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.045502 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 975 99.80% 99.80% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 963 99.79% 99.79% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 500500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 948000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 517500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 831 # Transaction distribution
-system.membus.trans_dist::ReadExReq 144 # Transaction distribution
-system.membus.trans_dist::ReadExResp 144 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 831 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::total 965 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 934500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 3.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 511500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
+system.membus.trans_dist::ReadResp 815 # Transaction distribution
+system.membus.trans_dist::ReadExReq 146 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 816 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1923 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1923 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 61504 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 975 # Request fanout histogram
+system.membus.snoop_fanout::samples 962 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 962 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 975 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1186000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 4.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 5196500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 21.0 # Layer utilization (%)
+system.membus.snoop_fanout::total 962 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1181000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 4.6 # Layer utilization (%)
+system.membus.respLayer1.occupancy 5115750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 20.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 92cd3c63d..d8bc200f7 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index cab027d03..d7b61e924 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000027 # Number of seconds simulated
-sim_ticks 26944000 # Number of ticks simulated
-final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000029 # Number of seconds simulated
+sim_ticks 28845500 # Number of ticks simulated
+final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 12271 # Simulator instruction rate (inst/s)
host_op_rate 12271 # Simulator op (including micro ops) rate (op/s)
@@ -13,50 +13,50 @@ sim_insts 14436 # Nu
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 21888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
-system.physmem.bytes_read::total 31296 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21888 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 32640 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 489 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 812351544 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 349168646 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1161520190 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 812351544 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 812351544 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 812351544 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 349168646 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1161520190 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 489 # Number of read requests accepted
+system.physmem.num_reads::total 510 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 511 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 31296 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 31296 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 107 # Per bank write bursts
-system.physmem.perBankRdBursts::1 27 # Per bank write bursts
-system.physmem.perBankRdBursts::2 49 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24 # Per bank write bursts
-system.physmem.perBankRdBursts::4 20 # Per bank write bursts
+system.physmem.perBankRdBursts::0 105 # Per bank write bursts
+system.physmem.perBankRdBursts::1 28 # Per bank write bursts
+system.physmem.perBankRdBursts::2 53 # Per bank write bursts
+system.physmem.perBankRdBursts::3 27 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
-system.physmem.perBankRdBursts::7 36 # Per bank write bursts
-system.physmem.perBankRdBursts::8 4 # Per bank write bursts
-system.physmem.perBankRdBursts::9 2 # Per bank write bursts
-system.physmem.perBankRdBursts::10 1 # Per bank write bursts
+system.physmem.perBankRdBursts::7 38 # Per bank write bursts
+system.physmem.perBankRdBursts::8 7 # Per bank write bursts
+system.physmem.perBankRdBursts::9 4 # Per bank write bursts
+system.physmem.perBankRdBursts::10 2 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
-system.physmem.perBankRdBursts::12 56 # Per bank write bursts
+system.physmem.perBankRdBursts::12 57 # Per bank write bursts
system.physmem.perBankRdBursts::13 31 # Per bank write bursts
-system.physmem.perBankRdBursts::14 61 # Per bank write bursts
-system.physmem.perBankRdBursts::15 39 # Per bank write bursts
+system.physmem.perBankRdBursts::14 63 # Per bank write bursts
+system.physmem.perBankRdBursts::15 41 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 26891000 # Total gap between requests
+system.physmem.totGap 28814000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 489 # Read request sizes (log2)
+system.physmem.readPktSize::6 511 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 297 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -186,304 +186,308 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 73 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 396.273973 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 268.840282 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 332.152795 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12 16.44% 16.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 20 27.40% 43.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 11 15.07% 58.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7 9.59% 68.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 6 8.22% 76.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1 1.37% 78.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5 6.85% 84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 1.37% 86.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 10 13.70% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 73 # Bytes accessed per row activation
-system.physmem.totQLat 3681750 # Total ticks spent queuing
-system.physmem.totMemAccLat 12850500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2445000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation
+system.physmem.totQLat 3584250 # Total ticks spent queuing
+system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1161.52 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1161.52 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 9.07 # Data bus utilization in percentage
-system.physmem.busUtilRead 9.07 # Data bus utilization in percentage for reads
+system.physmem.busUtil 8.86 # Data bus utilization in percentage
+system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 409 # Number of row buffer hits during reads
+system.physmem.readRowHits 428 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 54991.82 # Average gap between requests
-system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 56387.48 # Average gap between requests
+system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 15849990 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 267750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 20193420 # Total energy per rank (pJ)
-system.physmem_0.averagePower 854.974120 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 363750 # Time in different power states
+system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ)
+system.physmem_0.averagePower 856.515480 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 22488750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ)
+system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 15637950 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ)
-system.physmem_1.averagePower 817.549616 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2040000 # Time in different power states
+system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ)
+system.physmem_1.averagePower 820.243027 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 8026 # Number of BP lookups
-system.cpu.branchPred.condPredicted 5198 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 978 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 5876 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 3165 # Number of BTB hits
+system.cpu.branchPred.lookups 12618 # Number of BP lookups
+system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 0 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 53.863172 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 554 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 53889 # number of cpu cycles simulated
+system.cpu.numCycles 57692 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 13792 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 15452 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 6095 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 549 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 31410 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.183699 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.297330 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 20227 64.40% 64.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5497 17.50% 81.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 701 2.23% 84.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 561 1.79% 85.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 758 2.41% 88.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 907 2.89% 91.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 332 1.06% 92.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 377 1.20% 93.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2050 6.53% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.148936 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.689937 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 6549 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 597 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1074 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 28093 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1074 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 11557 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 929 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9876 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 6585 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1389 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 25671 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 7933 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 7918 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
-system.cpu.rename.SQFullEvents 994 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 23124 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 48097 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 39637 # Number of integer rename lookups
+system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9305 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 731 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 747 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 3478 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 3489 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2288 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 22031 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 704 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 20835 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8299 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 5262 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 229 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 31410 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.663324 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.403192 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 796 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 23338 74.30% 74.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 2945 9.38% 83.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1556 4.95% 88.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1448 4.61% 93.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 938 2.99% 96.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 645 2.05% 98.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 357 1.14% 99.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 149 0.47% 99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 34 0.11% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 31410 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 59 33.33% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 51 28.81% 62.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 67 37.85% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 15392 73.88% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3355 16.10% 89.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 20835 # Type of FU issued
-system.cpu.iq.rate 0.386628 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 31060 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19408 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 25362 # Type of FU issued
+system.cpu.iq.rate 0.439610 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 294 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21012 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1264 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 840 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1074 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 918 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 23852 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 173 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 3489 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2288 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 704 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 261 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 835 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1096 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20012 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 3241 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 823 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
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-system.cpu.iew.wb_count 19408 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 9326 # num instructions producing a value
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-system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit
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system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 978 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::2 1108 3.74% 93.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 619 2.09% 95.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 326 1.10% 96.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 270 0.91% 97.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 381 1.29% 98.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 67 0.23% 99.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 290 0.98% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 29597 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -529,244 +533,244 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
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-system.cpu.idleCycles 22479 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached
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+system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 3.732959 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.732959 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.267884 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.267884 # IPC: Total IPC of All Threads
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+system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 569 # number of misc regfile writes
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system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -843,110 +847,110 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
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system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
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system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
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system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
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system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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-system.membus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 489 # Request fanout histogram
-system.membus.reqLayer0.occupancy 593500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 511 # Request fanout histogram
+system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2584750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 9.6 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 9.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index 3f212d6b7..4869afcc8 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -150,6 +152,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 0ac73aa5b..0632f29e9 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -180,7 +180,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -215,6 +214,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -280,6 +280,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
index 7b696dc10..bc179e2e1 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
index 2d8c24695..d03b53466 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
index 81f94afc6..efaf99014 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -320,6 +322,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
index bfdad65c3..c95223039 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -96,7 +98,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -173,7 +174,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -318,6 +318,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@@ -343,7 +344,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -454,6 +454,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
index 59bad1d00..6a950e658 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
index 9caeea038..624933f37 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
index 9e3e089f3..ad7fd8fe2 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -221,6 +223,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
index 4591e667c..b339bd7f3 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -94,7 +96,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -136,7 +137,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -219,6 +219,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@@ -244,7 +245,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -355,6 +355,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
index 70896c96b..8ec6092a8 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -253,6 +255,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
index 6b137db47..84612ddd1 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -100,7 +102,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -151,7 +152,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -251,6 +251,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@@ -276,7 +277,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -387,6 +387,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 0496a5daf..1c0f40c55 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -251,6 +253,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index ef1559159..144fe8415 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -90,7 +92,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -168,7 +169,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -281,7 +281,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -316,6 +315,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -381,6 +381,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 6630f8e67..c428f015f 100644
--- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -150,6 +152,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index b68d2ad5d..a935118c3 100644
--- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -184,6 +186,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index f3f0e1367..f3b0d748d 100644
--- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -151,6 +153,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index eb5e74a48..485cbfda8 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu0.dcache]
type=Cache
@@ -674,11 +683,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu1.dcache]
type=Cache
@@ -1180,11 +1196,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu2.dcache]
type=Cache
@@ -1686,11 +1709,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu3.dcache]
type=Cache
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index ff2e64cda..8aa92b057 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -92,7 +94,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -134,7 +135,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -248,7 +248,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -290,7 +289,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -381,7 +379,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -423,7 +420,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -514,7 +510,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -556,7 +551,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -626,7 +620,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -660,6 +653,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -689,6 +683,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 02edfa409..b3a457f47 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -240,7 +240,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -282,7 +281,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -369,7 +367,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -411,7 +408,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -498,7 +494,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -540,7 +535,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -610,7 +604,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -644,6 +637,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -673,6 +667,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
index 3223dc0b2..3e8c739dd 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
index 36b87373b..53b6a0871 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
system.cpu1: completed 10000 read, 5477 write accesses @993312
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index 903deb35a..b7d5ab13e 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
index 486672848..130856dd7 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
system.cpu0: completed 10000 read, 5508 write accesses @738866
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index e15bb00e9..36bf64ec9 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index 6827eb233..8dbcafe0c 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
system.cpu6: completed 10000 read, 5414 write accesses @600125
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 2292d0c6a..8891a5a9d 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index bf89e6e1d..a7e51e9a1 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
system.cpu6: completed 10000 read, 5442 write accesses @464151
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 8fe2e9afa..fa59e7b5f 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index 3fba81e2d..e4093d449 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
system.cpu0: completed 10000 read, 5571 write accesses @752421
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
index aa83b8fc1..8d136d962 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -72,7 +74,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -126,7 +127,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -180,7 +180,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -234,7 +233,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -288,7 +286,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -342,7 +339,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -396,7 +392,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -450,7 +445,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -503,7 +497,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -538,6 +531,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
@@ -574,6 +568,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 144cd4765..10563829b 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -72,7 +74,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -126,7 +127,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -180,7 +180,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -234,7 +233,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -288,7 +286,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -342,7 +339,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -396,7 +392,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -450,7 +445,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -503,7 +497,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -537,6 +530,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -566,6 +560,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 333ab1c3b..c720d6208 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -151,6 +153,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 936d3f6e3..5de9bc371 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -181,7 +181,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -216,6 +215,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -281,6 +281,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 66af6c729..7e0b9adf7 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index e8b410808..c84baeb43 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 20fc06e75..61556605d 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 9da4061be..f020fab37 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
index 06da5f023..5ac78b2ee 100644
--- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
+++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
index 13060c953..74f33c417 100755
--- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
+++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
@@ -6,5 +6,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
index f9b74217d..6f23123b5 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
index cee0dfc57..c2086c0ba 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
@@ -4,5 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index a9fdb6e67..41e35786f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
index cee0dfc57..c2086c0ba 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
@@ -4,5 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 47885b3ee..0143ed036 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
index cee0dfc57..c2086c0ba 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
@@ -4,5 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index 39a3b4a9b..d7e72749d 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
index cee0dfc57..c2086c0ba 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
@@ -4,5 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 736270382..ffe5cd6c7 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
index cee0dfc57..c2086c0ba 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
@@ -4,5 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
index 7ca6b51f7..07db75ab6 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
index 08be6a107..98d363051 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -127,6 +129,7 @@ manager=system.monitor
probe_name=PktRequest
trace_compress=true
trace_file=monitor.ptrc.gz
+with_pc=false
[system.physmem]
type=SimpleMemory
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 831912ec7..60c231209 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -151,6 +153,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 1e2092c81..65b4d26d0 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -181,7 +181,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -216,6 +215,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -281,6 +281,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index a38cc9763..291d88b45 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -251,6 +253,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index f94d22eff..ca7f3c7de 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -90,7 +92,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -168,7 +169,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -281,7 +281,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -316,6 +315,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -381,6 +381,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 4e8cfbb92..141a140d3 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -150,6 +152,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 250899e0a..86ee03838 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -180,7 +180,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -215,6 +214,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -280,6 +280,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index ce2e451b7..51d8f4004 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -184,6 +186,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 3014dab83..03ef1ba17 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -94,7 +96,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@@ -146,7 +147,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@@ -214,7 +214,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@@ -249,6 +248,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -314,6 +314,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4