diff options
| -rw-r--r-- | src/arch/riscv/isa/formats/compressed.isa | 5 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/standard.isa | 34 |
2 files changed, 38 insertions, 1 deletions
diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa index 9c812e886..62d5b7567 100644 --- a/src/arch/riscv/isa/formats/compressed.isa +++ b/src/arch/riscv/isa/formats/compressed.isa @@ -54,7 +54,10 @@ def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{ header_output = ImmDeclare.subst(iop) decoder_output = ImmConstructor.subst(iop) decode_block = BasicDecode.subst(iop) - exec_output = ImmExecute.subst(iop) + if (name == "c_lui"): + exec_output = CILuiExecute.subst(iop) + else: + exec_output = ImmExecute.subst(iop) }}; def format CJOp(code, *opt_flags) {{ diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index a689c5750..2ffa2de88 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -90,6 +90,40 @@ def template ImmExecute {{ } }}; +def template CILuiExecute {{ + Fault + %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + if (fault == NoFault) { + %(code)s; + if (fault == NoFault) { + %(op_wb)s; + } + } + return fault; + } + + std::string + %(class_name)s::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::vector<RegId> indices = {%(regs)s}; + std::stringstream ss; + ss << mnemonic << ' '; + for (const RegId& idx: indices) + ss << registerName(idx) << ", "; + // To be compliant with GCC, the immediate is formated to a 20-bit + // signed integer. + ss << ((((uint64_t)imm) >> 12) & 0xFFFFF); + return ss.str(); + } +}}; + def template FenceExecute {{ Fault %(class_name)s::execute( |