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-rw-r--r--src/arch/riscv/isa/decoder.isa4
-rw-r--r--src/arch/riscv/isa/formats/standard.isa2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 8fcfba6ca..78cb78ce6 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -443,7 +443,7 @@ decode QUADRANT default Unknown::unknown() {
}
0x05: UOp::auipc({{
- Rd = PC + imm;
+ Rd = PC + (sext<20>(imm) << 12);
}});
0x06: decode FUNCT3 {
@@ -787,7 +787,7 @@ decode QUADRANT default Unknown::unknown() {
}
0x0d: UOp::lui({{
- Rd = (uint64_t)imm;
+ Rd = (uint64_t)(sext<20>(imm) << 12);
}});
0x0e: decode FUNCT3 {
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 15d268112..3c71fc8fb 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -341,7 +341,7 @@ def format Jump(code, *opt_flags) {{
def format UOp(code, *opt_flags) {{
regs = ['_destRegIdx[0]']
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
- {'code': code, 'imm_code': 'imm = sext<20>(IMM20) << 12;',
+ {'code': code, 'imm_code': 'imm = IMM20;',
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)