diff options
| -rw-r--r-- | src/arch/arm/miscregs.cc | 2 | ||||
| -rw-r--r-- | src/dev/arm/gic_v3_cpu_interface.cc | 4 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 81bc3efae..bffb4446a 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4646,7 +4646,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_IGRPEN0); InitReg(MISCREG_ICC_IGRPEN1_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_IGRPEN1); InitReg(MISCREG_ICC_IGRPEN1_EL1_NS) .bankedChild() diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index 0d444f165..b793f7c28 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -191,6 +191,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg) return readMiscReg(MISCREG_ICV_IGRPEN1_EL1); } + value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1); break; } @@ -1358,7 +1359,8 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) icc_igrpen1_el3); } - break; + setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val); + return; } // Virtual Interrupt Group 1 Enable register |