diff options
| -rw-r--r-- | src/arch/arm/insts/misc64.cc | 13 | ||||
| -rw-r--r-- | src/arch/arm/utility.cc | 12 |
2 files changed, 23 insertions, 2 deletions
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index c219bd9ad..fed2d9ac8 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013,2017-2018 ARM Limited + * Copyright (c) 2011-2013,2017-2019 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -38,6 +38,7 @@ */ #include "arch/arm/insts/misc64.hh" +#include "arch/arm/isa.hh" std::string ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const @@ -268,6 +269,16 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, break; case MISCREG_IMPDEF_UNIMPL: trap_to_hyp = hcr.tidcp && el == EL1; + // GICv3 regs + case MISCREG_ICC_SGI0R_EL1: + if (tc->getIsaPtr()->haveGICv3CpuIfc()) + trap_to_hyp = hcr.fmo && el == EL1; + break; + case MISCREG_ICC_SGI1R_EL1: + case MISCREG_ICC_ASGI1R_EL1: + if (tc->getIsaPtr()->haveGICv3CpuIfc()) + trap_to_hyp = hcr.imo && el == EL1; + break; default: break; } diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index b41134f03..2888ebbf3 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2014, 2016-2018 ARM Limited + * Copyright (c) 2009-2014, 2016-2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -580,6 +580,16 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss) case MISCREG_PMCR: trapToHype = hdcr.tpmcr; break; + // GICv3 regs + case MISCREG_ICC_SGI0R: + if (tc->getIsaPtr()->haveGICv3CpuIfc()) + trapToHype = hcr.fmo; + break; + case MISCREG_ICC_SGI1R: + case MISCREG_ICC_ASGI1R: + if (tc->getIsaPtr()->haveGICv3CpuIfc()) + trapToHype = hcr.imo; + break; // No default action needed default: break; |