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-rw-r--r--src/dev/arm/SMMUv3.py6
-rw-r--r--src/dev/arm/smmu_v3.cc6
-rw-r--r--src/dev/arm/smmu_v3.hh4
-rw-r--r--src/dev/arm/smmu_v3_slaveifc.cc4
-rw-r--r--src/dev/arm/smmu_v3_slaveifc.hh4
-rw-r--r--src/learning_gem5/part2/SimpleCache.py4
-rw-r--r--src/learning_gem5/part2/SimpleMemobj.py4
-rw-r--r--src/learning_gem5/part2/simple_cache.cc6
-rw-r--r--src/learning_gem5/part2/simple_cache.hh6
-rw-r--r--src/learning_gem5/part2/simple_memobj.cc4
-rw-r--r--src/learning_gem5/part2/simple_memobj.hh5
11 files changed, 28 insertions, 25 deletions
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 0126c2b49..72540f5cf 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -40,9 +40,9 @@ from m5.params import *
from m5.proxy import *
from m5.util.fdthelper import *
from m5.SimObject import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class SMMUv3SlaveInterface(MemObject):
+class SMMUv3SlaveInterface(ClockedObject):
type = 'SMMUv3SlaveInterface'
cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'
@@ -73,7 +73,7 @@ class SMMUv3SlaveInterface(MemObject):
prefetch_reserve_last_way = Param.Bool(True,
'Reserve last way of the main TLB for prefetched entries')
-class SMMUv3(MemObject):
+class SMMUv3(ClockedObject):
type = 'SMMUv3'
cxx_header = 'dev/arm/smmu_v3.hh'
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index e278c0e25..f6c5f90df 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -54,7 +54,7 @@
#include "sim/system.hh"
SMMUv3::SMMUv3(SMMUv3Params *params) :
- MemObject(params),
+ ClockedObject(params),
system(*params->system),
masterId(params->system->getMasterId(this)),
masterPort(name() + ".master", *this),
@@ -739,7 +739,7 @@ SMMUv3::init()
void
SMMUv3::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
using namespace Stats;
@@ -824,7 +824,7 @@ SMMUv3::getPort(const std::string &name, PortID id)
} else if (name == "control") {
return controlPort;
} else {
- return MemObject::getPort(name, id);
+ return ClockedObject::getPort(name, id);
}
}
diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index f02ef2f77..e0768298d 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -55,9 +55,9 @@
#include "dev/arm/smmu_v3_proc.hh"
#include "dev/arm/smmu_v3_ptops.hh"
#include "dev/arm/smmu_v3_slaveifc.hh"
-#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "params/SMMUv3.hh"
+#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
/**
@@ -80,7 +80,7 @@
*/
class SMMUTranslationProcess;
-class SMMUv3 : public MemObject
+class SMMUv3 : public ClockedObject
{
protected:
diff --git a/src/dev/arm/smmu_v3_slaveifc.cc b/src/dev/arm/smmu_v3_slaveifc.cc
index 0ed6c4d48..3f92023d7 100644
--- a/src/dev/arm/smmu_v3_slaveifc.cc
+++ b/src/dev/arm/smmu_v3_slaveifc.cc
@@ -46,7 +46,7 @@
SMMUv3SlaveInterface::SMMUv3SlaveInterface(
const SMMUv3SlaveInterfaceParams *p) :
- MemObject(p),
+ ClockedObject(p),
smmu(nullptr),
microTLB(new SMMUTLB(p->utlb_entries,
p->utlb_assoc,
@@ -99,7 +99,7 @@ SMMUv3SlaveInterface::getPort(const std::string &name, PortID id)
} else if (name == "ats_slave") {
return atsSlavePort;
} else {
- return MemObject::getPort(name, id);
+ return ClockedObject::getPort(name, id);
}
}
diff --git a/src/dev/arm/smmu_v3_slaveifc.hh b/src/dev/arm/smmu_v3_slaveifc.hh
index 3e03ae49a..7838e4ad0 100644
--- a/src/dev/arm/smmu_v3_slaveifc.hh
+++ b/src/dev/arm/smmu_v3_slaveifc.hh
@@ -47,14 +47,14 @@
#include "dev/arm/smmu_v3_events.hh"
#include "dev/arm/smmu_v3_ports.hh"
#include "dev/arm/smmu_v3_proc.hh"
-#include "mem/mem_object.hh"
#include "params/SMMUv3SlaveInterface.hh"
+#include "sim/clocked_object.hh"
class SMMUTranslationProcess;
class SMMUv3;
class SMMUSlavePort;
-class SMMUv3SlaveInterface : public MemObject
+class SMMUv3SlaveInterface : public ClockedObject
{
protected:
friend class SMMUTranslationProcess;
diff --git a/src/learning_gem5/part2/SimpleCache.py b/src/learning_gem5/part2/SimpleCache.py
index d0ad261d8..7a02630d2 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -29,9 +29,9 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class SimpleCache(MemObject):
+class SimpleCache(ClockedObject):
type = 'SimpleCache'
cxx_header = "learning_gem5/part2/simple_cache.hh"
diff --git a/src/learning_gem5/part2/SimpleMemobj.py b/src/learning_gem5/part2/SimpleMemobj.py
index e1fb95e22..37694689d 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -28,9 +28,9 @@
# Authors: Jason Lowe-Power
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
-class SimpleMemobj(MemObject):
+class SimpleMemobj(SimObject):
type = 'SimpleMemobj'
cxx_header = "learning_gem5/part2/simple_memobj.hh"
diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc
index 6deefde53..f6a5f4c9b 100644
--- a/src/learning_gem5/part2/simple_cache.cc
+++ b/src/learning_gem5/part2/simple_cache.cc
@@ -35,7 +35,7 @@
#include "sim/system.hh"
SimpleCache::SimpleCache(SimpleCacheParams *params) :
- MemObject(params),
+ ClockedObject(params),
latency(params->latency),
blockSize(params->system->cacheLineSize()),
capacity(params->size / blockSize),
@@ -64,7 +64,7 @@ SimpleCache::getPort(const std::string &if_name, PortID idx)
return cpuPorts[idx];
} else {
// pass it along to our super class
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
}
@@ -427,7 +427,7 @@ void
SimpleCache::regStats()
{
// If you don't do this you get errors about uninitialized stats.
- MemObject::regStats();
+ ClockedObject::regStats();
hits.name(name() + ".hits")
.desc("Number of hits")
diff --git a/src/learning_gem5/part2/simple_cache.hh b/src/learning_gem5/part2/simple_cache.hh
index 56859eb77..173aa0fbb 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -33,8 +33,10 @@
#include <unordered_map>
-#include "mem/mem_object.hh"
+#include "base/statistics.hh"
+#include "mem/port.hh"
#include "params/SimpleCache.hh"
+#include "sim/clocked_object.hh"
/**
* A very simple cache object. Has a fully-associative data store with random
@@ -43,7 +45,7 @@
* be outstanding at a time.
* This cache is a writeback cache.
*/
-class SimpleCache : public MemObject
+class SimpleCache : public ClockedObject
{
private:
diff --git a/src/learning_gem5/part2/simple_memobj.cc b/src/learning_gem5/part2/simple_memobj.cc
index c9af3461f..91110786f 100644
--- a/src/learning_gem5/part2/simple_memobj.cc
+++ b/src/learning_gem5/part2/simple_memobj.cc
@@ -33,7 +33,7 @@
#include "debug/SimpleMemobj.hh"
SimpleMemobj::SimpleMemobj(SimpleMemobjParams *params) :
- MemObject(params),
+ SimObject(params),
instPort(params->name + ".inst_port", this),
dataPort(params->name + ".data_port", this),
memPort(params->name + ".mem_side", this),
@@ -55,7 +55,7 @@ SimpleMemobj::getPort(const std::string &if_name, PortID idx)
return dataPort;
} else {
// pass it along to our super class
- return MemObject::getPort(if_name, idx);
+ return SimObject::getPort(if_name, idx);
}
}
diff --git a/src/learning_gem5/part2/simple_memobj.hh b/src/learning_gem5/part2/simple_memobj.hh
index 7a9b44764..c08f98e93 100644
--- a/src/learning_gem5/part2/simple_memobj.hh
+++ b/src/learning_gem5/part2/simple_memobj.hh
@@ -31,8 +31,9 @@
#ifndef __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
#define __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/SimpleMemobj.hh"
+#include "sim/sim_object.hh"
/**
* A very simple memory object. Current implementation doesn't even cache
@@ -40,7 +41,7 @@
* This memobj is fully blocking (not non-blocking). Only a single request can
* be outstanding at a time.
*/
-class SimpleMemobj : public MemObject
+class SimpleMemobj : public SimObject
{
private:
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-07 21:12:26 +0000