diff options
| -rw-r--r-- | src/arch/x86/X86LocalApic.py | 13 | ||||
| -rw-r--r-- | src/cpu/BaseCPU.py | 8 |
2 files changed, 14 insertions, 7 deletions
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py index 5d4910e98..c1b835ccb 100644 --- a/src/arch/x86/X86LocalApic.py +++ b/src/arch/x86/X86LocalApic.py @@ -43,6 +43,7 @@ from m5.params import * from m5.proxy import * from m5.objects.Device import BasicPioDevice +from m5.objects.ClockDomain import DerivedClockDomain class X86LocalApic(BasicPioDevice): type = 'X86LocalApic' @@ -52,3 +53,15 @@ class X86LocalApic(BasicPioDevice): int_slave = SlavePort("Port for receiving interrupt messages") int_latency = Param.Latency('1ns', \ "Latency for an interrupt to propagate through this device.") + + # pio_addr isn't used by the local APIC model since it's address is + # calculated dynamically using the initial ID of the CPU it's attached to, + # but it needs to be set to something to make the BasicPioDevice happy. + pio_addr = 0x2000000000000000 + + # The clock rate for the local APIC timer is supposed to be the "bus clock" + # which we assume is 1/16th the rate of the CPU clock. I don't think this + # is a hard rule, but seems to be true in practice. This can be overriden + # in configs that use it. + clk_domain = DerivedClockDomain( + clk_domain=Parent.clk_domain, clk_divider=16) diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6dd460cbe..2486c2e67 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -245,13 +245,7 @@ class BaseCPU(ClockedObject): elif buildEnv['TARGET_ISA'] == 'alpha': self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'x86': - self.apic_clk_domain = DerivedClockDomain(clk_domain = - Parent.clk_domain, - clk_divider = 16) - self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, - pio_addr=0x2000000000000000) - for i in range(self.numThreads)] - _localApic = self.interrupts + self.interrupts = [X86LocalApic() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'mips': self.interrupts = [MipsInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'arm': |