diff options
| -rw-r--r-- | src/arch/arm/isa.cc | 14 | ||||
| -rw-r--r-- | src/arch/arm/isa.hh | 3 |
2 files changed, 15 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 767fd9f6a..101ca5420 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2019 ARM Limited + * Copyright (c) 2010-2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -2190,6 +2190,18 @@ ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) } } +ISA::MiscRegLUTEntryInitializer::chain +ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const +{ + switch (FullSystem ? sys->highestEL() : EL1) { + case EL0: + case EL1: priv(); break; + case EL2: hyp(); break; + case EL3: mon(); break; + } + return *this; +} + } // namespace ArmISA ArmISA::ISA * diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index fea372ed4..7ffa682ef 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2019 ARM Limited + * Copyright (c) 2010, 2012-2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -357,6 +357,7 @@ namespace ArmISA user(0); return *this; } + chain highest(ArmSystem *const sys) const; MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e, std::bitset<NUM_MISCREG_INFOS> &i) : entry(e), |