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-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini9
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json11
-rwxr-xr-xtests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout6
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt52
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini17
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json21
-rwxr-xr-xtests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout8
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt436
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini28
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json82
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr5
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout6
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt850
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini28
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json82
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr6
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout8
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt2074
18 files changed, 1917 insertions, 1812 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index c34b731c8..91582aaaf 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -110,6 +111,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -135,11 +137,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
index 27bdb34a5..559630530 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
@@ -3,6 +3,7 @@
"sim_quantum": 0,
"system": {
"kernel": "",
+ "mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"slave": {
@@ -15,10 +16,10 @@
},
"name": "membus",
"snoop_filter": null,
+ "forward_latency": 4,
"clk_domain": "system.clk_domain",
- "header_cycles": 1,
"system": "system",
- "width": 8,
+ "width": 16,
"eventq_index": 0,
"master": {
"peer": [
@@ -26,10 +27,13 @@
],
"role": "MASTER"
},
+ "response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
+ "snoop_response_latency": 4,
"type": "CoherentXBar",
- "use_default_range": false
+ "use_default_range": false,
+ "frontend_latency": 3
},
"symbolfile": "",
"readfile": "",
@@ -177,6 +181,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
index 1ae1ea322..d5f5ca1c8 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2014 15:53:23
-gem5 started Sep 21 2014 16:10:49
-gem5 executing on zizzer
+gem5 compiled Mar 7 2015 13:46:57
+gem5 started Mar 7 2015 13:47:23
+gem5 executing on zizzer2
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 4e61c814d..3003773af 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2577407 # Simulator instruction rate (inst/s)
-host_op_rate 2577191 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1288569274 # Simulator tick rate (ticks/s)
-host_mem_usage 218888 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 1781493 # Simulator instruction rate (inst/s)
+host_op_rate 1781360 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 890669168 # Simulator tick rate (ticks/s)
+host_mem_usage 214316 # Number of bytes of host memory used
+host_seconds 0.28 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -35,27 +35,6 @@ system.physmem.bw_write::total 1670144451 # Wr
system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 624454 # Transaction distribution
-system.membus.trans_dist::ReadResp 624454 # Transaction distribution
-system.membus.trans_dist::WriteReq 56340 # Transaction distribution
-system.membus.trans_dist::WriteResp 56340 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 680794 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram
-system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 680794 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -148,5 +127,26 @@ system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction
+system.membus.trans_dist::ReadReq 624454 # Transaction distribution
+system.membus.trans_dist::ReadResp 624454 # Transaction distribution
+system.membus.trans_dist::WriteReq 56340 # Transaction distribution
+system.membus.trans_dist::WriteResp 56340 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 680794 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram
+system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 680794 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index f153b1e92..eeb68edec 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -82,6 +83,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -122,6 +124,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -171,6 +174,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -204,8 +208,11 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
@@ -223,6 +230,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -248,11 +256,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
index c9ad58d39..787ac7aeb 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
@@ -3,6 +3,7 @@
"sim_quantum": 0,
"system": {
"kernel": "",
+ "mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"slave": {
@@ -14,10 +15,10 @@
},
"name": "membus",
"snoop_filter": null,
+ "forward_latency": 4,
"clk_domain": "system.clk_domain",
- "header_cycles": 1,
"system": "system",
- "width": 8,
+ "width": 16,
"eventq_index": 0,
"master": {
"peer": [
@@ -25,10 +26,13 @@
],
"role": "MASTER"
},
+ "response_latency": 2,
"cxx_class": "CoherentXBar",
"path": "system.membus",
+ "snoop_response_latency": 4,
"type": "CoherentXBar",
- "use_default_range": false
+ "use_default_range": false,
+ "frontend_latency": 3
},
"symbolfile": "",
"readfile": "",
@@ -154,8 +158,8 @@
},
"name": "toL2Bus",
"snoop_filter": null,
+ "forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
- "header_cycles": 1,
"system": "system",
"width": 32,
"eventq_index": 0,
@@ -165,10 +169,13 @@
],
"role": "MASTER"
},
+ "response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.cpu.toL2Bus",
+ "snoop_response_latency": 1,
"type": "CoherentXBar",
- "use_default_range": false
+ "use_default_range": false,
+ "frontend_latency": 1
},
"do_quiesce": true,
"type": "TimingSimpleCPU",
@@ -208,6 +215,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -268,6 +276,7 @@
"mshrs": 20,
"forward_snoops": true,
"hit_latency": 20,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
@@ -293,6 +302,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -348,6 +358,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
index ad496f406..62a14a3d5 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2014 15:53:23
-gem5 started Sep 21 2014 16:10:49
-gem5 executing on zizzer
+gem5 compiled Mar 7 2015 13:46:57
+gem5 started Mar 7 2015 13:47:12
+gem5 executing on zizzer2
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
->Exiting @ tick 727072000 because a thread reached the max instruction count
+>Exiting @ tick 727072500 because a thread reached the max instruction count
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index a2648216d..7d45c36b9 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000727 # Number of seconds simulated
-sim_ticks 727072000 # Number of ticks simulated
-final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 727072500 # Number of ticks simulated
+final_tick 727072500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1546280 # Simulator instruction rate (inst/s)
-host_op_rate 1546201 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2248282899 # Simulator tick rate (ticks/s)
-host_mem_usage 227720 # Number of bytes of host memory used
-host_seconds 0.32 # Real time elapsed on the host
+host_inst_rate 639322 # Simulator instruction rate (inst/s)
+host_op_rate 639300 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 929601467 # Simulator tick rate (ticks/s)
+host_mem_usage 223596 # Number of bytes of host memory used
+host_seconds 0.78 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 25792 # Nu
system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 35473791 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 39963030 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 75436821 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 35473791 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 35473791 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 35473791 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 39963030 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 75436821 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 718 # Transaction distribution
-system.membus.trans_dist::ReadResp 718 # Transaction distribution
-system.membus.trans_dist::ReadExReq 139 # Transaction distribution
-system.membus.trans_dist::ReadExResp 139 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 857 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 857 # Request fanout histogram
-system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 7713000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
+system.physmem.bw_read::cpu.inst 35473766 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 39963002 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 75436769 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 35473766 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 35473766 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 35473766 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 39963002 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 75436769 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 1454144 # number of cpu cycles simulated
+system.cpu.numCycles 1454145 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
@@ -105,7 +82,7 @@ system.cpu.num_mem_refs 180793 # nu
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1454144 # Number of busy cycles
+system.cpu.num_busy_cycles 1454145 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 59023 # Number of branches fetched
@@ -144,13 +121,118 @@ system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 500019 # Class of executed instruction
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 287.258890 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 287.258890 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
+system.cpu.dcache.overall_hits::total 180321 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
+system.cpu.dcache.overall_misses::total 454 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16852500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 16852500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7436500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24289000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 24289000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24289000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 24289000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 265.012564 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 265.012564 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id
@@ -170,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 403 # n
system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.icache.overall_misses::total 403 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 22165000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 22165000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 22165000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 22165000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 22165000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 22165000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 22165500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 22165500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 22165500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 22165500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 22165500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 22165500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
@@ -188,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000806
system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55001.240695 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55001.240695 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55001.240695 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55001.240695 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55001.240695 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55001.240695 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -208,33 +290,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 403
system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21359000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 21359000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21359000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 21359000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21359000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 21359000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21561000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 21561000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21561000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 21561000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21561000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 21561000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53501.240695 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53501.240695 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 481.541188 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019216 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 216.521972 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy
@@ -256,17 +338,17 @@ system.cpu.l2cache.demand_misses::total 857 # nu
system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
system.cpu.l2cache.overall_misses::total 857 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20956000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16380000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 37336000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7228000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 7228000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 20956000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 23608000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 44564000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 20956000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 23608000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 44564000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21158000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16537500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 37695500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7297500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 7297500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 21158000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 23835000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 44993000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 21158000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 23835000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 44993000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 315 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses)
@@ -289,17 +371,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.240695 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.696379 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.240695 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52500.583431 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.240695 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52500.583431 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -319,17 +401,17 @@ system.cpu.l2cache.demand_mshr_misses::total 857
system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16120000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12600000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5560000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5560000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16120000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 34280000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16120000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 34280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16321500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12757500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 29079000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5629500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5629500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16321500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18387000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 34708500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16321500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18387000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 34708500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
@@ -341,123 +423,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
-system.cpu.dcache.overall_hits::total 180321 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
-system.cpu.dcache.overall_misses::total 454 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
@@ -486,5 +463,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 604500 # La
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 718 # Transaction distribution
+system.membus.trans_dist::ReadResp 718 # Transaction distribution
+system.membus.trans_dist::ReadExReq 139 # Transaction distribution
+system.membus.trans_dist::ReadExResp 139 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 857 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 857 # Request fanout histogram
+system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4285500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 3cbe4882e..8ea14a565 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -23,6 +23,7 @@ load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -86,6 +87,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -126,6 +128,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -180,6 +183,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -228,6 +232,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -268,6 +273,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -322,6 +328,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -370,6 +377,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -410,6 +418,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -464,6 +473,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -512,6 +522,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -552,6 +563,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -606,6 +618,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -633,6 +646,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -666,11 +680,14 @@ size=4194304
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.l2c.mem_side
@@ -691,11 +708,14 @@ port=system.membus.master[0]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json
index 19d6c1397..274fffd10 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json
@@ -3,6 +3,38 @@
"sim_quantum": 0,
"system": {
"kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.l2c.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "membus",
+ "snoop_filter": null,
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
+ "width": 16,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "type": "CoherentXBar",
+ "use_default_range": false,
+ "frontend_latency": 3
+ },
+ "symbolfile": "",
"l2c": {
"is_top_level": false,
"prefetcher": null,
@@ -34,6 +66,7 @@
"mshrs": 20,
"forward_snoops": true,
"hit_latency": 20,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
@@ -50,34 +83,6 @@
},
"two_queue": false
},
- "kernel_addr_check": true,
- "membus": {
- "slave": {
- "peer": [
- "system.system_port",
- "system.l2c.mem_side"
- ],
- "role": "SLAVE"
- },
- "name": "membus",
- "snoop_filter": null,
- "clk_domain": "system.clk_domain",
- "header_cycles": 1,
- "system": "system",
- "width": 8,
- "eventq_index": 0,
- "master": {
- "peer": [
- "system.physmem.port"
- ],
- "role": "MASTER"
- },
- "cxx_class": "CoherentXBar",
- "path": "system.membus",
- "type": "CoherentXBar",
- "use_default_range": false
- },
- "symbolfile": "",
"readfile": "",
"cxx_class": "System",
"load_offset": 0,
@@ -177,10 +182,10 @@
},
"name": "toL2Bus",
"snoop_filter": null,
+ "forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
- "header_cycles": 1,
"system": "system",
- "width": 8,
+ "width": 32,
"eventq_index": 0,
"master": {
"peer": [
@@ -188,10 +193,13 @@
],
"role": "MASTER"
},
+ "response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.toL2Bus",
+ "snoop_response_latency": 1,
"type": "CoherentXBar",
- "use_default_range": false
+ "use_default_range": false,
+ "frontend_latency": 1
},
"mem_mode": "atomic",
"name": "system",
@@ -264,6 +272,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -302,6 +311,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -358,6 +368,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -454,6 +465,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -492,6 +504,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -548,6 +561,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -644,6 +658,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -682,6 +697,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -738,6 +754,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -834,6 +851,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -872,6 +890,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -928,6 +947,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index 193b4989f..8af5388f9 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -3,8 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 0ed1fc9c8..90692ccf8 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2014 15:53:23
-gem5 started Sep 21 2014 16:10:49
-gem5 executing on zizzer
+gem5 compiled Mar 7 2015 13:46:57
+gem5 started Mar 7 2015 13:47:23
+gem5 executing on zizzer2
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index ee7e01f12..7a94e3207 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2852799 # Simulator instruction rate (inst/s)
-host_op_rate 2852705 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 356601416 # Simulator tick rate (ticks/s)
-host_mem_usage 239540 # Number of bytes of host memory used
-host_seconds 0.70 # Real time elapsed on the host
+host_inst_rate 1548972 # Simulator instruction rate (inst/s)
+host_op_rate 1548948 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 193626740 # Simulator tick rate (ticks/s)
+host_mem_usage 235568 # Number of bytes of host memory used
+host_seconds 1.29 # Real time elapsed on the host
sim_insts 2000004 # Number of instructions simulated
sim_ops 2000004 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -59,235 +59,7 @@ system.physmem.bw_total::cpu2.data 116216795 # To
system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 2872 # Transaction distribution
-system.membus.trans_dist::ReadResp 2872 # Transaction distribution
-system.membus.trans_dist::ReadExReq 556 # Transaction distribution
-system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3428 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3428 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3428 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
-system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 34048 # Number of tag accesses
-system.l2c.tags.data_accesses 34048 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
-system.l2c.Writeback_hits::total 116 # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu0.data 9 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu1.data 9 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu2.data 9 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu3.data 9 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu0.data 454 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu1.data 454 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu2.data 454 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu3.data 454 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
@@ -379,54 +151,6 @@ system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 500019 # Class of executed instruction
-system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits
-system.cpu0.icache.overall_hits::total 499556 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
-system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 61 # number of replacements
system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@@ -486,6 +210,54 @@ system.cpu0.dcache.cache_copies 0 # nu
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu0.dcache.writebacks::total 29 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements 152 # number of replacements
+system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits
+system.cpu0.icache.overall_hits::total 499556 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
+system.cpu0.icache.overall_misses::total 463 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
@@ -577,54 +349,6 @@ system.cpu1.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 500019 # Class of executed instruction
-system.cpu1.icache.tags.replacements 152 # number of replacements
-system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 499556 # number of overall hits
-system.cpu1.icache.overall_hits::total 499556 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
-system.cpu1.icache.overall_misses::total 463 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 500019 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 61 # number of replacements
system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@@ -684,6 +408,54 @@ system.cpu1.dcache.cache_copies 0 # nu
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu1.dcache.writebacks::total 29 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements 152 # number of replacements
+system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses 500482 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 500482 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 499556 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 499556 # number of overall hits
+system.cpu1.icache.overall_hits::total 499556 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
+system.cpu1.icache.overall_misses::total 463 # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 500019 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 500019 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
@@ -775,54 +547,6 @@ system.cpu2.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::total 500019 # Class of executed instruction
-system.cpu2.icache.tags.replacements 152 # number of replacements
-system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu2.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 499556 # number of overall hits
-system.cpu2.icache.overall_hits::total 499556 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
-system.cpu2.icache.overall_misses::total 463 # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 500019 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes 0 # number of fast writes performed
-system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.tags.replacements 61 # number of replacements
system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@@ -882,6 +606,54 @@ system.cpu2.dcache.cache_copies 0 # nu
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu2.dcache.writebacks::total 29 # number of writebacks
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.icache.tags.replacements 152 # number of replacements
+system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses 500482 # Number of tag accesses
+system.cpu2.icache.tags.data_accesses 500482 # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total 499556 # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst 499556 # number of overall hits
+system.cpu2.icache.overall_hits::total 499556 # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
+system.cpu2.icache.overall_misses::total 463 # number of overall misses
+system.cpu2.icache.ReadReq_accesses::cpu2.inst 500019 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst 500019 # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes 0 # number of fast writes performed
+system.cpu2.icache.cache_copies 0 # number of cache copies performed
+system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.fetch_acv 0 # ITB acv
@@ -973,54 +745,6 @@ system.cpu3.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::total 500019 # Class of executed instruction
-system.cpu3.icache.tags.replacements 152 # number of replacements
-system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 499556 # number of overall hits
-system.cpu3.icache.overall_hits::total 499556 # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
-system.cpu3.icache.overall_misses::total 463 # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 500019 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements 61 # number of replacements
system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
@@ -1080,5 +804,281 @@ system.cpu3.dcache.cache_copies 0 # nu
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu3.dcache.writebacks::total 29 # number of writebacks
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.icache.tags.replacements 152 # number of replacements
+system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses 500482 # Number of tag accesses
+system.cpu3.icache.tags.data_accesses 500482 # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total 499556 # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst 499556 # number of overall hits
+system.cpu3.icache.overall_hits::total 499556 # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
+system.cpu3.icache.overall_misses::total 463 # number of overall misses
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 500019 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst 500019 # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes 0 # number of fast writes performed
+system.cpu3.icache.cache_copies 0 # number of cache copies performed
+system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.tags.replacements 0 # number of replacements
+system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
+system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 34048 # Number of tag accesses
+system.l2c.tags.data_accesses 34048 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
+system.l2c.Writeback_hits::total 116 # number of Writeback hits
+system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::total 276 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu0.data 9 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu1.data 9 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu2.data 9 # number of overall hits
+system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu3.data 9 # number of overall hits
+system.l2c.overall_hits::total 276 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
+system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu0.data 454 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu1.data 454 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu2.data 454 # number of overall misses
+system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu3.data 454 # number of overall misses
+system.l2c.overall_misses::total 3428 # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 2872 # Transaction distribution
+system.membus.trans_dist::ReadResp 2872 # Transaction distribution
+system.membus.trans_dist::ReadExReq 556 # Transaction distribution
+system.membus.trans_dist::ReadExResp 556 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3428 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3428 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 3428 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 0 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 0679aa6bf..098ebf393 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -82,6 +83,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -122,6 +124,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -176,6 +179,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -220,6 +224,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -260,6 +265,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -314,6 +320,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -358,6 +365,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -398,6 +406,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -452,6 +461,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -496,6 +506,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -536,6 +547,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -590,6 +602,7 @@ errout=cerr
eventq_index=0
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
+kvmInSE=false
max_stack_size=67108864
output=cout
system=system
@@ -617,6 +630,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -650,11 +664,14 @@ size=4194304
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.l2c.mem_side
@@ -675,11 +692,14 @@ port=system.membus.master[0]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json
index 0d2ee3731..26a85d3e0 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json
@@ -3,6 +3,38 @@
"sim_quantum": 0,
"system": {
"kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.l2c.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "membus",
+ "snoop_filter": null,
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
+ "width": 16,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "type": "CoherentXBar",
+ "use_default_range": false,
+ "frontend_latency": 3
+ },
+ "symbolfile": "",
"l2c": {
"is_top_level": false,
"prefetcher": null,
@@ -34,6 +66,7 @@
"mshrs": 20,
"forward_snoops": true,
"hit_latency": 20,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
@@ -50,34 +83,6 @@
},
"two_queue": false
},
- "kernel_addr_check": true,
- "membus": {
- "slave": {
- "peer": [
- "system.system_port",
- "system.l2c.mem_side"
- ],
- "role": "SLAVE"
- },
- "name": "membus",
- "snoop_filter": null,
- "clk_domain": "system.clk_domain",
- "header_cycles": 1,
- "system": "system",
- "width": 8,
- "eventq_index": 0,
- "master": {
- "peer": [
- "system.physmem.port"
- ],
- "role": "MASTER"
- },
- "cxx_class": "CoherentXBar",
- "path": "system.membus",
- "type": "CoherentXBar",
- "use_default_range": false
- },
- "symbolfile": "",
"readfile": "",
"cxx_class": "System",
"load_offset": 0,
@@ -177,10 +182,10 @@
},
"name": "toL2Bus",
"snoop_filter": null,
+ "forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
- "header_cycles": 1,
"system": "system",
- "width": 8,
+ "width": 32,
"eventq_index": 0,
"master": {
"peer": [
@@ -188,10 +193,13 @@
],
"role": "MASTER"
},
+ "response_latency": 1,
"cxx_class": "CoherentXBar",
"path": "system.toL2Bus",
+ "snoop_response_latency": 1,
"type": "CoherentXBar",
- "use_default_range": false
+ "use_default_range": false,
+ "frontend_latency": 1
},
"mem_mode": "timing",
"name": "system",
@@ -261,6 +269,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -299,6 +308,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -354,6 +364,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -447,6 +458,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -485,6 +497,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -540,6 +553,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -633,6 +647,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -671,6 +686,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -726,6 +742,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -819,6 +836,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
@@ -857,6 +875,7 @@
"output": "cout",
"chkpt": "",
"errout": "cerr",
+ "kvmInSE": false,
"system": "system",
"useArchPT": false,
"eventq_index": 0,
@@ -912,6 +931,7 @@
"mshrs": 4,
"forward_snoops": true,
"hit_latency": 2,
+ "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 12d988946..8be63e416 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -3,7 +3,5 @@ warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+stdout: Broken pipe
+stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index bb34829ad..aa09b6199 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2014 15:53:23
-gem5 started Sep 21 2014 16:10:49
-gem5 executing on zizzer
+gem5 compiled Mar 7 2015 13:46:57
+gem5 started Mar 7 2015 13:47:11
+gem5 executing on zizzer2
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -15,4 +15,4 @@ main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
->>>>Exiting @ tick 729024000 because a thread reached the max instruction count
+>>>>Exiting @ tick 727903500 because a thread reached the max instruction count
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 844307bd8..42278656d 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000729 # Number of seconds simulated
-sim_ticks 729024000 # Number of ticks simulated
-final_tick 729024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000728 # Number of seconds simulated
+sim_ticks 727903500 # Number of ticks simulated
+final_tick 727903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1431965 # Simulator instruction rate (inst/s)
-host_op_rate 1431947 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 521966515 # Simulator tick rate (ticks/s)
-host_mem_usage 239544 # Number of bytes of host memory used
-host_seconds 1.40 # Real time elapsed on the host
-sim_insts 1999959 # Number of instructions simulated
-sim_ops 1999959 # Number of ops (including micro ops) simulated
+host_inst_rate 639540 # Simulator instruction rate (inst/s)
+host_op_rate 639535 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 232760737 # Simulator tick rate (ticks/s)
+host_mem_usage 235576 # Number of bytes of host memory used
+host_seconds 3.13 # Real time elapsed on the host
+sim_insts 1999978 # Number of instructions simulated
+sim_ops 1999978 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
@@ -36,472 +36,30 @@ system.physmem.num_reads::cpu2.data 454 # Nu
system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 35378808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39856027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35378808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 39856027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 35378808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 39856027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 35378808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 39856027 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 300939338 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 35378808 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 141515231 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39856027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 39856027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 39856027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 35378808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 39856027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 300939338 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 2872 # Transaction distribution
-system.membus.trans_dist::ReadResp 2872 # Transaction distribution
-system.membus.trans_dist::ReadExReq 556 # Transaction distribution
-system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3431 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3431 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3431 # Request fanout histogram
-system.membus.reqLayer0.occupancy 4229968 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 31051500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 4.3 # Layer utilization (%)
+system.physmem.bw_read::cpu0.inst 35433268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 39917379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35433268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 39917379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 35433268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 39917379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 35433268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 39917379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 301402590 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 35433268 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35433268 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 35433268 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 35433268 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 141733073 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 35433268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 39917379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35433268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 39917379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 35433268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 39917379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 35433268 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 39917379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 301402590 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use
-system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2904 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 34048 # Number of tag accesses
-system.l2c.tags.data_accesses 34048 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
-system.l2c.Writeback_hits::total 116 # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu0.data 9 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu1.data 9 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu2.data 9 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu3.data 9 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu0.data 454 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu1.data 454 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu2.data 454 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu3.data 454 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 21101500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 21110000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 16409500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 21118500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 16409500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst 21129500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data 16412000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 150100000 # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 7252500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 7252500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 7252500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data 7252500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 29010000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 21101500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 23662000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 21110000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 23662000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 21118500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 23662000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst 21129500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data 23664500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 179110000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 21101500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 23662000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 21110000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 23662000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 21118500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 23662000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst 21129500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data 23664500 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 179110000 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52361.042184 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52093.650794 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52382.133995 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52093.650794 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52403.225806 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 52093.650794 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52430.521092 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.data 52101.587302 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52263.231198 # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52176.258993 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52176.258993 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52176.258993 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52176.258993 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52176.258993 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52361.042184 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52118.942731 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52382.133995 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52118.942731 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 52403.225806 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 52118.942731 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 52430.521092 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 52124.449339 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52249.124854 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52361.042184 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52118.942731 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52382.133995 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52118.942731 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 52403.225806 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 52118.942731 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 52430.521092 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 52124.449339 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52249.124854 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.ReadReq_mshr_misses::cpu0.inst 403 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 315 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 403 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 315 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 403 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 315 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst 403 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.data 315 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 2872 # number of ReadReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data 139 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 556 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 403 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 454 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 403 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 454 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 403 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 454 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst 403 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data 454 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 3428 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 403 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 454 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 403 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 454 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 403 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 454 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 16120000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12600000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 16274000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12629500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 16282500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 12629500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 16293500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.data 12632000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 115461000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5560000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5584500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5584500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5584500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 22313500 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 16120000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 18160000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 16274000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 18214000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 16282500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 18214000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst 16293500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data 18216500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 137774500 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 16120000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 18160000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 16274000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 18214000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 16282500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 18214000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst 16293500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data 18216500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 137774500 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.912325 # mshr miss rate for ReadReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40093.650794 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40093.650794 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40202.298050 # average ReadReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40176.258993 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40176.258993 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40176.258993 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40132.194245 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40382.133995 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40118.942731 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40403.225806 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40118.942731 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40430.521092 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40124.449339 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40190.927655 # average overall mshr miss latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2374000 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2083500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2083500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 2083500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 2083500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 2083500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 2083500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 2083500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 2083500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
@@ -535,7 +93,7 @@ system.cpu0.itb.data_misses 0 # DT
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.numCycles 1458048 # number of cpu cycles simulated
+system.cpu0.numCycles 1455807 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 500001 # Number of instructions committed
@@ -554,7 +112,7 @@ system.cpu0.num_mem_refs 180793 # nu
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_store_insts 56350 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 1458048 # Number of busy cycles
+system.cpu0.num_busy_cycles 1455807 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.Branches 59023 # Number of branches fetched
@@ -593,98 +151,15 @@ system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Cl
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 500019 # Class of executed instruction
-system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits
-system.cpu0.icache.overall_hits::total 499557 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
-system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23096000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 23096000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 23096000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 23096000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 23096000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 23096000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49883.369330 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 49883.369330 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49883.369330 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 49883.369330 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49883.369330 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 49883.369330 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22170000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 22170000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22170000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 22170000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22170000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 22170000 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47883.369330 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 61 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use
+system.cpu0.dcache.tags.tagsinuse 273.598283 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.598283 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534372 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.534372 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
@@ -708,14 +183,14 @@ system.cpu0.dcache.demand_misses::cpu0.data 463 #
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
system.cpu0.dcache.overall_misses::total 463 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17474500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7669500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 25144000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 25144000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17443000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7645000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 25088000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 25088000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
@@ -732,14 +207,14 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561
system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53933.641975 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55176.258993 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54306.695464 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54306.695464 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53836.419753 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55000 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54185.745140 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54185.745140 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -758,14 +233,14 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 463
system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16826500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7391500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24218000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24218000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16957000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7436500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24393500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24393500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -774,15 +249,98 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51933.641975 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53176.258993 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52306.695464 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52306.695464 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52336.419753 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53500 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52685.745140 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52685.745140 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements 152 # number of replacements
+system.cpu0.icache.tags.tagsinuse 216.437634 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.437634 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422730 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.422730 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits
+system.cpu0.icache.overall_hits::total 499557 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
+system.cpu0.icache.overall_misses::total 463 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 22947500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 22947500 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 22947500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 22947500 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 22947500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 22947500 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49562.634989 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 49562.634989 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49562.634989 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 49562.634989 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49562.634989 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 49562.634989 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22253000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 22253000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22253000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 22253000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22253000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 22253000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48062.634989 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 48062.634989 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48062.634989 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 48062.634989 # average overall mshr miss latency
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
@@ -799,10 +357,10 @@ system.cpu1.dtb.data_hits 180774 # DT
system.cpu1.dtb.data_misses 18 # DTB misses
system.cpu1.dtb.data_acv 0 # DTB access violations
system.cpu1.dtb.data_accesses 180792 # DTB accesses
-system.cpu1.itb.fetch_hits 500012 # ITB hits
+system.cpu1.itb.fetch_hits 500016 # ITB hits
system.cpu1.itb.fetch_misses 13 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 500025 # ITB accesses
+system.cpu1.itb.fetch_accesses 500029 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
@@ -816,31 +374,31 @@ system.cpu1.itb.data_misses 0 # DT
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu1.numCycles 1458048 # number of cpu cycles simulated
+system.cpu1.numCycles 1455807 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 499993 # Number of instructions committed
-system.cpu1.committedOps 499993 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 474681 # Number of integer alu accesses
+system.cpu1.committedInsts 499997 # Number of instructions committed
+system.cpu1.committedOps 499997 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 474685 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu1.num_func_calls 14357 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 474681 # number of integer instructions
+system.cpu1.num_int_insts 474685 # number of integer instructions
system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_int_register_reads 654273 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 371536 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 654279 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 371540 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu1.num_mem_refs 180792 # number of memory refs
system.cpu1.num_load_insts 124443 # Number of load instructions
system.cpu1.num_store_insts 56349 # Number of store instructions
system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_busy_cycles 1458048 # Number of busy cycles
+system.cpu1.num_busy_cycles 1455807 # Number of busy cycles
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0 # Percentage of idle cycles
system.cpu1.Branches 59022 # Number of branches fetched
system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu1.op_class::IntAlu 300381 60.07% 63.84% # Class of executed instruction
+system.cpu1.op_class::IntAlu 300385 60.08% 63.84% # Class of executed instruction
system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
@@ -873,99 +431,16 @@ system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Cl
system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 500011 # Class of executed instruction
-system.cpu1.icache.tags.replacements 152 # number of replacements
-system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 500475 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 500475 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 499549 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 499549 # number of overall hits
-system.cpu1.icache.overall_hits::total 499549 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
-system.cpu1.icache.overall_misses::total 463 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23105000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 23105000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 23105000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 23105000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 23105000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 23105000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 500012 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 500012 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 500012 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 500012 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 500012 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 500012 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49902.807775 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 49902.807775 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49902.807775 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 49902.807775 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49902.807775 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 49902.807775 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22179000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22179000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22179000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47902.807775 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.op_class::total 500015 # Class of executed instruction
system.cpu1.dcache.tags.replacements 61 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use
+system.cpu1.dcache.tags.tagsinuse 273.595522 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.595522 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534366 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.534366 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
@@ -989,14 +464,14 @@ system.cpu1.dcache.demand_misses::cpu1.data 463 #
system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
system.cpu1.dcache.overall_misses::total 463 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17474500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7669500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 25144000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 25144000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17443000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7645000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 25088000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 25088000 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses)
@@ -1013,14 +488,14 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561
system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53933.641975 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55176.258993 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54306.695464 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54306.695464 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53836.419753 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55000 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54185.745140 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54185.745140 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1039,14 +514,14 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 463
system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16826500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7391500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24218000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24218000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16957000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7436500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24393500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24393500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -1055,35 +530,118 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561
system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51933.641975 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53176.258993 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52306.695464 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52306.695464 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 52336.419753 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53500 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52685.745140 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52685.745140 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements 152 # number of replacements
+system.cpu1.icache.tags.tagsinuse 216.435498 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 499553 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 1078.948164 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.435498 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422726 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.422726 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses 500479 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 500479 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 499553 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 499553 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 499553 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 499553 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 499553 # number of overall hits
+system.cpu1.icache.overall_hits::total 499553 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
+system.cpu1.icache.overall_misses::total 463 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 22952500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 22952500 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 22952500 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 22952500 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 22952500 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 22952500 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 500016 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 500016 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 500016 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 500016 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 500016 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 500016 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49573.434125 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 49573.434125 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49573.434125 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 49573.434125 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49573.434125 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 49573.434125 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22258000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 22258000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22258000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 22258000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22258000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 22258000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48073.434125 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 48073.434125 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48073.434125 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 48073.434125 # average overall mshr miss latency
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 124433 # DTB read hits
+system.cpu2.dtb.read_hits 124435 # DTB read hits
system.cpu2.dtb.read_misses 8 # DTB read misses
system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_accesses 124441 # DTB read accesses
+system.cpu2.dtb.read_accesses 124443 # DTB read accesses
system.cpu2.dtb.write_hits 56339 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
system.cpu2.dtb.write_acv 0 # DTB write access violations
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
-system.cpu2.dtb.data_hits 180772 # DTB hits
+system.cpu2.dtb.data_hits 180774 # DTB hits
system.cpu2.dtb.data_misses 18 # DTB misses
system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_accesses 180790 # DTB accesses
-system.cpu2.itb.fetch_hits 500005 # ITB hits
+system.cpu2.dtb.data_accesses 180792 # DTB accesses
+system.cpu2.itb.fetch_hits 500011 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_accesses 500018 # ITB accesses
+system.cpu2.itb.fetch_accesses 500024 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
@@ -1097,31 +655,31 @@ system.cpu2.itb.data_misses 0 # DT
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.workload.num_syscalls 18 # Number of system calls
-system.cpu2.numCycles 1458048 # number of cpu cycles simulated
+system.cpu2.numCycles 1455807 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 499986 # Number of instructions committed
-system.cpu2.committedOps 499986 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 474674 # Number of integer alu accesses
+system.cpu2.committedInsts 499992 # Number of instructions committed
+system.cpu2.committedOps 499992 # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses 474680 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 474674 # number of integer instructions
+system.cpu2.num_int_insts 474680 # number of integer instructions
system.cpu2.num_fp_insts 32 # number of float instructions
-system.cpu2.num_int_register_reads 654263 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 371529 # number of times the integer registers were written
+system.cpu2.num_int_register_reads 654271 # number of times the integer registers were read
+system.cpu2.num_int_register_writes 371535 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu2.num_mem_refs 180790 # number of memory refs
-system.cpu2.num_load_insts 124441 # Number of load instructions
+system.cpu2.num_mem_refs 180792 # number of memory refs
+system.cpu2.num_load_insts 124443 # Number of load instructions
system.cpu2.num_store_insts 56349 # Number of store instructions
system.cpu2.num_idle_cycles 0 # Number of idle cycles
-system.cpu2.num_busy_cycles 1458048 # Number of busy cycles
+system.cpu2.num_busy_cycles 1455807 # Number of busy cycles
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0 # Percentage of idle cycles
system.cpu2.Branches 59022 # Number of branches fetched
system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu2.op_class::IntAlu 300376 60.07% 63.84% # Class of executed instruction
+system.cpu2.op_class::IntAlu 300380 60.07% 63.84% # Class of executed instruction
system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
@@ -1150,118 +708,35 @@ system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Cl
system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction
+system.cpu2.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::total 500004 # Class of executed instruction
-system.cpu2.icache.tags.replacements 152 # number of replacements
-system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 500468 # Number of tag accesses
-system.cpu2.icache.tags.data_accesses 500468 # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 499542 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 499542 # number of overall hits
-system.cpu2.icache.overall_hits::total 499542 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
-system.cpu2.icache.overall_misses::total 463 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23114000 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 23114000 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 23114000 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 23114000 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 23114000 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 23114000 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 500005 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 500005 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 500005 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 500005 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 500005 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 500005 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49922.246220 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 49922.246220 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49922.246220 # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 49922.246220 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49922.246220 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 49922.246220 # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes 0 # number of fast writes performed
-system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22188000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 22188000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22188000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 22188000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22188000 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 22188000 # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 47922.246220 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.op_class::total 500010 # Class of executed instruction
system.cpu2.dcache.tags.replacements 61 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse 273.592761 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.592761 # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534361 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total 0.534361 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 723551 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 723551 # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
+system.cpu2.dcache.tags.tag_accesses 723559 # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses 723559 # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 180309 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 180309 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 180309 # number of overall hits
-system.cpu2.dcache.overall_hits::total 180309 # number of overall hits
+system.cpu2.dcache.demand_hits::cpu2.data 180311 # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total 180311 # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data 180311 # number of overall hits
+system.cpu2.dcache.overall_hits::total 180311 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
@@ -1270,22 +745,22 @@ system.cpu2.dcache.demand_misses::cpu2.data 463 #
system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
system.cpu2.dcache.overall_misses::total 463 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17474500 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7669500 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 25144000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 25144000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 124433 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17443000 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total 17443000 # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7645000 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data 25088000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total 25088000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data 25088000 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total 25088000 # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 180772 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 180772 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
+system.cpu2.dcache.demand_accesses::cpu2.data 180774 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data 180774 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
@@ -1294,14 +769,14 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561
system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53933.641975 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55176.258993 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54306.695464 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54306.695464 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53836.419753 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 53836.419753 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55000 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54185.745140 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 54185.745140 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54185.745140 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 54185.745140 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1320,14 +795,14 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 463
system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16826500 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7391500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24218000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24218000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16957000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16957000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7436500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24393500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 24393500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24393500 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 24393500 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -1336,35 +811,118 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561
system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51933.641975 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53176.258993 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52306.695464 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52306.695464 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52336.419753 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53500 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52685.745140 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52685.745140 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52685.745140 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.icache.tags.replacements 152 # number of replacements
+system.cpu2.icache.tags.tagsinuse 216.433362 # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs 499548 # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs 1078.937365 # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.433362 # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422721 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total 0.422721 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses 500474 # Number of tag accesses
+system.cpu2.icache.tags.data_accesses 500474 # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst 499548 # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total 499548 # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst 499548 # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total 499548 # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst 499548 # number of overall hits
+system.cpu2.icache.overall_hits::total 499548 # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
+system.cpu2.icache.overall_misses::total 463 # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 22957500 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total 22957500 # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst 22957500 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total 22957500 # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst 22957500 # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total 22957500 # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst 500011 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total 500011 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst 500011 # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total 500011 # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst 500011 # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total 500011 # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49584.233261 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 49584.233261 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49584.233261 # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 49584.233261 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49584.233261 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 49584.233261 # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu2.icache.fast_writes 0 # number of fast writes performed
+system.cpu2.icache.cache_copies 0 # number of cache copies performed
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22263000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total 22263000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22263000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 22263000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22263000 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 22263000 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48084.233261 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 48084.233261 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48084.233261 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 48084.233261 # average overall mshr miss latency
+system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.fetch_acv 0 # ITB acv
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
-system.cpu3.dtb.read_hits 124431 # DTB read hits
+system.cpu3.dtb.read_hits 124433 # DTB read hits
system.cpu3.dtb.read_misses 8 # DTB read misses
system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_accesses 124439 # DTB read accesses
+system.cpu3.dtb.read_accesses 124441 # DTB read accesses
system.cpu3.dtb.write_hits 56339 # DTB write hits
system.cpu3.dtb.write_misses 10 # DTB write misses
system.cpu3.dtb.write_acv 0 # DTB write access violations
system.cpu3.dtb.write_accesses 56349 # DTB write accesses
-system.cpu3.dtb.data_hits 180770 # DTB hits
+system.cpu3.dtb.data_hits 180772 # DTB hits
system.cpu3.dtb.data_misses 18 # DTB misses
system.cpu3.dtb.data_acv 0 # DTB access violations
-system.cpu3.dtb.data_accesses 180788 # DTB accesses
-system.cpu3.itb.fetch_hits 499998 # ITB hits
+system.cpu3.dtb.data_accesses 180790 # DTB accesses
+system.cpu3.itb.fetch_hits 500007 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_accesses 500011 # ITB accesses
+system.cpu3.itb.fetch_accesses 500020 # ITB accesses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.read_acv 0 # DTB read access violations
@@ -1378,31 +936,31 @@ system.cpu3.itb.data_misses 0 # DT
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.cpu3.numCycles 1458048 # number of cpu cycles simulated
+system.cpu3.numCycles 1455807 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 499979 # Number of instructions committed
-system.cpu3.committedOps 499979 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 474668 # Number of integer alu accesses
+system.cpu3.committedInsts 499988 # Number of instructions committed
+system.cpu3.committedOps 499988 # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses 474676 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu3.num_func_calls 14357 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 474668 # number of integer instructions
+system.cpu3.num_conditional_control_insts 38179 # number of instructions that are conditional controls
+system.cpu3.num_int_insts 474676 # number of integer instructions
system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 371524 # number of times the integer registers were written
+system.cpu3.num_int_register_reads 654266 # number of times the integer registers were read
+system.cpu3.num_int_register_writes 371531 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu3.num_mem_refs 180788 # number of memory refs
-system.cpu3.num_load_insts 124439 # Number of load instructions
+system.cpu3.num_mem_refs 180790 # number of memory refs
+system.cpu3.num_load_insts 124441 # Number of load instructions
system.cpu3.num_store_insts 56349 # Number of store instructions
system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_busy_cycles 1458048 # Number of busy cycles
+system.cpu3.num_busy_cycles 1455807 # Number of busy cycles
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.Branches 59020 # Number of branches fetched
+system.cpu3.Branches 59022 # Number of branches fetched
system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu 300371 60.07% 63.84% # Class of executed instruction
+system.cpu3.op_class::IntAlu 300378 60.07% 63.84% # Class of executed instruction
system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
@@ -1431,118 +989,35 @@ system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Cl
system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::MemRead 124439 24.89% 88.73% # Class of executed instruction
+system.cpu3.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction
system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 499997 # Class of executed instruction
-system.cpu3.icache.tags.replacements 152 # number of replacements
-system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 500461 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 500461 # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 499535 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 499535 # number of overall hits
-system.cpu3.icache.overall_hits::total 499535 # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
-system.cpu3.icache.overall_misses::total 463 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23123000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 23123000 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 23123000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 23123000 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst 23123000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total 23123000 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 499998 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 499998 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 499998 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 499998 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 499998 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 499998 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49941.684665 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 49941.684665 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 49941.684665 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49941.684665 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 49941.684665 # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22197000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 22197000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22197000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 22197000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22197000 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 22197000 # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 47941.684665 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.op_class::total 500006 # Class of executed instruction
system.cpu3.dcache.tags.replacements 61 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse 273.589931 # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.589931 # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534355 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total 0.534355 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 723543 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 723543 # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
+system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses 723551 # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data 124109 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 180307 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 180307 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 180307 # number of overall hits
-system.cpu3.dcache.overall_hits::total 180307 # number of overall hits
+system.cpu3.dcache.demand_hits::cpu3.data 180309 # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total 180309 # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data 180309 # number of overall hits
+system.cpu3.dcache.overall_hits::total 180309 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
@@ -1551,22 +1026,22 @@ system.cpu3.dcache.demand_misses::cpu3.data 463 #
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
system.cpu3.dcache.overall_misses::total 463 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17474500 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 17474500 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7669500 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data 25144000 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total 25144000 # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data 25144000 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total 25144000 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 124431 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 124431 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17443500 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total 17443500 # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7645500 # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total 7645500 # number of WriteReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data 25089000 # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total 25089000 # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data 25089000 # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total 25089000 # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data 124433 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 180770 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 180770 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 180770 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 180770 # number of overall (read+write) accesses
+system.cpu3.dcache.demand_accesses::cpu3.data 180772 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data 180772 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
@@ -1575,14 +1050,14 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561
system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53933.641975 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 53933.641975 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55176.258993 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54306.695464 # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 54306.695464 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54306.695464 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 54306.695464 # average overall miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53837.962963 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 53837.962963 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55003.597122 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 55003.597122 # average WriteReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54187.904968 # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 54187.904968 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54187.904968 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 54187.904968 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1601,14 +1076,14 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 463
system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16826500 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16826500 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7391500 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24218000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total 24218000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24218000 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total 24218000 # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16957500 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16957500 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7437000 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7437000 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24394500 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total 24394500 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24394500 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total 24394500 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses
@@ -1617,14 +1092,539 @@ system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561
system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51933.641975 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 51933.641975 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53176.258993 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 52337.962963 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52337.962963 # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53503.597122 # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53503.597122 # average WriteReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52687.904968 # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52687.904968 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52687.904968 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52687.904968 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.icache.tags.replacements 152 # number of replacements
+system.cpu3.icache.tags.tagsinuse 216.431169 # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs 499544 # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs 1078.928726 # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.431169 # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422717 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total 0.422717 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses 500470 # Number of tag accesses
+system.cpu3.icache.tags.data_accesses 500470 # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst 499544 # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total 499544 # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst 499544 # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total 499544 # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst 499544 # number of overall hits
+system.cpu3.icache.overall_hits::total 499544 # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
+system.cpu3.icache.overall_misses::total 463 # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 22962500 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total 22962500 # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst 22962500 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total 22962500 # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst 22962500 # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total 22962500 # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 500007 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 500007 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst 500007 # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total 500007 # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst 500007 # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total 500007 # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49595.032397 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 49595.032397 # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49595.032397 # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 49595.032397 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49595.032397 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 49595.032397 # average overall miss latency
+system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu3.icache.fast_writes 0 # number of fast writes performed
+system.cpu3.icache.cache_copies 0 # number of cache copies performed
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22268000 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total 22268000 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22268000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total 22268000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22268000 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total 22268000 # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48095.032397 # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48095.032397 # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48095.032397 # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 48095.032397 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48095.032397 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 48095.032397 # average overall mshr miss latency
+system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.tags.replacements 0 # number of replacements
+system.l2c.tags.tagsinuse 1943.831902 # Cycle average of tags in use
+system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 17.239792 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 265.090633 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 216.564822 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 265.087863 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 216.562658 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 265.085095 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 216.560494 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst 265.082241 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data 216.558304 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.004045 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.003305 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.004045 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.003304 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.004045 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.003304 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst 0.004045 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data 0.003304 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.029661 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 2904 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 34048 # Number of tag accesses
+system.l2c.tags.data_accesses 34048 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
+system.l2c.Writeback_hits::total 116 # number of Writeback hits
+system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
+system.l2c.demand_hits::total 276 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu0.data 9 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu1.data 9 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu2.data 9 # number of overall hits
+system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
+system.l2c.overall_hits::cpu3.data 9 # number of overall hits
+system.l2c.overall_hits::total 276 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
+system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
+system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu0.data 454 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu1.data 454 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu2.data 454 # number of overall misses
+system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
+system.l2c.overall_misses::cpu3.data 454 # number of overall misses
+system.l2c.overall_misses::total 3428 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst 21158500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 16537500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 21164500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 16537500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 21169000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 16538500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst 21172000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.data 16539000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 150816500 # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 7297500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 7297500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 7297500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data 7298000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 29190500 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 21158500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 23835000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 21164500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 23835000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 21169000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 23836000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst 21172000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data 23837000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 180007000 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 21158500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 23835000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 21164500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 23835000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 21169000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 23836000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst 21172000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data 23837000 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 180007000 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52502.481390 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52517.369727 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52528.535980 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 52503.174603 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52535.980149 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.data 52504.761905 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52512.708914 # average ReadReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52500 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52503.597122 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52500.899281 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52502.481390 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52517.369727 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52500 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 52528.535980 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 52502.202643 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 52535.980149 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 52504.405286 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52510.793466 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52502.481390 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52517.369727 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 52528.535980 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 52502.202643 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 52535.980149 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 52504.405286 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52510.793466 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.ReadReq_mshr_misses::cpu0.inst 403 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 315 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 403 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 315 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst 403 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data 315 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.inst 403 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.data 315 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 2872 # number of ReadReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data 139 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 556 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 403 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 454 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 403 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 454 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 403 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 454 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst 403 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data 454 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 3428 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 403 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 454 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 403 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 454 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 403 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 454 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 16321500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12757500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 16328500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12757500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 16333000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 12758500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 16335500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.data 12758500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 116350500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5629500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5629500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5629500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5629500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 22518000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 16321500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 18387000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 16328500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 18387000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 16333000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 18388000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst 16335500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data 18388000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 138868500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 16321500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 18387000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 16328500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 18387000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 16333000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 18388000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst 16335500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data 18388000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 138868500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.912325 # mshr miss rate for ReadReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40517.369727 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40503.174603 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40503.174603 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40512.012535 # average ReadReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40517.369727 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40502.202643 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40502.202643 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40510.064177 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40517.369727 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40528.535980 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40502.202643 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40534.739454 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40502.202643 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40510.064177 # average overall mshr miss latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 2872 # Transaction distribution
+system.membus.trans_dist::ReadResp 2872 # Transaction distribution
+system.membus.trans_dist::ReadExReq 556 # Transaction distribution
+system.membus.trans_dist::ReadExResp 556 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3437 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3437 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 3437 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3440968 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 17142500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 2.4 # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq 3148 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 116 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 926 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 955 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7524 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 29632 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 244480 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 0 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3820 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 3820 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3820 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2026000 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 694500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------