diff options
| -rw-r--r-- | src/cpu/BaseCPU.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 85e37776e..143ee9224 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -182,8 +182,8 @@ class BaseCPU(ClockedObject): dtb = Param.BaseTLB(ArchDTB(), "Data TLB") itb = Param.BaseTLB(ArchITB(), "Instruction TLB") if buildEnv['TARGET_ISA'] == 'arm': - istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") - dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") + istage2_mmu = ArmStage2IMMU() + dstage2_mmu = ArmStage2DMMU() elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") interrupts = ArchInterruptsParam([], "Interrupt Controller") |