summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py48
-rw-r--r--src/arch/x86/isa/microops/regop.isa2
2 files changed, 49 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py
index 8a036ef58..264bbe370 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py
@@ -56,12 +56,14 @@
microcode = '''
def macroop CMOVZ_R_R
{
+ mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, regm, flags=(CZF,)
};
def macroop CMOVZ_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, t1, flags=(CZF,)
};
@@ -69,17 +71,20 @@ def macroop CMOVZ_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, t1, flags=(CZF,)
};
def macroop CMOVNZ_R_R
{
+ mov reg, reg, reg, flags=(CZF,)
mov reg, reg, regm, flags=(nCZF,)
};
def macroop CMOVNZ_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CZF,)
mov reg, reg, t1, flags=(nCZF,)
};
@@ -87,17 +92,20 @@ def macroop CMOVNZ_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CZF,)
mov reg, reg, t1, flags=(nCZF,)
};
def macroop CMOVB_R_R
{
+ mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, regm, flags=(CCF,)
};
def macroop CMOVB_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, t1, flags=(CCF,)
};
@@ -105,17 +113,20 @@ def macroop CMOVB_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, t1, flags=(CCF,)
};
def macroop CMOVNB_R_R
{
+ mov reg, reg, reg, flags=(CCF,)
mov reg, reg, regm, flags=(nCCF,)
};
def macroop CMOVNB_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CCF,)
mov reg, reg, t1, flags=(nCCF,)
};
@@ -123,17 +134,20 @@ def macroop CMOVNB_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CCF,)
mov reg, reg, t1, flags=(nCCF,)
};
def macroop CMOVBE_R_R
{
+ mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, regm, flags=(CCvZF,)
};
def macroop CMOVBE_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, t1, flags=(CCvZF,)
};
@@ -141,17 +155,20 @@ def macroop CMOVBE_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, t1, flags=(CCvZF,)
};
def macroop CMOVNBE_R_R
{
+ mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, regm, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
@@ -159,17 +176,20 @@ def macroop CMOVNBE_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVS_R_R
{
+ mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, regm, flags=(CSF,)
};
def macroop CMOVS_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, t1, flags=(CSF,)
};
@@ -177,17 +197,20 @@ def macroop CMOVS_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, t1, flags=(CSF,)
};
def macroop CMOVNS_R_R
{
+ mov reg, reg, reg, flags=(CSF,)
mov reg, reg, regm, flags=(nCSF,)
};
def macroop CMOVNS_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CSF,)
mov reg, reg, t1, flags=(nCSF,)
};
@@ -195,17 +218,20 @@ def macroop CMOVNS_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CSF,)
mov reg, reg, t1, flags=(nCSF,)
};
def macroop CMOVP_R_R
{
+ mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, regm, flags=(CPF,)
};
def macroop CMOVP_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, t1, flags=(CPF,)
};
@@ -213,17 +239,20 @@ def macroop CMOVP_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, t1, flags=(CPF,)
};
def macroop CMOVNP_R_R
{
+ mov reg, reg, reg, flags=(CPF,)
mov reg, reg, regm, flags=(nCPF,)
};
def macroop CMOVNP_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CPF,)
mov reg, reg, t1, flags=(nCPF,)
};
@@ -231,17 +260,20 @@ def macroop CMOVNP_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CPF,)
mov reg, reg, t1, flags=(nCPF,)
};
def macroop CMOVL_R_R
{
+ mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, regm, flags=(CSxOF,)
};
def macroop CMOVL_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, t1, flags=(CSxOF,)
};
@@ -249,17 +281,20 @@ def macroop CMOVL_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, t1, flags=(CSxOF,)
};
def macroop CMOVNL_R_R
{
+ mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, regm, flags=(nCSxOF,)
};
def macroop CMOVNL_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, t1, flags=(nCSxOF,)
};
@@ -267,17 +302,20 @@ def macroop CMOVNL_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, t1, flags=(nCSxOF,)
};
def macroop CMOVLE_R_R
{
+ mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, regm, flags=(CSxOvZF,)
};
def macroop CMOVLE_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, t1, flags=(CSxOvZF,)
};
@@ -285,17 +323,20 @@ def macroop CMOVLE_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, t1, flags=(CSxOvZF,)
};
def macroop CMOVNLE_R_R
{
+ mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, regm, flags=(nCSxOvZF,)
};
def macroop CMOVNLE_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, t1, flags=(nCSxOvZF,)
};
@@ -303,17 +344,20 @@ def macroop CMOVNLE_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, t1, flags=(nCSxOvZF,)
};
def macroop CMOVO_R_R
{
+ mov reg, reg, reg, flags=(nCOF,)
mov reg, reg, regm, flags=(COF,)
};
def macroop CMOVO_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(nCOF,)
mov reg, reg, t1, flags=(COF,)
};
@@ -321,17 +365,20 @@ def macroop CMOVO_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(nCOF,)
mov reg, reg, t1, flags=(COF,)
};
def macroop CMOVNO_R_R
{
+ mov reg, reg, reg, flags=(COF,)
mov reg, reg, regm, flags=(nCOF,)
};
def macroop CMOVNO_R_M
{
ld t1, seg, sib, disp
+ mov reg, reg, reg, flags=(COF,)
mov reg, reg, t1, flags=(nCOF,)
};
@@ -339,6 +386,7 @@ def macroop CMOVNO_R_P
{
rdip t7
ld t1, seg, riprel, disp
+ mov reg, reg, reg, flags=(COF,)
mov reg, reg, t1, flags=(nCOF,)
};
'''
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 017ac49e4..a4cb6f4cc 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -639,7 +639,7 @@ let {{
class Mov(CondRegOp):
code = 'DestReg = merge(SrcReg1, op2, dataSize)'
- else_code = 'DestReg = merge(DestReg, DestReg, dataSize);'
+ else_code = 'DestReg = DestReg;'
# Shift instructions