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| -rw-r--r-- | configs/example/arm/devices.py | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 4615daac2..02b9bd7f0 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -159,6 +159,31 @@ class CpuCluster(SubSystem): cpu.connectAllPorts(self.toL2Bus) self.toL2Bus.master = self.l2.cpu_side + def addPMUs(self, ints, events=[]): + """ + Instantiates 1 ArmPMU per PE. The method is accepting a list of + interrupt numbers (ints) used by the PMU and a list of events to + register in it. + + :param ints: List of interrupt numbers. The code will iterate over + the cpu list in order and will assign to every cpu in the cluster + a PMU with the matching interrupt. + :type ints: List[int] + :param events: Additional events to be measured by the PMUs + :type events: List[Union[ProbeEvent, SoftwareIncrement]] + """ + assert len(ints) == len(self.cpus) + for cpu, pint in zip(self.cpus, ints): + int_cls = ArmPPI if pint < 32 else ArmSPI + for isa in cpu.isa: + isa.pmu = ArmPMU(interrupt=int_cls(num=pint)) + isa.pmu.addArchEvents(cpu=cpu, itb=cpu.itb, dtb=cpu.dtb, + icache=getattr(cpu, 'icache', None), + dcache=getattr(cpu, 'dcache', None), + l2cache=getattr(self, 'l2', None)) + for ev in events: + isa.pmu.addEvent(ev) + def connectMemSide(self, bus): bus.slave try: |