diff options
| -rw-r--r-- | src/arch/arm/isa/formats/sve_2nd_level.isa | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa index c06d7f6a7..8bde189b2 100644 --- a/src/arch/arm/isa/formats/sve_2nd_level.isa +++ b/src/arch/arm/isa/formats/sve_2nd_level.isa @@ -3132,10 +3132,6 @@ namespace Aarch64 IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16); IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); - if (rm == 0x1f) { - return new Unknown64(machInst); - } - return decodeSveContigLoadSSInsts<SveContigFFLoadSS>( bits(machInst, 24, 21), machInst, zt, pg, rn, rm, true); } // decodeSveContigFFLoadSS |