diff options
| -rw-r--r-- | src/arch/arm/ArmISA.py | 6 | ||||
| -rw-r--r-- | src/arch/arm/isa.cc | 17 |
2 files changed, 19 insertions, 4 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 3c1f7dd11..7b7189565 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -57,7 +57,11 @@ class ArmISA(SimObject): pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit") decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification") - midr = Param.UInt32(0x410fc0f0, "MIDR value") + # If no MIDR value is provided, 0x0 is treated by gem5 as follows: + # When 'highest_el_is_64' (AArch64 support) is: + # True -> Cortex-A57 TRM r0p0 MIDR is used + # False -> Cortex-A15 TRM r0p0 MIDR is used + midr = Param.UInt32(0x0, "MIDR value") # See section B4.1.89 - B4.1.92 of the ARM ARM # VMSAv7 support diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 14cc993d1..767fd9f6a 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -319,9 +319,20 @@ void ISA::initID32(const ArmISAParams *p) { // Initialize configurable default values - miscRegs[MISCREG_MIDR] = p->midr; - miscRegs[MISCREG_MIDR_EL1] = p->midr; - miscRegs[MISCREG_VPIDR] = p->midr; + + uint32_t midr; + if (p->midr != 0x0) + midr = p->midr; + else if (highestELIs64) + // Cortex-A57 TRM r0p0 MIDR + midr = 0x410fd070; + else + // Cortex-A15 TRM r0p0 MIDR + midr = 0x410fc0f0; + + miscRegs[MISCREG_MIDR] = midr; + miscRegs[MISCREG_MIDR_EL1] = midr; + miscRegs[MISCREG_VPIDR] = midr; miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; |