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-rw-r--r--configs/common/CacheConfig.py27
-rw-r--r--configs/common/HWPConfig.py88
-rw-r--r--configs/common/Options.py28
3 files changed, 143 insertions, 0 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 946060768..f705ab09a 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -47,6 +47,7 @@ from __future__ import absolute_import
import m5
from m5.objects import *
from .Caches import *
+from . import HWPConfig
def config_cache(options, system):
if options.external_memory_system and (options.caches or options.l2cache):
@@ -104,6 +105,14 @@ def config_cache(options, system):
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
+ if options.l2_hwp_type:
+ hwpClass = HWPConfig.get(options.l2_hwp_type)
+ if system.l2.prefetcher != "Null":
+ print("Warning: l2-hwp-type is set (", hwpClass, "), but",
+ "the current l2 has a default Hardware Prefetcher",
+ "of type", type(system.l2.prefetcher), ", using the",
+ "specified by the flag option.")
+ system.l2.prefetcher = hwpClass()
if options.memchecker:
system.memchecker = MemChecker()
@@ -139,6 +148,24 @@ def config_cache(options, system):
# Let CPU connect to monitors
dcache = dcache_mon
+ if options.l1d_hwp_type:
+ hwpClass = HWPConfig.get(options.l1d_hwp_type)
+ if dcache.prefetcher != m5.params.NULL:
+ print("Warning: l1d-hwp-type is set (", hwpClass, "), but",
+ "the current l1d has a default Hardware Prefetcher",
+ "of type", type(dcache.prefetcher), ", using the",
+ "specified by the flag option.")
+ dcache.prefetcher = hwpClass()
+
+ if options.l1i_hwp_type:
+ hwpClass = HWPConfig.get(options.l1i_hwp_type)
+ if icache.prefetcher != m5.params.NULL:
+ print("Warning: l1i-hwp-type is set (", hwpClass, "), but",
+ "the current l1i has a default Hardware Prefetcher",
+ "of type", type(icache.prefetcher), ", using the",
+ "specified by the flag option.")
+ icache.prefetcher = hwpClass()
+
# When connecting the caches, the clock is also inherited
# from the CPU in question
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
diff --git a/configs/common/HWPConfig.py b/configs/common/HWPConfig.py
new file mode 100644
index 000000000..dd8cafa2e
--- /dev/null
+++ b/configs/common/HWPConfig.py
@@ -0,0 +1,88 @@
+# Copyright (c) 2018 Metempsy Technology Consulting
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Pau Cabre
+
+# This file is a copy of MemConfig.py / CpuConfig.py, but modified to
+# hanle branch predictors instead of memory controllers / CPUs
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+from m5 import fatal
+import m5.objects
+import inspect
+import sys
+from textwrap import TextWrapper
+
+# Dictionary of mapping names of real branch predictor models to classes.
+_hwp_classes = {}
+
+
+def is_hwp_class(cls):
+ """Determine if a class is a prefetcher that can be instantiated"""
+
+ # We can't use the normal inspect.isclass because the ParamFactory
+ # and ProxyFactory classes have a tendency to confuse it.
+ try:
+ return issubclass(cls, m5.objects.BasePrefetcher) and \
+ not cls.abstract
+ except (TypeError, AttributeError):
+ return False
+
+def get(name):
+ """Get a HWP class from a user provided class name or alias."""
+
+ try:
+ hwp_class = _hwp_classes[name]
+ return hwp_class
+ except KeyError:
+ print("%s is not a valid HWP model." % (name,))
+ sys.exit(1)
+
+def print_hwp_list():
+ """Print a list of available HWP classes."""
+
+ print("Available Hardware Prefetcher classes:")
+ doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
+ for name, cls in _hwp_classes.items():
+ print("\t%s" % name)
+
+ # Try to extract the class documentation from the class help
+ # string.
+ doc = inspect.getdoc(cls)
+ if doc:
+ for line in doc_wrapper.wrap(doc):
+ print(line)
+
+def hwp_names():
+ """Return a list of valid Hardware Prefetcher names."""
+ return list(_hwp_classes.keys())
+
+# Add all HWPs in the object hierarchy.
+for name, cls in inspect.getmembers(m5.objects, is_hwp_class):
+ _hwp_classes[name] = cls
+
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 6d9c9cf37..58078ec86 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -48,6 +48,7 @@ from m5.objects import *
from .Benchmarks import *
from . import CpuConfig
from . import BPConfig
+from . import HWPConfig
from . import MemConfig
from . import PlatformConfig
@@ -59,6 +60,10 @@ def _listBPTypes(option, opt, value, parser):
BPConfig.print_bp_list()
sys.exit(0)
+def _listHWPTypes(option, opt, value, parser):
+ HWPConfig.print_hwp_list()
+ sys.exit(0)
+
def _listMemTypes(option, opt, value, parser):
MemConfig.print_mem_list()
sys.exit(0)
@@ -163,6 +168,29 @@ def addCommonOptions(parser):
type of branch predictor to run with
(if not set, use the default branch predictor of
the selected CPU)""")
+ parser.add_option("--list-hwp-types",
+ action="callback", callback=_listHWPTypes,
+ help="List available hardware prefetcher types")
+ parser.add_option("--l1i-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L1
+ instruction cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
+ parser.add_option("--l1d-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L1
+ data cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
+ parser.add_option("--l2-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L2 cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
parser.add_option("--checker", action="store_true");
parser.add_option("--cpu-clock", action="store", type="string",
default='2GHz',
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-25 08:59:02 +0000