diff options
| -rw-r--r-- | src/dev/arm/gic_v3_cpu_interface.cc | 14 | ||||
| -rw-r--r-- | src/dev/arm/gic_v3_cpu_interface.hh | 2 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index cc630b4d2..d3d73a32f 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -1623,6 +1623,20 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) } } +RegVal +Gicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const +{ + return isa->readMiscRegNoEffect( + isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3())); +} + +void +Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const +{ + isa->setMiscRegNoEffect( + isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val); +} + int Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const { diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh index 56a66952c..9e1c9a09f 100644 --- a/src/dev/arm/gic_v3_cpu_interface.hh +++ b/src/dev/arm/gic_v3_cpu_interface.hh @@ -338,6 +338,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable void virtualUpdate(); RegVal bpr1(Gicv3::GroupId group); + RegVal readBankedMiscReg(MiscRegIndex misc_reg) const; + void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const; public: Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id); |