diff options
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 8 | ||||
| -rw-r--r-- | src/arch/arm/utility.cc | 9 | ||||
| -rw-r--r-- | src/arch/arm/utility.hh | 4 |
3 files changed, 16 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 92a6b53f1..ecf09aab5 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013,2017-2018 ARM Limited +// Copyright (c) 2010-2013,2017-2019 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -784,11 +784,9 @@ let {{ ThreadContext *oc = sys->getThreadContext(x); if (oc == xc->tcBase()) continue; + // Wake CPU with interrupt if they were sleeping - if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { - // Post Interrupt and wake cpu if needed - oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0); - } + sendEvent(oc); } ''' sevIop = InstObjParams("sev", "SevInst", "PredOp", \ diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 924024d0e..d68850c5f 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -192,6 +192,15 @@ copyRegs(ThreadContext *src, ThreadContext *dest) dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg(); } +void +sendEvent(ThreadContext *tc) +{ + if (tc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { + // Post Interrupt and wake cpu if needed + tc->getCpuPtr()->postInterrupt(tc->threadId(), INT_SEV, 0); + } +} + bool inSecureState(ThreadContext *tc) { diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 3a1506114..96f6843c3 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -117,6 +117,10 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest) void initCPU(ThreadContext *tc, int cpuId); +/** Send an event (SEV) to a specific PE if there isn't + * already a pending event */ +void sendEvent(ThreadContext *tc); + static inline bool inUserMode(CPSR cpsr) { |