diff options
| -rw-r--r-- | src/dev/arm/gic_v3_cpu_interface.cc | 9 | ||||
| -rw-r--r-- | src/dev/arm/gic_v3_cpu_interface.hh | 1 | ||||
| -rw-r--r-- | src/dev/arm/gic_v3_distributor.cc | 2 |
3 files changed, 10 insertions, 2 deletions
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index 73257a718..67f5a39d3 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -70,6 +70,13 @@ Gicv3CPUInterface::init() } void +Gicv3CPUInterface::resetHppi(uint32_t intid) +{ + if (intid == hppi.intid) + hppi.prio = 0xff; +} + +void Gicv3CPUInterface::setThreadContext(ThreadContext *tc) { maintenanceInterrupt = gic->params()->maint_int->get(tc); @@ -1843,7 +1850,7 @@ Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) // By setting the priority to 0xff we are effectively // making the int_id not pending anymore at the cpu // interface. - hppi.prio = 0xff; + resetHppi(int_id); updateDistributor(); } diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh index c88e1f635..3b235ec1c 100644 --- a/src/dev/arm/gic_v3_cpu_interface.hh +++ b/src/dev/arm/gic_v3_cpu_interface.hh @@ -322,6 +322,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable bool isEOISplitMode() const; bool isSecureBelowEL3() const; ICH_MISR_EL2 maintenanceInterruptStatus() const; + void resetHppi(uint32_t intid); void serialize(CheckpointOut & cp) const override; void unserialize(CheckpointIn & cp) override; void update(); diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc index fd43326c1..e38fa185c 100644 --- a/src/dev/arm/gic_v3_distributor.cc +++ b/src/dev/arm/gic_v3_distributor.cc @@ -1055,7 +1055,7 @@ Gicv3Distributor::clearIrqCpuInterface(uint32_t int_id) { auto cpu_interface = route(int_id); if (cpu_interface) - cpu_interface->hppi.prio = 0xff; + cpu_interface->resetHppi(int_id); } void |