diff options
434 files changed, 9815 insertions, 3397 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 048f742ca..bf1bde417 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -936,9 +936,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -998,10 +997,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -1057,9 +1055,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index a7ff9525f..9e5305367 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:31:55 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index fbb891fc7..e3ecd4b02 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,23 +4,50 @@ sim_seconds 1.899401 # Nu sim_ticks 1899401490000 # Number of ticks simulated final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69911 # Simulator instruction rate (inst/s) -host_op_rate 69911 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2348556801 # Simulator tick rate (ticks/s) -host_mem_usage 300512 # Number of bytes of host memory used -host_seconds 808.75 # Real time elapsed on the host +host_inst_rate 124517 # Simulator instruction rate (inst/s) +host_op_rate 124517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4182952627 # Simulator tick rate (ticks/s) +host_mem_usage 300876 # Number of bytes of host memory used +host_seconds 454.08 # Real time elapsed on the host sim_insts 56540749 # Number of instructions simulated sim_ops 56540749 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30421696 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10508736 # Number of bytes written to this memory -system.physmem.num_reads 475339 # Number of read requests responded to by this memory -system.physmem.num_writes 164199 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16016464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 596702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5532657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21549121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 865216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25431680 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 268160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1206144 # Number of bytes read from this memory +system.physmem.bytes_read::total 30421696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 865216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 268160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1133376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10508736 # Number of bytes written to this memory +system.physmem.bytes_written::total 10508736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 397370 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 18846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 475339 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 164199 # Number of write requests responded to by this memory +system.physmem.num_writes::total 164199 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 455520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13389312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 141181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 635013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16016464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 455520 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 141181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 596702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5532657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5532657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5532657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 455520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13389312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 141181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 635013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21549121 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 397771 # number of replacements system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use system.l2c.total_refs 2469954 # Total number of references to valid blocks. @@ -142,38 +169,50 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.014629 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.301431 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.023663 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.026314 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141923 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945624 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847087 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.924975 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.867133 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901235 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.885246 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.414779 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.474003 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.421493 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.014629 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.325894 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.023663 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.123786 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.175450 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.014629 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.325894 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.023663 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.123786 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.175450 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52306.597145 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52040.352799 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52326.955075 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 50733.511307 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52042.436289 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 692.922763 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3665.472779 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1263.403904 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17356.854839 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5568.493151 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 10982.407407 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52463.410281 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52413.706697 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52457.073833 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52161.894298 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52161.894298 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -254,44 +293,59 @@ system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014628 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.301431 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026314 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141914 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945624 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847087 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.924975 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.867133 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.901235 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.885246 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.414779 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.474003 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.421493 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.175443 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.175443 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.837812 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39448.492462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40026.250295 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.041511 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40004.297994 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40002.474567 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40004.032258 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.712329 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40002.777778 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40298.511698 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40214.276765 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40287.773030 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41698 # number of replacements system.iocache.tagsinuse 0.205020 # Cycle average of tags in use @@ -327,13 +381,21 @@ system.iocache.demand_accesses::total 41730 # nu system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115247.179775 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137665.980121 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137570.352360 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137570.352360 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked @@ -361,13 +423,21 @@ system.iocache.demand_mshr_miss_latency::total 3570695996 system.iocache.overall_mshr_miss_latency::tsunami.ide 3570695996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.179775 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85662.254476 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -751,11 +821,17 @@ system.cpu0.icache.demand_accesses::total 7876403 # n system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.123657 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.123657 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.123657 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14933.529195 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14933.529195 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14933.529195 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked @@ -785,11 +861,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.117352 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.117352 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.117352 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11922.673044 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1225027 # number of replacements system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use @@ -849,17 +931,29 @@ system.cpu0.dcache.demand_accesses::total 13473054 # n system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.193416 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.311981 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104660 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.010046 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.241498 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.241498 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22449.520533 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30909.202624 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14534.120482 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12237.192118 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26881.500057 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26881.500057 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked @@ -911,20 +1005,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118800 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049117 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083087 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.010046 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.090541 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.090541 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24163.211588 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29457.684102 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11127.026043 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9233.497537 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -1265,11 +1374,17 @@ system.cpu1.icache.demand_accesses::total 1679880 # n system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.112150 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.112150 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.112150 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15322.238028 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15322.238028 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15322.238028 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked @@ -1299,11 +1414,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105852 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.105852 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.105852 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12305.163144 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 156190 # number of replacements system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use @@ -1363,17 +1484,29 @@ system.cpu1.dcache.demand_accesses::total 2874738 # n system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.125808 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.220031 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.138024 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081077 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.160323 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.160323 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15786.348523 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32638.570657 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13052.205690 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13354.471956 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24258.512904 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24258.512904 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked @@ -1425,20 +1558,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.069742 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.035185 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106355 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080913 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.057083 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.057083 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12373.655046 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30498.203530 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8775.237127 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10377.215190 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed @@ -1466,6 +1614,7 @@ system.cpu0.kern.ipl_used::21 1 # fr system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.801750 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed @@ -1523,7 +1672,7 @@ system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.278972 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode @@ -1550,6 +1699,7 @@ system.cpu1.kern.ipl_used::0 0.998669 # fr system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.782648 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed @@ -1595,7 +1745,7 @@ system.cpu1.kern.mode_good::idle 169 system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.702972 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370812 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index a8321f91c..3ccfd349b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -512,9 +512,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -574,10 +573,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -633,9 +631,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6b30da191..f3bacddca 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:06 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:16:04 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index ae2948145..d7b6a1ccb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.858684 # Nu sim_ticks 1858684403000 # Number of ticks simulated final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73473 # Simulator instruction rate (inst/s) -host_op_rate 73473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2572309842 # Simulator tick rate (ticks/s) -host_mem_usage 296656 # Number of bytes of host memory used -host_seconds 722.57 # Real time elapsed on the host +host_inst_rate 125153 # Simulator instruction rate (inst/s) +host_op_rate 125153 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4381630644 # Simulator tick rate (ticks/s) +host_mem_usage 297044 # Number of bytes of host memory used +host_seconds 424.20 # Real time elapsed on the host sim_insts 53089851 # Number of instructions simulated sim_ops 53089851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29847552 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10195968 # Number of bytes written to this memory -system.physmem.num_reads 466368 # Number of read requests responded to by this memory -system.physmem.num_writes 159312 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16058429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 582365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5485583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21544012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1082432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 26112576 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652544 # Number of bytes read from this memory +system.physmem.bytes_read::total 29847552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1082432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1082432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10195968 # Number of bytes written to this memory +system.physmem.bytes_written::total 10195968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16913 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 408009 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41446 # Number of read requests responded to by this memory +system.physmem.num_reads::total 466368 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 159312 # Number of write requests responded to by this memory +system.physmem.num_writes::total 159312 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 582365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14048956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1427108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16058429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 582365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 582365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5485583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5485583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5485583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 582365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14048956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1427108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21544012 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 391653 # number of replacements system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use system.l2c.total_refs 2427420 # Total number of references to valid blocks. @@ -98,21 +115,32 @@ system.l2c.overall_accesses::cpu.data 1403007 # nu system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.144884 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.680851 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.389089 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.175120 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.175120 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52055.178139 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13296.875000 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52452.302421 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52164.425310 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52164.425310 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,25 +195,40 @@ system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.144884 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.680851 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.389089 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.175120 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.175120 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40034.215681 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41968.750000 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40285.591605 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.266745 # Cycle average of tags in use @@ -221,13 +264,21 @@ system.iocache.demand_accesses::total 41725 # nu system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137703.090248 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137609.989311 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137609.989311 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked @@ -255,13 +306,21 @@ system.iocache.demand_mshr_miss_latency::total 3571928992 system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85699.532971 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -645,11 +704,17 @@ system.cpu.icache.demand_accesses::total 9001683 # nu system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120654 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120654 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120654 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14978.890385 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14978.890385 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14978.890385 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked @@ -679,11 +744,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12299507497 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114017 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114017 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114017 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.817785 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1402627 # number of replacements system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use @@ -743,17 +814,29 @@ system.cpu.dcache.demand_accesses::total 15284608 # nu system.cpu.dcache.overall_accesses::cpu.data 15284608 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15284608 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197665 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.197665 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315555 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.315555 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107789 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000014 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000014 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.245154 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245154 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.245154 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245154 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21564.412465 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21564.412465 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29908.900809 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29908.900809 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14827.843607 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14827.843607 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27833.333333 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27833.333333 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25891.032108 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25891.032108 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 927127320 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked @@ -805,20 +888,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1233731998 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2137812498 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 2137812498 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118919 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118919 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048701 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048701 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082959 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082959 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000014 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000014 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090634 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090634 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22826.893897 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22826.893897 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28446.182850 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28446.182850 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11814.556470 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11814.556470 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24666.666667 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24666.666667 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed @@ -842,6 +940,7 @@ system.cpu.kern.ipl_used::0 0.981743 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815921 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -899,7 +998,7 @@ system.cpu.kern.mode_good::idle 170 system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401737 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.389995 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index b11582c4e..5d60c7bc8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -570,9 +571,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -631,10 +631,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -1046,9 +1045,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 1bca46ae4..086d512f2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:58:44 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2501685689500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 2501dfd76..e9f646cad 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.501686 # Nu sim_ticks 2501685689500 # Number of ticks simulated final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54158 # Simulator instruction rate (inst/s) -host_op_rate 69928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2274069684 # Simulator tick rate (ticks/s) -host_mem_usage 384504 # Number of bytes of host memory used -host_seconds 1100.09 # Real time elapsed on the host +host_inst_rate 49441 # Simulator instruction rate (inst/s) +host_op_rate 63837 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2075989543 # Simulator tick rate (ticks/s) +host_mem_usage 387400 # Number of bytes of host memory used +host_seconds 1205.06 # Real time elapsed on the host sim_insts 59579009 # Number of instructions simulated sim_ops 76926775 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585736 # Number of bytes written to this memory -system.physmem.num_reads 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes 856669 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory +system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 119797 # number of replacements system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use system.l2c.total_refs 1834134 # Total number of references to valid blocks. @@ -139,32 +170,44 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -241,37 +284,52 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -676,11 +734,17 @@ system.cpu.icache.demand_accesses::total 13709800 # nu system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked @@ -714,13 +778,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 645895 # number of replacements system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use @@ -780,17 +852,29 @@ system.cpu.dcache.demand_accesses::total 25214634 # nu system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked @@ -842,20 +926,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -876,7 +975,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 632f13a19..aff8253f7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -953,9 +954,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -1014,10 +1014,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -1429,9 +1428,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 3d3cfe606..c0177ee1d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:58:50 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2570833934500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index a45391ada..6e759f59e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 2.570834 # Nu sim_ticks 2570833934500 # Number of ticks simulated final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63716 # Simulator instruction rate (inst/s) -host_op_rate 82290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2641493756 # Simulator tick rate (ticks/s) -host_mem_usage 388068 # Number of bytes of host memory used -host_seconds 973.25 # Real time elapsed on the host +host_inst_rate 53678 # Simulator instruction rate (inst/s) +host_op_rate 69325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2225327298 # Simulator tick rate (ticks/s) +host_mem_usage 390932 # Number of bytes of host memory used +host_seconds 1155.26 # Real time elapsed on the host sim_insts 62012062 # Number of instructions simulated sim_ops 80088895 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 131429540 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1199424 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10175696 # Number of bytes written to this memory -system.physmem.num_reads 15128117 # Number of read requests responded to by this memory -system.physmem.num_writes 868949 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51123310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 466551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3958130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55081440 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory +system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 130926 # number of replacements system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use system.l2c.total_refs 1855308 # Total number of references to valid blocks. @@ -211,12 +269,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000137 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.014302 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.052466 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849004 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836304 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784080 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607287 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.650892 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.552698 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000869 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.024345 # miss rate for demand accesses @@ -225,6 +287,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.demand_miss_rate::cpu1.itb.walker 0.000137 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.014302 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.240884 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000869 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.024345 # miss rate for overall accesses @@ -233,6 +296,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.overall_miss_rate::cpu1.itb.walker 0.000137 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.014302 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.240884 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109 # average ReadReq miss latency @@ -241,12 +305,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3478.081138 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6680.529301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2849.619289 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8968.333333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency @@ -255,6 +323,7 @@ system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency @@ -263,6 +332,7 @@ system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,12 +451,16 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052326 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.849004 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836304 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784080 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607287 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650892 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552698 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for demand accesses @@ -395,6 +469,7 @@ system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for overall accesses @@ -403,6 +478,7 @@ system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency @@ -411,12 +487,16 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency @@ -425,6 +505,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency @@ -433,16 +514,20 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -802,11 +887,17 @@ system.cpu0.icache.demand_accesses::total 3831829 # n system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked @@ -840,13 +931,21 @@ system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 232498 # number of replacements system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use @@ -906,17 +1005,29 @@ system.cpu0.dcache.demand_accesses::total 9184667 # n system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked @@ -968,20 +1079,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -1335,11 +1461,17 @@ system.cpu1.icache.demand_accesses::total 10441732 # n system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked @@ -1373,13 +1505,21 @@ system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 417022 # number of replacements system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use @@ -1439,17 +1579,29 @@ system.cpu1.dcache.demand_accesses::total 17145866 # n system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked @@ -1503,21 +1655,37 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -1538,7 +1706,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index e70ebd6c7..911c40f55 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -511,9 +512,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -572,10 +572,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -987,9 +986,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c9bc70145..c37c93eb0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:55:16 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2501685689500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 097a484ee..93f3afbea 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.501686 # Nu sim_ticks 2501685689500 # Number of ticks simulated final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62639 # Simulator instruction rate (inst/s) -host_op_rate 80877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2630163340 # Simulator tick rate (ticks/s) -host_mem_usage 384244 # Number of bytes of host memory used -host_seconds 951.15 # Real time elapsed on the host +host_inst_rate 57858 # Simulator instruction rate (inst/s) +host_op_rate 74704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2429415836 # Simulator tick rate (ticks/s) +host_mem_usage 387132 # Number of bytes of host memory used +host_seconds 1029.75 # Real time elapsed on the host sim_insts 59579009 # Number of instructions simulated sim_ops 76926775 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585736 # Number of bytes written to this memory -system.physmem.num_reads 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes 856669 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory +system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 119797 # number of replacements system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use system.l2c.total_refs 1834134 # Total number of references to valid blocks. @@ -139,32 +170,44 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -241,37 +284,52 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -631,11 +689,17 @@ system.cpu.icache.demand_accesses::total 13709800 # nu system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked @@ -669,13 +733,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 645895 # number of replacements system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use @@ -735,17 +807,29 @@ system.cpu.dcache.demand_accesses::total 25214634 # nu system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked @@ -797,20 +881,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -831,7 +930,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 7261617c5..a9da64c54 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 17:03:49 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 3dd4a07d4..bfc607b4f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,23 +4,48 @@ sim_seconds 5.157514 # Nu sim_ticks 5157514159500 # Number of ticks simulated final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128842 # Simulator instruction rate (inst/s) -host_op_rate 253899 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1558019011 # Simulator tick rate (ticks/s) -host_mem_usage 389972 # Number of bytes of host memory used -host_seconds 3310.30 # Real time elapsed on the host +host_inst_rate 123762 # Simulator instruction rate (inst/s) +host_op_rate 243888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1496586873 # Simulator tick rate (ticks/s) +host_mem_usage 369148 # Number of bytes of host memory used +host_seconds 3446.18 # Real time elapsed on the host sim_insts 426506235 # Number of instructions simulated sim_ops 840483958 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15959488 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1257664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 12050112 # Number of bytes written to this memory -system.physmem.num_reads 249367 # Number of read requests responded to by this memory -system.physmem.num_writes 188283 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3094415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 243851 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2336419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5430833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory +system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory +system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory +system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory +system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 167142 # number of replacements system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use system.l2c.total_refs 3843284 # Total number of references to valid blocks. @@ -122,30 +147,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52201.292100 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -213,33 +248,46 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000957 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.033076 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.025337 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.882394 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.882394 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.481904 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.481904 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.071838 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.071838 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47578 # number of replacements system.iocache.tagsinuse 0.166155 # Cycle average of tags in use @@ -275,13 +323,21 @@ system.iocache.demand_accesses::total 47633 # nu system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked @@ -309,13 +365,21 @@ system.iocache.demand_mshr_miss_latency::total 4010524860 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -635,11 +699,17 @@ system.cpu.icache.demand_accesses::total 9366799 # nu system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked @@ -669,11 +739,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 13093471492 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115814 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115814 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115814 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 10825 # number of replacements system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use @@ -713,11 +789,17 @@ system.cpu.itb_walker_cache.demand_accesses::total 39097 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39097 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 39097 # number of overall (read+write) accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298946 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298946 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298923 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.298923 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298923 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.298923 # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308 # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,11 +823,17 @@ system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.replacements 116553 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use @@ -781,11 +869,17 @@ system.cpu.dtb_walker_cache.demand_accesses::total 253531 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,11 +903,17 @@ system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1673290 # number of replacements system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use @@ -857,13 +957,21 @@ system.cpu.dcache.demand_accesses::total 21751990 # nu system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked @@ -905,16 +1013,27 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini index 78474a665..c9fc9d3a5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -995,7 +995,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1015,7 +1015,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1185,9 +1185,8 @@ zero=false port=system.piobus.master[0] [system.piobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index 5cc55eff8..f9683d0c4 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/21/2012 19:39:45 +Real time: Jun/04/2012 17:25:31 Profiler Stats -------------- -Elapsed_time_in_seconds: 1285 -Elapsed_time_in_minutes: 21.4167 -Elapsed_time_in_hours: 0.356944 -Elapsed_time_in_days: 0.0148727 +Elapsed_time_in_seconds: 842 +Elapsed_time_in_minutes: 14.0333 +Elapsed_time_in_hours: 0.233889 +Elapsed_time_in_days: 0.00974537 -Virtual_time_in_seconds: 1013.41 -Virtual_time_in_minutes: 16.8902 -Virtual_time_in_hours: 0.281503 -Virtual_time_in_days: 0.0117293 +Virtual_time_in_seconds: 842.03 +Virtual_time_in_minutes: 14.0338 +Virtual_time_in_hours: 0.233897 +Virtual_time_in_days: 0.00974572 Ruby_current_time: 10609379371 Ruby_start_time: 0 Ruby_cycles: 10609379371 -mbytes_resident: 269.652 -mbytes_total: 517.469 -resident_ratio: 0.521114 +mbytes_resident: 268.047 +mbytes_total: 470.199 +resident_ratio: 0.570071 ruby_cycles_executed: [ 10609379372 10609379372 ] @@ -123,13 +123,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 | Resource Usage -------------- page_size: 4096 -user_time: 1013 +user_time: 841 system_time: 0 -page_reclaims: 70791 -page_faults: 113 +page_reclaims: 69674 +page_faults: 18 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 16056 +block_outputs: 408 Network Stats ------------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index 4bb71c433..d6cb455f2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 21 2012 19:18:11 -gem5 started May 21 2012 19:18:20 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jun 4 2012 13:44:12 +gem5 started Jun 4 2012 17:11:29 +gem5 executing on zizzer command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5304689685500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index c2f297e1d..b7d143468 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,23 +4,74 @@ sim_seconds 5.304690 # Nu sim_ticks 5304689685500 # Number of ticks simulated final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106822 # Simulator instruction rate (inst/s) -host_op_rate 218222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4128199893 # Simulator tick rate (ticks/s) -host_mem_usage 529892 # Number of bytes of host memory used -host_seconds 1284.99 # Real time elapsed on the host +host_inst_rate 163049 # Simulator instruction rate (inst/s) +host_op_rate 333085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6301127704 # Simulator tick rate (ticks/s) +host_mem_usage 481488 # Number of bytes of host memory used +host_seconds 841.86 # Real time elapsed on the host sim_insts 137264752 # Number of instructions simulated sim_ops 280412254 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1392025556 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1298120352 # Number of instructions bytes read from this memory -system.physmem.bytes_written 70902832 # Number of bytes written to this memory -system.physmem.num_reads 178001662 # Number of read requests responded to by this memory -system.physmem.num_writes 9866514 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 262414135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 244711836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13366066 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 275780201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory +system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory +system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory +system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -44,7 +95,7 @@ system.cpu0.num_func_calls 0 # nu system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls system.cpu0.num_int_insts 168469813 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 517963582 # number of times the integer registers were read +system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written @@ -68,7 +119,7 @@ system.cpu1.num_func_calls 0 # nu system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls system.cpu1.num_int_insts 89110416 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 273178552 # number of times the integer registers were read +system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index acae3dcdb..1fcee5057 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -19,7 +19,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic -memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem2 system.rom system.physmem +memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2 num_work_ids=16 nvram=system.nvram nvram_addr=133429198848 @@ -140,9 +140,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=2 header_cycles=1 use_default_range=false @@ -151,10 +150,9 @@ master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake slave=system.bridge.master [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=2 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr index 179231b2e..61ba0c5bc 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting terminal connections +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. hack: be nice to actually delete the event here diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index 3dd47139a..483f7795e 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:49:20 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 15:02:47 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 714a7f4dc..80abd3d9c 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -4,67 +4,107 @@ sim_seconds 1.116889 # Nu sim_ticks 2233777512 # Number of ticks simulated final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 1707325 # Simulator instruction rate (inst/s) -host_op_rate 1707996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1711534 # Simulator tick rate (ticks/s) -host_mem_usage 511008 # Number of bytes of host memory used -host_seconds 1305.13 # Real time elapsed on the host +host_inst_rate 3140005 # Simulator instruction rate (inst/s) +host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3147745 # Simulator tick rate (ticks/s) +host_mem_usage 511524 # Number of bytes of host memory used +host_seconds 709.64 # Real time elapsed on the host sim_insts 2228284650 # Number of instructions simulated sim_ops 2229160714 # Number of ops (including micro ops) simulated -system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory -system.hypervisor_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.hypervisor_desc.bytes_written 0 # Number of bytes written to this memory -system.hypervisor_desc.num_reads 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.num_writes 0 # Number of write requests responded to by this memory -system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory -system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bytes_read 284 # Number of bytes read from this memory -system.nvram.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.nvram.bytes_written 92 # Number of bytes written to this memory -system.nvram.num_reads 284 # Number of read requests responded to by this memory -system.nvram.num_writes 92 # Number of write requests responded to by this memory -system.nvram.num_other 0 # Number of other requests responded to by this memory -system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bytes_read 4846 # Number of bytes read from this memory -system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.partition_desc.bytes_written 0 # Number of bytes written to this memory -system.partition_desc.num_reads 608 # Number of read requests responded to by this memory -system.partition_desc.num_writes 0 # Number of write requests responded to by this memory -system.partition_desc.num_other 0 # Number of other requests responded to by this memory -system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory -system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_written 897268422 # Number of bytes written to this memory -system.physmem2.num_reads 2403489130 # Number of read requests responded to by this memory -system.physmem2.num_writes 187387796 # Number of write requests responded to by this memory -system.physmem2.num_other 5403067 # Number of other requests responded to by this memory -system.physmem2.bw_read 8786901931 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read 7447569684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_write 803364182 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_total 9590266113 # Total bandwidth to/from this memory (bytes/s) -system.rom.bytes_read 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory -system.rom.bytes_written 0 # Number of bytes written to this memory -system.rom.num_reads 195123 # Number of read requests responded to by this memory -system.rom.num_writes 0 # Number of write requests responded to by this memory -system.rom.num_other 0 # Number of other requests responded to by this memory -system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 709825348 # Number of bytes read from this memory -system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory -system.physmem.bytes_written 15400223 # Number of bytes written to this memory -system.physmem.num_reads 165224885 # Number of read requests responded to by this memory -system.physmem.num_writes 1927067 # Number of write requests responded to by this memory -system.physmem.num_other 14 # Number of other requests responded to by this memory -system.physmem.bw_read 635538091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory +system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory +system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory +system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory +system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory +system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory +system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory +system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory +system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s) +system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory +system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory +system.rom.bytes_read::total 1128688 # Number of bytes read from this memory +system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory +system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory +system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory +system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory +system.rom.num_reads::total 195123 # Number of read requests responded to by this memory +system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory +system.nvram.bytes_read::total 284 # Number of bytes read from this memory +system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory +system.nvram.bytes_written::total 92 # Number of bytes written to this memory +system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory +system.nvram.num_reads::total 284 # Number of read requests responded to by this memory +system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory +system.nvram.num_writes::total 92 # Number of write requests responded to by this memory +system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory +system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory +system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory +system.physmem.num_other::total 14 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory +system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory +system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory +system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory +system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory +system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory +system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory +system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory +system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory +system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory +system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory +system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory +system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory +system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory +system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s) system.cpu.numCycles 2233777513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 37ea66e58..c1fb80fc3 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 4bff58d47..b4ecd43cf 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:43:43 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 7e649e9a6..e5597cd29 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.274300 # Nu sim_ticks 274300226500 # Number of ticks simulated final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71153 # Simulator instruction rate (inst/s) -host_op_rate 71153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32428333 # Simulator tick rate (ticks/s) -host_mem_usage 214868 # Number of bytes of host memory used -host_seconds 8458.66 # Real time elapsed on the host +host_inst_rate 112537 # Simulator instruction rate (inst/s) +host_op_rate 112537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51289289 # Simulator tick rate (ticks/s) +host_mem_usage 215256 # Number of bytes of host memory used +host_seconds 5348.10 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5894080 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3798144 # Number of bytes written to this memory -system.physmem.num_reads 92095 # Number of read requests responded to by this memory -system.physmem.num_writes 59346 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 21487696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35334364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory +system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory +system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -156,11 +169,17 @@ system.cpu.icache.demand_accesses::total 25020500 # nu system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,11 +207,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 45765000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use @@ -236,13 +261,21 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked @@ -278,13 +311,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73798 # number of replacements system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use @@ -346,18 +387,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 455395 system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.158457 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236350 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52310.393829 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52174.395765 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52221.678701 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52221.678701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked @@ -392,18 +441,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158457 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236350 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40008.338799 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40063.993941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index d7f68c19e..01ebbe1c7 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index 1f4384270..ef914e93c 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:45 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 0a8d681a5..aa861e979 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.134621 # Nu sim_ticks 134621123500 # Number of ticks simulated final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99995 # Simulator instruction rate (inst/s) -host_op_rate 99995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23802311 # Simulator tick rate (ticks/s) -host_mem_usage 215740 # Number of bytes of host memory used -host_seconds 5655.80 # Real time elapsed on the host +host_inst_rate 192359 # Simulator instruction rate (inst/s) +host_op_rate 192359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45788058 # Simulator tick rate (ticks/s) +host_mem_usage 216172 # Number of bytes of host memory used +host_seconds 2940.09 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5937600 # Number of bytes read from this memory -system.physmem.bytes_inst_read 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797952 # Number of bytes written to this memory -system.physmem.num_reads 92775 # Number of read requests responded to by this memory -system.physmem.num_writes 59343 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 44106005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 72318160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory +system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory +system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 66483943 # nu system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 35750000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 460743 # number of replacements system.cpu.dcache.tagsinuse 4093.783086 # Cycle average of tags in use @@ -446,15 +471,25 @@ system.cpu.dcache.demand_accesses::total 151114481 # nu system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006469 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032971 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015873 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013388 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013388 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15513.457453 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15513.457453 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked @@ -492,13 +527,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7699.484588 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74480 # number of replacements system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use @@ -560,18 +603,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 464839 system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151842 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.155864 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.235100 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.197430 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.199156 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.197430 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.199156 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34353.792415 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.888367 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.516471 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34540.434172 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34540.434172 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34489.695500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34489.695500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 339500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 49 # number of cycles access was blocked @@ -606,18 +657,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2868929500 system.cpu.l2cache.overall_mshr_miss_latency::total 2900132500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.199156 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199156 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31018.914898 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31392.467997 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 927f52249..352fd32f4 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr index 1b49765a7..1ed796979 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout index db142b8a8..a4781a82f 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:40 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:03:38 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 068e22070..7df2c8121 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.300931 # Nu sim_ticks 300930958000 # Number of ticks simulated final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2479447 # Simulator instruction rate (inst/s) -host_op_rate 2479447 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1239733454 # Simulator tick rate (ticks/s) -host_mem_usage 205680 # Number of bytes of host memory used -host_seconds 242.74 # Real time elapsed on the host +host_inst_rate 3871430 # Simulator instruction rate (inst/s) +host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1935730316 # Simulator tick rate (ticks/s) +host_mem_usage 206040 # Number of bytes of host memory used +host_seconds 155.46 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2782990928 # Number of bytes read from this memory -system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory -system.physmem.bytes_written 152669504 # Number of bytes written to this memory -system.physmem.num_reads 716375939 # Number of read requests responded to by this memory -system.physmem.num_writes 39451321 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 375543340 # Number of bytes read from this memory +system.physmem.bytes_read::total 2782990928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2407447588 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2407447588 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 152669504 # Number of bytes written to this memory +system.physmem.bytes_written::total 152669504 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 601861897 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 114514042 # Number of read requests responded to by this memory +system.physmem.num_reads::total 716375939 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 39451321 # Number of write requests responded to by this memory +system.physmem.num_writes::total 39451321 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1247938539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9247938286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 507324022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 507324022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 86520ac69..f4efff3d6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index 5a809a831..fcee7bced 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:36 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index fb6f85834..4082e04ad 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.765623 # Nu sim_ticks 765623032000 # Number of ticks simulated final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 835603 # Simulator instruction rate (inst/s) -host_op_rate 835603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1062971026 # Simulator tick rate (ticks/s) -host_mem_usage 214568 # Number of bytes of host memory used -host_seconds 720.27 # Real time elapsed on the host +host_inst_rate 1675799 # Simulator instruction rate (inst/s) +host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2131786057 # Simulator tick rate (ticks/s) +host_mem_usage 214908 # Number of bytes of host memory used +host_seconds 359.15 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5889984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797824 # Number of bytes written to this memory -system.physmem.num_reads 92031 # Number of read requests responded to by this memory -system.physmem.num_writes 59341 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory +system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory +system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 601861898 # nu system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42135000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use @@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73734 # number of replacements system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use @@ -286,18 +327,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 455395 system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.158207 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236340 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.201738 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.201738 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +381,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index d2c692362..c1e9b189c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 6445e3ddc..1edb7f5fa 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:58 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:27:39 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 54f7feb76..ed106fd55 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.164248 # Nu sim_ticks 164248292500 # Number of ticks simulated final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95192 # Simulator instruction rate (inst/s) -host_op_rate 100587 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27427613 # Simulator tick rate (ticks/s) -host_mem_usage 231504 # Number of bytes of host memory used -host_seconds 5988.43 # Real time elapsed on the host +host_inst_rate 143439 # Simulator instruction rate (inst/s) +host_op_rate 151568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41328806 # Simulator tick rate (ticks/s) +host_mem_usage 231960 # Number of bytes of host memory used +host_seconds 3974.18 # Real time elapsed on the host sim_insts 570052728 # Number of instructions simulated sim_ops 602360935 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5850432 # Number of bytes read from this memory -system.physmem.bytes_inst_read 51136 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3722112 # Number of bytes written to this memory -system.physmem.num_reads 91413 # Number of read requests responded to by this memory -system.physmem.num_writes 58158 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 35619439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 311334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 22661496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 58280935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 51136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5799296 # Number of bytes read from this memory +system.physmem.bytes_read::total 5850432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3722112 # Number of bytes written to this memory +system.physmem.bytes_written::total 3722112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 799 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90614 # Number of read requests responded to by this memory +system.physmem.num_reads::total 91413 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58158 # Number of write requests responded to by this memory +system.physmem.num_writes::total 58158 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 311334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35308105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 35619439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 311334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 311334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 22661496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 22661496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 22661496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 311334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35308105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58280935 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -368,11 +381,17 @@ system.cpu.icache.demand_accesses::total 67495318 # nu system.cpu.icache.overall_accesses::cpu.inst 67495318 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 67495318 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34196.692776 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34196.692776 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34196.692776 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34196.692776 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,11 +419,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 28616000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28616000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 28616000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34107.270560 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34107.270560 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 440506 # number of replacements system.cpu.dcache.tagsinuse 4094.673413 # Cycle average of tags in use @@ -460,15 +485,25 @@ system.cpu.dcache.demand_accesses::total 201731606 # nu system.cpu.dcache.overall_accesses::cpu.data 201731606 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 201731606 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001884 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022587 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022587 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.009379 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.009379 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009008 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009008 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009008 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009008 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13208.806613 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13208.806613 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17259.271740 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17259.271740 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12687.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12687.500000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16703.549355 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16703.549355 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9569014 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked @@ -506,13 +541,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4172571513 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4172571513 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4172571513 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8257.093815 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8257.093815 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10286.222787 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10286.222787 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73212 # number of replacements system.cpu.l2cache.tagsinuse 17814.608666 # Cycle average of tags in use @@ -583,19 +626,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 444603 system.cpu.l2cache.overall_accesses::total 445439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.956938 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163582 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.166926 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.333333 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235994 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.235994 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956938 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.203829 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.205242 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956938 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.203829 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.205242 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.875000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34299.124002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34299.915423 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34319.932438 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34319.932438 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34312.683898 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34312.683898 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2005000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 332 # number of cycles access was blocked @@ -643,20 +695,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2825195000 system.cpu.l2cache.overall_mshr_miss_latency::total 2850070000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163537 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166876 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235994 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235994 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.205220 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.205220 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31132.665832 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31085.271078 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.415277 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31229.898657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31229.898657 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index 98278be8c..c0d4f8993 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index aa43ef922..3264273f7 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:21:51 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:27:49 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index b23b7f871..ab951a1c0 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1201570 # Simulator instruction rate (inst/s) -host_op_rate 1269670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 634859326 # Simulator tick rate (ticks/s) -host_mem_usage 220780 # Number of bytes of host memory used -host_seconds 474.42 # Real time elapsed on the host +host_inst_rate 2291609 # Simulator instruction rate (inst/s) +host_op_rate 2421488 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1210789798 # Simulator tick rate (ticks/s) +host_mem_usage 221260 # Number of bytes of host memory used +host_seconds 248.76 # Real time elapsed on the host sim_insts 570051644 # Number of instructions simulated sim_ops 602359851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2680160157 # Number of bytes read from this memory -system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory -system.physmem.bytes_written 236359611 # Number of bytes written to this memory -system.physmem.num_reads 717867713 # Number of read requests responded to by this memory -system.physmem.num_writes 69418858 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8898529055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7570927866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 784748949 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9683278004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2280298136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 399862021 # Number of bytes read from this memory +system.physmem.bytes_read::total 2680160157 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2280298136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2280298136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory +system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 570074534 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147793179 # Number of read requests responded to by this memory +system.physmem.num_reads::total 717867713 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory +system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7570927866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1327601189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8898529055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7570927866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7570927866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 784748949 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 784748949 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7570927866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2112350138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9683278004 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 8ba39dd31..81852cb71 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index ec5b6e605..dd5e622ba 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:22:17 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:27:51 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index dd6b444c4..44a2387d1 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 606714 # Simulator instruction rate (inst/s) -host_op_rate 640712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 850261270 # Simulator tick rate (ticks/s) -host_mem_usage 229976 # Number of bytes of host memory used -host_seconds 937.08 # Real time elapsed on the host +host_inst_rate 1154549 # Simulator instruction rate (inst/s) +host_op_rate 1219245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618008338 # Simulator tick rate (ticks/s) +host_mem_usage 230404 # Number of bytes of host memory used +host_seconds 492.43 # Real time elapsed on the host sim_insts 568539343 # Number of instructions simulated sim_ops 600398281 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5759488 # Number of bytes read from this memory -system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3704704 # Number of bytes written to this memory -system.physmem.num_reads 89992 # Number of read requests responded to by this memory -system.physmem.num_writes 57886 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7228609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 49480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4649694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11878304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5720064 # Number of bytes read from this memory +system.physmem.bytes_read::total 5759488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3704704 # Number of bytes written to this memory +system.physmem.bytes_written::total 3704704 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 89376 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89992 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57886 # Number of write requests responded to by this memory +system.physmem.num_writes::total 57886 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 49480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 7179129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7228609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4649694 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4649694 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4649694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 7179129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11878304 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 570074535 # nu system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54236.391913 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54236.391913 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54236.391913 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32945000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51236.391913 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 217209383 # nu system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20842.679226 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23909.028529 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22578.841038 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22578.841038 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17842.679226 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20909.028529 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71804 # number of replacements system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 437564 system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.165605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.235929 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.205364 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.205364 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165605 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235929 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.205364 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.205364 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 98314f012..6dd839e0e 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 3d27114e4..b261460cd 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:17 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:35 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 3819069b9..042ffd7cf 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.388554 # Nu sim_ticks 388554296500 # Number of ticks simulated final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119684 # Simulator instruction rate (inst/s) -host_op_rate 120061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33188741 # Simulator tick rate (ticks/s) -host_mem_usage 223864 # Number of bytes of host memory used -host_seconds 11707.41 # Real time elapsed on the host +host_inst_rate 160259 # Simulator instruction rate (inst/s) +host_op_rate 160764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44440455 # Simulator tick rate (ticks/s) +host_mem_usage 224388 # Number of bytes of host memory used +host_seconds 8743.26 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5987456 # Number of bytes read from this memory -system.physmem.bytes_inst_read 85056 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3788160 # Number of bytes written to this memory -system.physmem.num_reads 93554 # Number of read requests responded to by this memory -system.physmem.num_writes 59190 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15409574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 218904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 9749371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 25158945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 85056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5902400 # Number of bytes read from this memory +system.physmem.bytes_read::total 5987456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 85056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 85056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3788160 # Number of bytes written to this memory +system.physmem.bytes_written::total 3788160 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1329 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 92225 # Number of read requests responded to by this memory +system.physmem.num_reads::total 93554 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59190 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59190 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 218904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15190670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15409574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 218904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 218904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9749371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9749371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9749371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 218904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15190670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 25158945 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 777108594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -324,11 +337,17 @@ system.cpu.icache.demand_accesses::total 162823525 # nu system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34024.544534 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34024.544534 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34024.544534 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,11 +375,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 47023000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34780.325444 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 458031 # number of replacements system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use @@ -412,15 +437,25 @@ system.cpu.dcache.demand_accesses::total 368453310 # nu system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003985 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011224 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007263 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007263 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.703875 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15844.705290 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 38142.857143 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15529.487014 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15529.487014 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -460,15 +495,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7769.265376 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13747.043644 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 35142.857143 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 75325 # number of replacements system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use @@ -533,18 +578,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 462127 system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982988 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.160796 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.166316 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.229160 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.229160 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982988 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34037.511942 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34411.294082 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34277.465421 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34277.465421 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -579,18 +632,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166316 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.229160 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.403630 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31318.658630 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 5860d36d4..47913c070 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout index 86dd2db54..bf7412ed2 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:18 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:41 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index a7bbf2f2d..ed36e3ce0 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.744764 # Nu sim_ticks 744764119000 # Number of ticks simulated final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1723625 # Simulator instruction rate (inst/s) -host_op_rate 1728749 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 864377228 # Simulator tick rate (ticks/s) -host_mem_usage 213676 # Number of bytes of host memory used -host_seconds 861.62 # Real time elapsed on the host +host_inst_rate 3186892 # Simulator instruction rate (inst/s) +host_op_rate 3196366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1598188492 # Simulator tick rate (ticks/s) +host_mem_usage 214172 # Number of bytes of host memory used +host_seconds 466.01 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 7326269637 # Number of bytes read from this memory -system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory -system.physmem.bytes_written 614672063 # Number of bytes written to this memory -system.physmem.num_reads 1887625855 # Number of read requests responded to by this memory -system.physmem.num_writes 166846816 # Number of write requests responded to by this memory -system.physmem.num_other 1326 # Number of other requests responded to by this memory -system.physmem.bw_read 9837033566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7976286575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 825324485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10662358051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 5940452044 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1385817593 # Number of bytes read from this memory +system.physmem.bytes_read::total 7326269637 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5940452044 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5940452044 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory +system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1485113011 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 402512844 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1887625855 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory +system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory +system.physmem.num_other::total 1326 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1860746990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9837033566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 825324485 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 825324485 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2686071475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10662358051 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 1489528239 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index 8e4dd6b01..577b4c1d7 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index 0309c0267..4517a277e 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:22 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:45 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 327f1f99e..0ce23ef70 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.064259 # Nu sim_ticks 2064258667000 # Number of ticks simulated final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 667477 # Simulator instruction rate (inst/s) -host_op_rate 669461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 927773801 # Simulator tick rate (ticks/s) -host_mem_usage 222564 # Number of bytes of host memory used -host_seconds 2224.96 # Real time elapsed on the host +host_inst_rate 1371910 # Simulator instruction rate (inst/s) +host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1906915769 # Simulator tick rate (ticks/s) +host_mem_usage 223048 # Number of bytes of host memory used +host_seconds 1082.51 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5909952 # Number of bytes read from this memory -system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3778240 # Number of bytes written to this memory -system.physmem.num_reads 92343 # Number of read requests responded to by this memory -system.physmem.num_writes 59035 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2862990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 4693303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory +system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory +system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 4128517334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1485113012 # nu system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 58503000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use @@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 569359660 # nu system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74112 # number of replacements system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use @@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 453221 system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 7b2a9ad59..5eab9f73c 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:07:25 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 639bcc189..26e1be238 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.636988 # Nu sim_ticks 636988382500 # Number of ticks simulated final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71818 # Simulator instruction rate (inst/s) -host_op_rate 132329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51984066 # Simulator tick rate (ticks/s) -host_mem_usage 250428 # Number of bytes of host memory used -host_seconds 12253.53 # Real time elapsed on the host +host_inst_rate 63436 # Simulator instruction rate (inst/s) +host_op_rate 116883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45916521 # Simulator tick rate (ticks/s) +host_mem_usage 227532 # Number of bytes of host memory used +host_seconds 13872.75 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5834048 # Number of bytes read from this memory -system.physmem.bytes_inst_read 59200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3731712 # Number of bytes written to this memory -system.physmem.num_reads 91157 # Number of read requests responded to by this memory -system.physmem.num_writes 58308 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9158798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 92937 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5858367 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 15017166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 59200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5774848 # Number of bytes read from this memory +system.physmem.bytes_read::total 5834048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 59200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 59200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3731712 # Number of bytes written to this memory +system.physmem.bytes_written::total 3731712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90232 # Number of read requests responded to by this memory +system.physmem.num_reads::total 91157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58308 # Number of write requests responded to by this memory +system.physmem.num_writes::total 58308 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 9065861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9158798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5858367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5858367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5858367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 9065861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15017166 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1273976766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -322,11 +335,17 @@ system.cpu.icache.demand_accesses::total 186830267 # nu system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33672.202166 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33672.202166 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33672.202166 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,11 +373,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32805000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35085.561497 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35085.561497 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 445407 # number of replacements system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use @@ -402,13 +427,21 @@ system.cpu.dcache.demand_accesses::total 453124365 # nu system.cpu.dcache.overall_accesses::cpu.data 453124365 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 453124365 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10393.162559 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13094.918510 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11861.789165 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11861.789165 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,13 +477,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3996172000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3996172000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7432.029905 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7432.029905 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10094.012234 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 72883 # number of replacements system.cpu.l2cache.tagsinuse 17779.692577 # Cycle average of tags in use @@ -519,18 +560,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 449505 system.cpu.l2cache.overall_accesses::total 450433 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996767 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.156964 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.160780 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236882 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236882 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996767 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200736 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.202376 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996767 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200736 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.202376 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.378378 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34292.077967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.692045 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34267.939507 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34267.939507 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34276.495497 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34276.495497 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -565,18 +614,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000 system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.160780 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236882 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.202376 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202376 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.268608 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.660140 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 87bcc8171..db4607fa4 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:08:17 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 14740711a..0e02ab2e6 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.963993 # Nu sim_ticks 963992704000 # Number of ticks simulated final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 688761 # Simulator instruction rate (inst/s) -host_op_rate 1269079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 754478822 # Simulator tick rate (ticks/s) -host_mem_usage 239576 # Number of bytes of host memory used -host_seconds 1277.69 # Real time elapsed on the host +host_inst_rate 1254577 # Simulator instruction rate (inst/s) +host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1374282564 # Simulator tick rate (ticks/s) +host_mem_usage 216676 # Number of bytes of host memory used +host_seconds 701.45 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11334586825 # Number of bytes read from this memory -system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory -system.physmem.bytes_written 864451000 # Number of bytes written to this memory -system.physmem.num_reads 1605558864 # Number of read requests responded to by this memory -system.physmem.num_writes 188186057 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11757959140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 9846686466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 896740189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12654699330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory +system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory +system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory +system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1927985409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 9ebad8844..7f0dbded6 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:13:02 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 4294088ef..00ab9a331 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 1.803259 # Nu sim_ticks 1803258587000 # Number of ticks simulated final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 617600 # Simulator instruction rate (inst/s) -host_op_rate 1137962 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1265523884 # Simulator tick rate (ticks/s) -host_mem_usage 248496 # Number of bytes of host memory used -host_seconds 1424.91 # Real time elapsed on the host +host_inst_rate 587265 # Simulator instruction rate (inst/s) +host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1203364849 # Simulator tick rate (ticks/s) +host_mem_usage 225604 # Number of bytes of host memory used +host_seconds 1498.51 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5725952 # Number of bytes read from this memory -system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3712448 # Number of bytes written to this memory -system.physmem.num_reads 89468 # Number of read requests responded to by this memory -system.physmem.num_writes 58007 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3175336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 25625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2058744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5234080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory +system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory +system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory +system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 3606517174 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1186516740 # nu system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 38266000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 607228182 # nu system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20490.305383 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23997.572756 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22431.962140 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22431.962140 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17490.305383 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20997.572756 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71208 # number of replacements system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use @@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 442048 system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.157613 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.238037 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.202064 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.202064 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.157613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238037 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.202064 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 3ea467c54..dcc46b583 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 97b90c338..60efd00ac 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:22:28 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:32:09 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0a1029305..90f8077ba 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.025989 # Nu sim_ticks 25988864000 # Number of ticks simulated final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71403 # Simulator instruction rate (inst/s) -host_op_rate 71915 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20482160 # Simulator tick rate (ticks/s) -host_mem_usage 364344 # Number of bytes of host memory used -host_seconds 1268.85 # Real time elapsed on the host +host_inst_rate 141606 # Simulator instruction rate (inst/s) +host_op_rate 142623 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40620332 # Simulator tick rate (ticks/s) +host_mem_usage 364696 # Number of bytes of host memory used +host_seconds 639.80 # Real time elapsed on the host sim_insts 90599356 # Number of instructions simulated sim_ops 91249910 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 999040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2048 # Number of bytes written to this memory -system.physmem.num_reads 15610 # Number of read requests responded to by this memory -system.physmem.num_writes 32 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 38441080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1775530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 78803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 38519883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 46144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 952896 # Number of bytes read from this memory +system.physmem.bytes_read::total 999040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory +system.physmem.bytes_written::total 2048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14889 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15610 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory +system.physmem.num_writes::total 32 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1775530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36665550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38441080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1775530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1775530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1775530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36665550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 38519883 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total 14156722 # nu system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34868.827160 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34868.827160 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34868.827160 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 25625000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34212.283044 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 943602 # number of replacements system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use @@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total 29605337 # nu system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040373 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037182 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001355 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039863 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039863 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5760.542992 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26197.875726 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16125 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8809.367484 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8809.367484 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked @@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036356 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009190 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032011 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032011 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2656.699127 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2656.699127 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24753.157217 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 770 # number of replacements system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use @@ -578,18 +621,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 947698 system.cpu.l2cache.overall_accesses::total 948447 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963952 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000403 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001202 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.325962 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.325962 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963952 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015720 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016469 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963952 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015720 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016469 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34279.005525 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34352.380625 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34347.279129 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34347.279129 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -633,18 +684,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001190 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.325962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 0dc5ea994..394878465 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index 863d389ca..6025dc422 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:24:24 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:36:14 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 6150ebd1b..cb9066ccb 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.054241 # Nu sim_ticks 54240666000 # Number of ticks simulated final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1203852 # Simulator instruction rate (inst/s) -host_op_rate 1212496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 720706000 # Simulator tick rate (ticks/s) -host_mem_usage 353596 # Number of bytes of host memory used -host_seconds 75.26 # Real time elapsed on the host +host_inst_rate 2223712 # Simulator instruction rate (inst/s) +host_op_rate 2239678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1331261387 # Simulator tick rate (ticks/s) +host_mem_usage 354056 # Number of bytes of host memory used +host_seconds 40.74 # Real time elapsed on the host sim_insts 90602415 # Number of instructions simulated sim_ops 91252969 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 521339715 # Number of bytes read from this memory -system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory -system.physmem.bytes_written 18908138 # Number of bytes written to this memory -system.physmem.num_reads 130384074 # Number of read requests responded to by this memory -system.physmem.num_writes 4738868 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9611602391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7952024704 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 348597084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9960199475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 431323116 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 90016599 # Number of bytes read from this memory +system.physmem.bytes_read::total 521339715 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 431323116 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 431323116 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory +system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 107830779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22553295 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130384074 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7952024704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1659577687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9611602391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7952024704 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7952024704 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 348597084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 348597084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7952024704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2008174771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9960199475 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 98847a36c..227acc83b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 10d881c1d..b972e2aeb 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:24:48 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:37:05 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index d20615e1d..dd28872f6 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.148086 # Nu sim_ticks 148086239000 # Number of ticks simulated final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 549790 # Simulator instruction rate (inst/s) -host_op_rate 553732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 898863423 # Simulator tick rate (ticks/s) -host_mem_usage 362780 # Number of bytes of host memory used -host_seconds 164.75 # Real time elapsed on the host +host_inst_rate 1056603 # Simulator instruction rate (inst/s) +host_op_rate 1064179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1727464138 # Simulator tick rate (ticks/s) +host_mem_usage 363220 # Number of bytes of host memory used +host_seconds 85.72 # Real time elapsed on the host sim_insts 90576869 # Number of instructions simulated sim_ops 91226321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 986112 # Number of bytes read from this memory -system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2048 # Number of bytes written to this memory -system.physmem.num_reads 15408 # Number of read requests responded to by this memory -system.physmem.num_writes 32 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 6659039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 249800 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 6672869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 949120 # Number of bytes read from this memory +system.physmem.bytes_read::total 986112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory +system.physmem.bytes_written::total 2048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14830 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15408 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory +system.physmem.num_writes::total 32 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 249800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6409238 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6659039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 249800 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 249800 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 13830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 13830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 249800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6409238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6672869 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 107830780 # nu system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54527.545910 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54527.545910 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 30865000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 27284389 # nu system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14013.157237 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14657.859438 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14657.859438 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11013.157237 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 634 # number of replacements system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 946798 system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016264 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016264 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000955 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index addbca3ec..a0039b696 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout index 70118299e..c071d26fa 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:24 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:53:37 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index f04b9260d..804f585d6 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.122216 # Nu sim_ticks 122215830000 # Number of ticks simulated final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1503519 # Simulator instruction rate (inst/s) -host_op_rate 1503581 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 753629165 # Simulator tick rate (ticks/s) -host_mem_usage 346024 # Number of bytes of host memory used -host_seconds 162.17 # Real time elapsed on the host +host_inst_rate 2951739 # Simulator instruction rate (inst/s) +host_op_rate 2951861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1479540198 # Simulator tick rate (ticks/s) +host_mem_usage 346528 # Number of bytes of host memory used +host_seconds 82.60 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1306360053 # Number of bytes read from this memory -system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory -system.physmem.bytes_written 91606089 # Number of bytes written to this memory -system.physmem.num_reads 326641945 # Number of read requests responded to by this memory -system.physmem.num_writes 22901951 # Number of write requests responded to by this memory -system.physmem.num_other 3886 # Number of other requests responded to by this memory -system.physmem.bw_read 10688959466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 749543566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11438503032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 977686044 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 328674009 # Number of bytes read from this memory +system.physmem.bytes_read::total 1306360053 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 977686044 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977686044 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory +system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 244421511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82220434 # Number of read requests responded to by this memory +system.physmem.num_reads::total 326641945 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory +system.physmem.num_other::total 3886 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2689291633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10688959466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 749543566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 749543566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3438835198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11438503032 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 244431661 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index 861290241..e29268380 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 4ee289cc3..2436d9105 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:44:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:55:10 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 300c74bea..9186661e0 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.362431 # Nu sim_ticks 362430887000 # Number of ticks simulated final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 628265 # Simulator instruction rate (inst/s) -host_op_rate 628291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 933876298 # Simulator tick rate (ticks/s) -host_mem_usage 354916 # Number of bytes of host memory used -host_seconds 388.09 # Real time elapsed on the host +host_inst_rate 1267775 # Simulator instruction rate (inst/s) +host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1884467398 # Simulator tick rate (ticks/s) +host_mem_usage 355400 # Number of bytes of host memory used +host_seconds 192.33 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1001472 # Number of bytes read from this memory -system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2560 # Number of bytes written to this memory -system.physmem.num_reads 15648 # Number of read requests responded to by this memory -system.physmem.num_writes 40 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory +system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory +system.physmem.bytes_written::total 2560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory +system.physmem.num_writes::total 40 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 724861774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 244421512 # nu system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 46620000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use @@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 105122385 # nu system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 865 # number of replacements system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use @@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 939571 system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 7dd036543..5c8d95ce9 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:14:48 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 2d4c91c54..a6e1946c5 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.067388 # Nu sim_ticks 67388458000 # Number of ticks simulated final_tick 67388458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74550 # Simulator instruction rate (inst/s) -host_op_rate 131270 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31798513 # Simulator tick rate (ticks/s) -host_mem_usage 385908 # Number of bytes of host memory used -host_seconds 2119.23 # Real time elapsed on the host +host_inst_rate 84988 # Simulator instruction rate (inst/s) +host_op_rate 149650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36250631 # Simulator tick rate (ticks/s) +host_mem_usage 363056 # Number of bytes of host memory used +host_seconds 1858.96 # Real time elapsed on the host sim_insts 157988582 # Number of instructions simulated sim_ops 278192519 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 3907520 # Number of bytes read from this memory -system.physmem.bytes_inst_read 69248 # Number of instructions bytes read from this memory -system.physmem.bytes_written 897536 # Number of bytes written to this memory -system.physmem.num_reads 61055 # Number of read requests responded to by this memory -system.physmem.num_writes 14024 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 57985004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1027594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13318839 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 71303843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 69248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3838272 # Number of bytes read from this memory +system.physmem.bytes_read::total 3907520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 897536 # Number of bytes written to this memory +system.physmem.bytes_written::total 897536 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 59973 # Number of read requests responded to by this memory +system.physmem.num_reads::total 61055 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 14024 # Number of write requests responded to by this memory +system.physmem.num_writes::total 14024 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1027594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56957410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 57985004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1027594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1027594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 13318839 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13318839 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 13318839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1027594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56957410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 71303843 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 134776917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -323,11 +336,17 @@ system.cpu.icache.demand_accesses::total 27278821 # nu system.cpu.icache.overall_accesses::cpu.inst 27278821 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 27278821 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35528.308563 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35528.308563 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35528.308563 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35528.308563 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,11 +374,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 38330500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38330500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 38330500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34909.380692 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34909.380692 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2072128 # number of replacements system.cpu.dcache.tagsinuse 4072.706371 # Cycle average of tags in use @@ -403,13 +428,21 @@ system.cpu.dcache.demand_accesses::total 78000448 # nu system.cpu.dcache.overall_accesses::cpu.data 78000448 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 78000448 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049205 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049205 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002736 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002736 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.030475 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.030475 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.030475 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.030475 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6031.763813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6031.763813 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17468.488873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17468.488873 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 6445.578990 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 6445.578990 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,13 +478,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6755035291 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6755035291 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6755035291 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026618 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026618 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2806.348172 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2806.348172 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14114.884540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14114.884540 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 33429 # number of replacements system.cpu.l2cache.tagsinuse 18994.164700 # Cycle average of tags in use @@ -522,19 +563,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 2076226 system.cpu.l2cache.overall_accesses::total 2077320 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989031 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015273 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015807 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358999 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358999 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989031 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.028886 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.029391 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989031 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.028886 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.029391 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.491682 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34158.052865 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34162.047753 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.473271 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.473271 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34125.026615 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34125.026615 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,20 +623,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1859866500 system.cpu.l2cache.overall_mshr_miss_latency::total 1893481500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015807 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358999 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358999 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029391 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029391 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31022.212005 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.574700 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 8772b21f0..9f1b85cdf 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:20:09 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 09f40044d..75d2c32b9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.168950 # Nu sim_ticks 168950072000 # Number of ticks simulated final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 563497 # Simulator instruction rate (inst/s) -host_op_rate 992227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 602592819 # Simulator tick rate (ticks/s) -host_mem_usage 374808 # Number of bytes of host memory used -host_seconds 280.37 # Real time elapsed on the host +host_inst_rate 1244063 # Simulator instruction rate (inst/s) +host_op_rate 2190595 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1330377575 # Simulator tick rate (ticks/s) +host_mem_usage 351912 # Number of bytes of host memory used +host_seconds 126.99 # Real time elapsed on the host sim_insts 157988583 # Number of instructions simulated sim_ops 278192520 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2458815679 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 243173115 # Number of bytes written to this memory -system.physmem.num_reads 308475658 # Number of read requests responded to by this memory -system.physmem.num_writes 31439751 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 14553504772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 10308191310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1439319393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 15992824164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1741569664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 717246015 # Number of bytes read from this memory +system.physmem.bytes_read::total 2458815679 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1741569664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1741569664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory +system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 217696208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90779450 # Number of read requests responded to by this memory +system.physmem.num_reads::total 308475658 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory +system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10308191310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4245313462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14553504772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10308191310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10308191310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1439319393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1439319393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10308191310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5684632854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15992824164 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 337900145 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 3e731c17d..d95343c19 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:22:27 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 093a41c03..bcdb996d9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.370011 # Nu sim_ticks 370010840000 # Number of ticks simulated final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376379 # Simulator instruction rate (inst/s) -host_op_rate 662743 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 881483751 # Simulator tick rate (ticks/s) -host_mem_usage 383736 # Number of bytes of host memory used -host_seconds 419.76 # Real time elapsed on the host +host_inst_rate 564351 # Simulator instruction rate (inst/s) +host_op_rate 993732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1321716509 # Simulator tick rate (ticks/s) +host_mem_usage 360832 # Number of bytes of host memory used +host_seconds 279.95 # Real time elapsed on the host sim_insts 157988583 # Number of instructions simulated sim_ops 278192520 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 4900800 # Number of bytes read from this memory -system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1885440 # Number of bytes written to this memory -system.physmem.num_reads 76575 # Number of read requests responded to by this memory -system.physmem.num_writes 29460 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4849088 # Number of bytes read from this memory +system.physmem.bytes_read::total 4900800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 1885440 # Number of bytes written to this memory +system.physmem.bytes_written::total 1885440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 75767 # Number of read requests responded to by this memory +system.physmem.num_reads::total 76575 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 29460 # Number of write requests responded to by this memory +system.physmem.num_writes::total 29460 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 139758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13105259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13245017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 139758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 139758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5095634 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5095634 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5095634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 139758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13105259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18340652 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 740021680 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 217696209 # nu system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42824000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 122219201 # nu system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15539.675029 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15539.675029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 49212 # number of replacements system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use @@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2066829 system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.017393 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.400136 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.037035 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.037035 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.694804 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.385243 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.385243 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017393 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.400136 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.037035 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.037035 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 08e7e2cb5..52f83ef58 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 5e99fb7a2..90b73e8ee 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:25:50 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:38:42 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 233090215000 because target called exit() +Exiting @ tick 233057542500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 8dc91f46c..b64f135f3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.233058 # Nu sim_ticks 233057542500 # Number of ticks simulated final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104599 # Simulator instruction rate (inst/s) -host_op_rate 117832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47897344 # Simulator tick rate (ticks/s) -host_mem_usage 237516 # Number of bytes of host memory used -host_seconds 4865.77 # Real time elapsed on the host +host_inst_rate 102553 # Simulator instruction rate (inst/s) +host_op_rate 115527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46960535 # Simulator tick rate (ticks/s) +host_mem_usage 237172 # Number of bytes of host memory used +host_seconds 4962.84 # Real time elapsed on the host sim_insts 508954936 # Number of instructions simulated sim_ops 573341497 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15214144 # Number of bytes read from this memory -system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10947904 # Number of bytes written to this memory -system.physmem.num_reads 237721 # Number of read requests responded to by this memory -system.physmem.num_writes 171061 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 246208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14967936 # Number of bytes read from this memory +system.physmem.bytes_read::total 15214144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 246208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 246208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10947904 # Number of bytes written to this memory +system.physmem.bytes_written::total 10947904 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3847 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 233874 # Number of read requests responded to by this memory +system.physmem.num_reads::total 237721 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 171061 # Number of write requests responded to by this memory +system.physmem.num_writes::total 171061 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1056426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 64224208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 65280633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1056426 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1056426 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46975111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46975111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46975111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1056426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64224208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 112255745 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -368,11 +381,17 @@ system.cpu.icache.demand_accesses::total 126860220 # nu system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000157 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000157 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000157 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13468.126288 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13468.126288 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,11 +421,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 171640500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000143 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000143 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000143 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9466.164792 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1204809 # number of replacements system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use @@ -462,15 +487,25 @@ system.cpu.dcache.demand_accesses::total 195622115 # nu system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009328 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026850 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000035 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014186 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014186 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14576.321503 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14576.321503 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,13 +543,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006138 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006292 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006181 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006181 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7154.602287 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12837.889185 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 218501 # number of replacements system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use @@ -587,20 +630,30 @@ system.cpu.l2cache.overall_accesses::cpu.data 1208896 system.cpu.l2cache.overall_accesses::total 1226913 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213798 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143718 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.145145 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.230769 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319698 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.319698 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213798 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.193480 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.193778 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213798 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.193480 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.193778 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34200.768309 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6212.121212 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6212.121212 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34242.649952 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34220.019853 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34220.019853 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -648,20 +701,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000 system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.145114 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.319698 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.193756 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.193756 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31038.310611 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 6e34c6137..f2f9dd654 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 61ef97f09..5bc6f404c 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:27:44 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:42:59 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 4ec8704b3..eec1b9eb1 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.290499 # Nu sim_ticks 290498972000 # Number of ticks simulated final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1142576 # Simulator instruction rate (inst/s) -host_op_rate 1287798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 655209825 # Simulator tick rate (ticks/s) -host_mem_usage 224168 # Number of bytes of host memory used -host_seconds 443.37 # Real time elapsed on the host +host_inst_rate 2223848 # Simulator instruction rate (inst/s) +host_op_rate 2506499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1275264214 # Simulator tick rate (ticks/s) +host_mem_usage 224628 # Number of bytes of host memory used +host_seconds 227.80 # Real time elapsed on the host sim_insts 506581615 # Number of instructions simulated sim_ops 570968176 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2489298238 # Number of bytes read from this memory -system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory -system.physmem.bytes_written 216067624 # Number of bytes written to this memory -system.physmem.num_reads 641840242 # Number of read requests responded to by this memory -system.physmem.num_writes 55727847 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8569043191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7113434935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 743781028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9312824219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2066445536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 422852702 # Number of bytes read from this memory +system.physmem.bytes_read::total 2489298238 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2066445536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2066445536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory +system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 516611384 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125228858 # Number of read requests responded to by this memory +system.physmem.num_reads::total 641840242 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory +system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7113434935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1455608256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8569043191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7113434935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7113434935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 743781028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 743781028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7113434935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2199389284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9312824219 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 77531d0fb..036427da7 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 22208540d..ec9ed9cd5 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:29:57 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:46:58 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 8678fa0ad..85dc67786 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.722234 # Nu sim_ticks 722234364000 # Number of ticks simulated final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 593765 # Simulator instruction rate (inst/s) -host_op_rate 669073 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 849204818 # Simulator tick rate (ticks/s) -host_mem_usage 233356 # Number of bytes of host memory used -host_seconds 850.48 # Real time elapsed on the host +host_inst_rate 1114772 # Simulator instruction rate (inst/s) +host_op_rate 1256160 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1594352181 # Simulator tick rate (ticks/s) +host_mem_usage 233804 # Number of bytes of host memory used +host_seconds 453.00 # Real time elapsed on the host sim_insts 504986861 # Number of instructions simulated sim_ops 569034848 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 14797056 # Number of bytes read from this memory -system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory -system.physmem.bytes_written 11027328 # Number of bytes written to this memory -system.physmem.num_reads 231204 # Number of read requests responded to by this memory -system.physmem.num_writes 172302 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 188608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14608448 # Number of bytes read from this memory +system.physmem.bytes_read::total 14797056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 188608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 188608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 11027328 # Number of bytes written to this memory +system.physmem.bytes_written::total 11027328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2947 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228257 # Number of read requests responded to by this memory +system.physmem.num_reads::total 231204 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 172302 # Number of write requests responded to by this memory +system.physmem.num_writes::total 172302 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 261145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 20226742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20487887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 261145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 261145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15268351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15268351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15268351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 261145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 20226742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35756238 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 516611385 # nu system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24743.338252 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24743.338252 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24743.338252 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 250505000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21743.338252 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 177979623 # nu system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.762778 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28150.625947 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22417.457622 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22417.457622 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16807.762778 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25150.625947 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 212089 # number of replacements system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1138918 system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.139985 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.336920 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.200970 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.200970 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.139985 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.336920 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.200970 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.200970 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index e360d8cc6..29af0d223 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:27:18 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1dc4deb54..4a5cfadf8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.459938 # Nu sim_ticks 459937575500 # Number of ticks simulated final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75971 # Simulator instruction rate (inst/s) -host_op_rate 140479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42257715 # Simulator tick rate (ticks/s) -host_mem_usage 287264 # Number of bytes of host memory used -host_seconds 10884.11 # Real time elapsed on the host +host_inst_rate 70939 # Simulator instruction rate (inst/s) +host_op_rate 131174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39458742 # Simulator tick rate (ticks/s) +host_mem_usage 264492 # Number of bytes of host memory used +host_seconds 11656.16 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37483008 # Number of bytes read from this memory -system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26316864 # Number of bytes written to this memory -system.physmem.num_reads 585672 # Number of read requests responded to by this memory -system.physmem.num_writes 411201 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory +system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory +system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory +system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 919875152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -323,11 +336,17 @@ system.cpu.icache.demand_accesses::total 183482871 # nu system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,11 +376,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 915847000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2527239 # number of replacements system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use @@ -405,13 +430,21 @@ system.cpu.dcache.demand_accesses::total 418117752 # nu system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,13 +480,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 574865 # number of replacements system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use @@ -526,20 +567,30 @@ system.cpu.l2cache.overall_accesses::cpu.data 2531251 system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,20 +629,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 5153e8f50..337e5053a 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:38:11 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 38deb4a58..a8445ed5c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.885229 # Nu sim_ticks 885229360000 # Number of ticks simulated final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 648787 # Simulator instruction rate (inst/s) -host_op_rate 1199679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 694571010 # Simulator tick rate (ticks/s) -host_mem_usage 243520 # Number of bytes of host memory used -host_seconds 1274.50 # Real time elapsed on the host +host_inst_rate 1285236 # Simulator instruction rate (inst/s) +host_op_rate 2376545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1375933868 # Simulator tick rate (ticks/s) +host_mem_usage 220604 # Number of bytes of host memory used +host_seconds 643.37 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 10832432532 # Number of bytes read from this memory -system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory -system.physmem.bytes_written 991849460 # Number of bytes written to this memory -system.physmem.num_reads 1452449298 # Number of read requests responded to by this memory -system.physmem.num_writes 149160201 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 12236865406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 9654872803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1120443475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13357308881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 8546776872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285655660 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832432532 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8546776872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8546776872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory +system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068347109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384102189 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452449298 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9654872803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581992604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12236865406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9654872803 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9654872803 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1120443475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1120443475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9654872803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3702436078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13357308881 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 1770458721 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index c9e0b30c1..1909314a2 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:45:58 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index c48e15266..b3396b2cb 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 1.658730 # Nu sim_ticks 1658729604000 # Number of ticks simulated final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 478704 # Simulator instruction rate (inst/s) -host_op_rate 885178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 960288988 # Simulator tick rate (ticks/s) -host_mem_usage 252496 # Number of bytes of host memory used -host_seconds 1727.32 # Real time elapsed on the host +host_inst_rate 615589 # Simulator instruction rate (inst/s) +host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1234881669 # Simulator tick rate (ticks/s) +host_mem_usage 229524 # Number of bytes of host memory used +host_seconds 1343.23 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37094976 # Number of bytes read from this memory -system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26349376 # Number of bytes written to this memory -system.physmem.num_reads 579609 # Number of read requests responded to by this memory -system.physmem.num_writes 411709 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory +system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory +system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory +system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 3317459208 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1068347110 # nu system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 128436000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 533262390 # nu system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 568906 # number of replacements system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use @@ -257,18 +298,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2518458 system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,18 +352,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index ad08e6373..673c743ff 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index 56d057ebd..051061431 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:58 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 28e031d9f..06e2fa444 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.141175 # Nu sim_ticks 141175129500 # Number of ticks simulated final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60144 # Simulator instruction rate (inst/s) -host_op_rate 60144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21298240 # Simulator tick rate (ticks/s) -host_mem_usage 221000 # Number of bytes of host memory used -host_seconds 6628.49 # Real time elapsed on the host +host_inst_rate 110841 # Simulator instruction rate (inst/s) +host_op_rate 110841 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39251086 # Simulator tick rate (ticks/s) +host_mem_usage 221340 # Number of bytes of host memory used +host_seconds 3596.72 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 468992 # Number of bytes read from this memory -system.physmem.bytes_inst_read 214592 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7328 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3322058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1520041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3322058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory +system.physmem.bytes_read::total 468992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1520041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1802017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3322058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1520041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1520041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1520041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1802017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3322058 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -155,11 +162,17 @@ system.cpu.icache.demand_accesses::total 49111849 # nu system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48928.995434 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48928.995434 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48928.995434 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,11 +200,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 185222000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185222000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 185222000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47480.645988 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use @@ -235,13 +254,21 @@ system.cpu.dcache.demand_accesses::total 168275218 # nu system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000164 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52139.705882 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52068.406365 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52068.406365 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -277,13 +304,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 215717000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215717000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 215717000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48610.526316 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3896.685167 # Cycle average of tags in use @@ -348,18 +383,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 4152 system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.862830 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.909971 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.909971 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.232608 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52405.977074 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52405.977074 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,18 +435,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862830 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909971 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909971 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.501076 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index bf1407a6b..7162e6c66 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 54524760f..0c5d1935a 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:12 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:46:44 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 891e3f52e..55fb5b70f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.080257 # Nu sim_ticks 80257421500 # Number of ticks simulated final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93963 # Simulator instruction rate (inst/s) -host_op_rate 93963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20079187 # Simulator tick rate (ticks/s) -host_mem_usage 221872 # Number of bytes of host memory used -host_seconds 3997.05 # Real time elapsed on the host +host_inst_rate 183656 # Simulator instruction rate (inst/s) +host_op_rate 183656 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39245952 # Simulator tick rate (ticks/s) +host_mem_usage 222148 # Number of bytes of host memory used +host_seconds 2044.99 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 478528 # Number of bytes read from this memory -system.physmem.bytes_inst_read 222720 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7477 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 5962414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2775070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 5962414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory +system.physmem.bytes_read::total 478528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222720 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3480 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7477 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2775070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3187344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5962414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2775070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2775070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2775070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3187344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5962414 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -357,11 +364,17 @@ system.cpu.icache.demand_accesses::total 52487109 # nu system.cpu.icache.overall_accesses::cpu.inst 52487109 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 52487109 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31012.199434 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31012.199434 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31012.199434 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31012.199434 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,11 +402,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 125153000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125153000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 125153000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30055.955812 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30055.955812 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 30055.955812 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30055.955812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 804 # number of replacements system.cpu.dcache.tagsinuse 3297.800145 # Cycle average of tags in use @@ -441,13 +460,21 @@ system.cpu.dcache.demand_accesses::total 161830750 # nu system.cpu.dcache.overall_accesses::cpu.data 161830750 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 161830750 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000131 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000131 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33167.850799 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33167.850799 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29072.241300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29072.241300 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29398.537736 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29398.537736 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -483,13 +510,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 144878500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144878500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 144878500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31659.521436 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31659.521436 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35329.169269 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35329.169269 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34453.864447 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34453.864447 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 11 # number of replacements system.cpu.l2cache.tagsinuse 4039.301940 # Cycle average of tags in use @@ -554,18 +589,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 4205 system.cpu.l2cache.overall_accesses::total 8369 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.835735 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867398 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.841881 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.976577 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.976577 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.835735 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.950535 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.893416 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.835735 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.950535 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.893416 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34383.045977 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34584.482759 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34423.333333 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34647.105852 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34647.105852 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34516.918550 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34383.045977 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34633.475106 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34516.918550 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -598,18 +641,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125810000 system.cpu.l2cache.overall_mshr_miss_latency::total 234231000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867398 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.841881 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976577 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.976577 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.893416 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.893416 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31155.459770 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31425.287356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31209.425287 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31490.246242 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31490.246242 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31326.869065 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31326.869065 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini index dc447cd7b..4442b5ed2 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr index 860580eeb..28eb1122e 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout index 57f8a5318..ba8d40ed9 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:06 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:23:04 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 290084525..695830448 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1838180 # Simulator instruction rate (inst/s) -host_op_rate 1838179 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 919090070 # Simulator tick rate (ticks/s) -host_mem_usage 211568 # Number of bytes of host memory used -host_seconds 216.88 # Real time elapsed on the host +host_inst_rate 3372014 # Simulator instruction rate (inst/s) +host_op_rate 3372014 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1686007461 # Simulator tick rate (ticks/s) +host_mem_usage 211928 # Number of bytes of host memory used +host_seconds 118.23 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2257107875 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_written 492356798 # Number of bytes written to this memory -system.physmem.num_reads 493419140 # Number of read requests responded to by this memory -system.physmem.num_writes 73520729 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11323336020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13793364824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory +system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory +system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory +system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory +system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index 998e07c81..b05b7d5ce 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index 8e7f3829a..39e268f04 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:47:31 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 852f5134d..f16fecb77 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.567343 # Nu sim_ticks 567343170000 # Number of ticks simulated final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 766770 # Simulator instruction rate (inst/s) -host_op_rate 766770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1091197730 # Simulator tick rate (ticks/s) -host_mem_usage 220456 # Number of bytes of host memory used -host_seconds 519.93 # Real time elapsed on the host +host_inst_rate 1377504 # Simulator instruction rate (inst/s) +host_op_rate 1377504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1960338494 # Simulator tick rate (ticks/s) +host_mem_usage 220796 # Number of bytes of host memory used +host_seconds 289.41 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 459520 # Number of bytes read from this memory -system.physmem.bytes_inst_read 205120 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7180 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 809951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 361545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 809951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory +system.physmem.bytes_read::total 459520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7180 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 448406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 448406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809951 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 398664666 # nu system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50648.516199 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50648.516199 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50648.516199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 175013000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 168275220 # nu system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50827.368421 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54209.537572 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54209.537572 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,13 +244,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 212622000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47827.368421 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use @@ -288,18 +323,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 4152 system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.873459 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.917572 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.917572 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +375,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.873459 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.917572 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.917572 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 1cf41a172..b166901dc 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index f0a5e284e..fd4ba336e 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:35:18 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:54:41 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 969b86901..154ddb0a7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.071775 # Nu sim_ticks 71774859500 # Number of ticks simulated final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69606 # Simulator instruction rate (inst/s) -host_op_rate 88987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18296996 # Simulator tick rate (ticks/s) -host_mem_usage 240272 # Number of bytes of host memory used -host_seconds 3922.77 # Real time elapsed on the host +host_inst_rate 120484 # Simulator instruction rate (inst/s) +host_op_rate 154032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31671128 # Simulator tick rate (ticks/s) +host_mem_usage 240520 # Number of bytes of host memory used +host_seconds 2266.26 # Real time elapsed on the host sim_insts 273048474 # Number of instructions simulated sim_ops 349076199 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 472896 # Number of bytes read from this memory -system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7389 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 199168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273728 # Number of bytes read from this memory +system.physmem.bytes_read::total 472896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 199168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 199168 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4277 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7389 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2774899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3813703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6588602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2774899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2774899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2774899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3813703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6588602 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -368,11 +375,17 @@ system.cpu.icache.demand_accesses::total 39951299 # nu system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000426 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000426 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12404.519807 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12404.519807 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,11 +413,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 139714000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8670.348765 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1427 # number of replacements system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use @@ -460,15 +479,25 @@ system.cpu.dcache.demand_accesses::total 172497310 # nu system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000040 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000238 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000143 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33118.913777 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33118.913777 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -506,13 +535,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 156453500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30396.733112 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35546.727336 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 69 # number of replacements system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use @@ -581,19 +618,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 4641 system.cpu.l2cache.overall_accesses::total 20733 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.194009 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834903 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.258647 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994006 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994006 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359234 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359234 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34292.611795 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34476.055339 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34362.043502 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34362.043502 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,20 +685,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994006 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31162.253829 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31290.528556 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 72280076c..796e4e4fa 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 51d5089a3..80d4c141d 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:37:41 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:01:26 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 30e59a4c3..1239fc01a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.212344 # Nu sim_ticks 212344048000 # Number of ticks simulated final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 841557 # Simulator instruction rate (inst/s) -host_op_rate 1075889 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 654486612 # Simulator tick rate (ticks/s) -host_mem_usage 228648 # Number of bytes of host memory used -host_seconds 324.44 # Real time elapsed on the host +host_inst_rate 1586428 # Simulator instruction rate (inst/s) +host_op_rate 2028172 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1233780581 # Simulator tick rate (ticks/s) +host_mem_usage 229108 # Number of bytes of host memory used +host_seconds 172.11 # Real time elapsed on the host sim_insts 273037671 # Number of instructions simulated sim_ops 349065408 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1875350709 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1394641440 # Number of instructions bytes read from this memory -system.physmem.bytes_written 400047783 # Number of bytes written to this memory -system.physmem.num_reads 443242866 # Number of read requests responded to by this memory -system.physmem.num_writes 82063572 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8831661291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6567838624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1883960425 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10715621716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1394641440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 480709269 # Number of bytes read from this memory +system.physmem.bytes_read::total 1875350709 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory +system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 348660360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 94582506 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443242866 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6567838624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2263822667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8831661291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6567838624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6567838624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1883960425 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1883960425 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6567838624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4147783092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10715621716 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 28132d5a1..f88d3c19b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 85721b4bd..02e894db6 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:38:02 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:04:29 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 1725766a3..ce6e736cb 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.525854 # Nu sim_ticks 525854475000 # Number of ticks simulated final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 425859 # Simulator instruction rate (inst/s) -host_op_rate 544445 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 821076045 # Simulator tick rate (ticks/s) -host_mem_usage 237820 # Number of bytes of host memory used -host_seconds 640.45 # Real time elapsed on the host +host_inst_rate 697015 # Simulator instruction rate (inst/s) +host_op_rate 891108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1343878935 # Simulator tick rate (ticks/s) +host_mem_usage 238268 # Number of bytes of host memory used +host_seconds 391.30 # Real time elapsed on the host sim_insts 272739291 # Number of instructions simulated sim_ops 348687131 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 437312 # Number of bytes read from this memory -system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 6833 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 831622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 317654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 831622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 167040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory +system.physmem.bytes_read::total 437312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6833 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 317654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 831622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 317654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 317654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 831622 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total 348660359 # nu system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21025.572005 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21025.572005 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21025.572005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 281253000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18025.572005 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use @@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total 176624288 # nu system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49749.688667 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55766.016713 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53608.307280 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53608.307280 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,13 +262,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 226624000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 48 # number of replacements system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use @@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 4478 system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.231100 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.340272 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.340272 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231100 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.340272 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.340272 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 16e2e58d3..c3e480ad3 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index f9974abd8..9147626b9 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:24:16 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 936c3a0e4..b1e9e0d80 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.645508 # Nu sim_ticks 645508416000 # Number of ticks simulated final_tick 645508416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101635 # Simulator instruction rate (inst/s) -host_op_rate 101635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35987047 # Simulator tick rate (ticks/s) -host_mem_usage 222212 # Number of bytes of host memory used -host_seconds 17937.24 # Real time elapsed on the host +host_inst_rate 137005 # Simulator instruction rate (inst/s) +host_op_rate 137005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48511232 # Simulator tick rate (ticks/s) +host_mem_usage 222596 # Number of bytes of host memory used +host_seconds 13306.37 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94795136 # Number of bytes read from this memory -system.physmem.bytes_inst_read 192384 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4281472 # Number of bytes written to this memory -system.physmem.num_reads 1481174 # Number of read requests responded to by this memory -system.physmem.num_writes 66898 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 146853447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 298035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6632713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 153486160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 192384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94602752 # Number of bytes read from this memory +system.physmem.bytes_read::total 94795136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 192384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 192384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory +system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1478168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1481174 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 298035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146555412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146853447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 298035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 298035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6632713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6632713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6632713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 298035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146555412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 153486160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 402604817 # nu system.cpu.icache.overall_accesses::cpu.inst 402604817 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 402604817 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16625.867453 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16625.867453 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16625.867453 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16625.867453 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 123488000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123488000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 123488000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12139.992135 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12139.992135 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1528059 # number of replacements system.cpu.dcache.tagsinuse 4095.059846 # Cycle average of tags in use @@ -446,15 +471,25 @@ system.cpu.dcache.demand_accesses::total 669730731 # nu system.cpu.dcache.overall_accesses::cpu.data 669730731 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 669730731 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002618 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002618 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.040000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.040000 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003704 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003704 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003704 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003704 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37072.672706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37072.672706 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.941679 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.941679 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37240.290883 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37240.290883 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 99000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 23000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked @@ -496,15 +531,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 52483443500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52483443500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 52483443500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.020000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.020000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34227.205505 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34227.205505 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34815.073180 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34815.073180 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34254.679034 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34254.679034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480784 # number of replacements system.cpu.l2cache.tagsinuse 31940.343129 # Cycle average of tags in use @@ -569,18 +614,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1532155 system.cpu.l2cache.overall_accesses::total 1542327 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.295517 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966291 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.961652 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933607 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933607 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.295517 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964764 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.960350 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.295517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964764 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.960350 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34318.196939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.522573 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34338.479372 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35134.764398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 35134.764398 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34318.196939 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34374.532529 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34374.418198 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34318.196939 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34374.532529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34374.418198 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 40500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -615,18 +668,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45899201500 system.cpu.l2cache.overall_mshr_miss_latency::total 45992673500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966291 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.961652 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933607 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933607 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.960350 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.960350 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31095.143047 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.637348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31000.838210 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32123.320868 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32123.320868 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31051.499351 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31051.499351 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index eadae54f6..aa91216e8 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr index ca52b457d..1c6544a2e 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 3888b9787..073913775 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:09 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:31:15 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 271502b93..8a7012f1d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 1.004711 # Nu sim_ticks 1004710587000 # Number of ticks simulated final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2020056 # Simulator instruction rate (inst/s) -host_op_rate 2020056 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1010246097 # Simulator tick rate (ticks/s) -host_mem_usage 211516 # Number of bytes of host memory used -host_seconds 994.52 # Real time elapsed on the host +host_inst_rate 3539563 # Simulator instruction rate (inst/s) +host_op_rate 3539563 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1770163280 # Simulator tick rate (ticks/s) +host_mem_usage 211940 # Number of bytes of host memory used +host_seconds 567.58 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11607100996 # Number of bytes read from this memory -system.physmem.bytes_inst_read 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1586125963 # Number of bytes written to this memory -system.physmem.num_reads 2520491096 # Number of read requests responded to by this memory -system.physmem.num_writes 210794896 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11552681087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13131370496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3569416716 # Number of bytes read from this memory +system.physmem.bytes_read::total 11607100996 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8037684280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8037684280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1586125963 # Number of bytes written to this memory +system.physmem.bytes_written::total 1586125963 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2009421070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 511070026 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2520491096 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 210794896 # Number of write requests responded to by this memory +system.physmem.num_writes::total 210794896 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3552681501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11552681087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1578689409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1578689409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 4f0c26637..f9460f41a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index c1dffe98f..508096573 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:40:02 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index df33397d8..c273e38a0 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.813468 # Nu sim_ticks 2813467842000 # Number of ticks simulated final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 748813 # Simulator instruction rate (inst/s) -host_op_rate 748813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1048668721 # Simulator tick rate (ticks/s) -host_mem_usage 220468 # Number of bytes of host memory used -host_seconds 2682.89 # Real time elapsed on the host +host_inst_rate 1483350 # Simulator instruction rate (inst/s) +host_op_rate 1483350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2077343480 # Simulator tick rate (ticks/s) +host_mem_usage 220820 # Number of bytes of host memory used +host_seconds 1354.36 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94708160 # Number of bytes read from this memory -system.physmem.bytes_inst_read 152128 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4281472 # Number of bytes written to this memory -system.physmem.num_reads 1479815 # Number of read requests responded to by this memory -system.physmem.num_writes 66898 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 33662428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 54071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1521777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35184206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94556032 # Number of bytes read from this memory +system.physmem.bytes_read::total 94708160 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 152128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 152128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory +system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2377 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1477438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479815 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33608357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33662428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1521777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1521777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1521777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33608357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35184206 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 2009421071 # nu system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23421.857305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23421.857305 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23421.857305 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 216390000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use @@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 721864922 # nu system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54628.209454 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54628.209454 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.273516 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54553.304787 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54553.304787 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 78883980000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78883980000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 78883980000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51628.209454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51628.209454 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51553.304787 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51553.304787 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1479797 # number of replacements system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use @@ -289,18 +330,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1530144 system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.967338 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.961978 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.965555 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.960457 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.965555 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.960457 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,18 +384,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59097520000 system.cpu.l2cache.overall_mshr_miss_latency::total 59192600000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.967338 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.961978 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.960457 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.960457 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 046ea4974..d9870188c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 5fdff30e2..0c5c10637 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:38:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:06:13 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 25a59d0b1..81f1da57a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.735495 # Nu sim_ticks 735495062500 # Number of ticks simulated final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70506 # Simulator instruction rate (inst/s) -host_op_rate 96019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37458496 # Simulator tick rate (ticks/s) -host_mem_usage 237496 # Number of bytes of host memory used -host_seconds 19634.93 # Real time elapsed on the host +host_inst_rate 76677 # Simulator instruction rate (inst/s) +host_op_rate 104424 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40737062 # Simulator tick rate (ticks/s) +host_mem_usage 237976 # Number of bytes of host memory used +host_seconds 18054.69 # Real time elapsed on the host sim_insts 1384379503 # Number of instructions simulated sim_ops 1885334256 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94839680 # Number of bytes read from this memory -system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1481870 # Number of read requests responded to by this memory -system.physmem.num_writes 66099 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 128946726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 290895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5751685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 134698411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 213952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94625728 # Number of bytes read from this memory +system.physmem.bytes_read::total 94839680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 213952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 213952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1478527 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1481870 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 290895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 128655830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128946726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 290895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 290895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5751685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5751685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5751685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 290895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 128655830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134698411 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total 414743940 # nu system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8807.319007 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8807.319007 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8807.319007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 192601000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5391.512471 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1532415 # number of replacements system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use @@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total 1036122172 # nu system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003120 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002965 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000228 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003078 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003078 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33834.598445 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34793.690065 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38166.666667 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34081.493121 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34081.493121 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001928 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34178.105737 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32230.114990 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480284 # number of replacements system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use @@ -584,19 +627,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 1536511 system.cpu.l2cache.overall_accesses::total 1567287 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108786 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964935 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.947305 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999394 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999394 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908791 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.908791 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108786 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.962278 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.945519 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108786 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.962278 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.945519 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.972521 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.089470 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34306.025346 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.322034 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.322034 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34296.139278 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34296.139278 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,20 +696,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947286 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999394 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908791 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.945500 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.945500 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31068.809993 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.680993 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 3c449c83d..73b2ffcd2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index d0a53e63c..1893c8b1d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:43:17 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:11:11 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index de6626577..56b9fe676 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.945613 # Nu sim_ticks 945613131000 # Number of ticks simulated final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 910891 # Simulator instruction rate (inst/s) -host_op_rate 1240507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 622191267 # Simulator tick rate (ticks/s) -host_mem_usage 225796 # Number of bytes of host memory used -host_seconds 1519.81 # Real time elapsed on the host +host_inst_rate 1814541 # Simulator instruction rate (inst/s) +host_op_rate 2471154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1239437075 # Simulator tick rate (ticks/s) +host_mem_usage 226248 # Number of bytes of host memory used +host_seconds 762.94 # Real time elapsed on the host sim_insts 1384381614 # Number of instructions simulated sim_ops 1885336367 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8025491315 # Number of bytes read from this memory -system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1123958396 # Number of bytes written to this memory -system.physmem.num_reads 2010616909 # Number of read requests responded to by this memory -system.physmem.num_writes 276945663 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8487076852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 5880931491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1188602780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9675679632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 5561086040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2464405275 # Number of bytes read from this memory +system.physmem.bytes_read::total 8025491315 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5561086040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5561086040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory +system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1390271510 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 620345399 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2010616909 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory +system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5880931491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606145361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8487076852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5880931491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5880931491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188602780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1188602780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5880931491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3794748141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9675679632 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 68de052dd..1dd9a3ff2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index d3e913037..579afd945 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:43:48 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:24:05 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 6675fca21..4610b3f7b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.369902 # Nu sim_ticks 2369901960000 # Number of ticks simulated final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 495417 # Simulator instruction rate (inst/s) -host_op_rate 672068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 849801430 # Simulator tick rate (ticks/s) -host_mem_usage 234976 # Number of bytes of host memory used -host_seconds 2788.77 # Real time elapsed on the host +host_inst_rate 768078 # Simulator instruction rate (inst/s) +host_op_rate 1041952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1317503901 # Simulator tick rate (ticks/s) +host_mem_usage 235416 # Number of bytes of host memory used +host_seconds 1798.78 # Real time elapsed on the host sim_insts 1381604347 # Number of instructions simulated sim_ops 1874244950 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94696320 # Number of bytes read from this memory -system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1479630 # Number of read requests responded to by this memory -system.physmem.num_writes 66099 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 39957906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 41742932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94551872 # Number of bytes read from this memory +system.physmem.bytes_read::total 94696320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1477373 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479630 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 60951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39896955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39957906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1785026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1785026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1785026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39896955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41742932 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 1390271511 # nu system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18786.850477 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18786.850477 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18786.850477 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 312627000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312627000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 312627000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15786.850477 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 897271092 # nu system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54574.204602 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54458.738711 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54458.738711 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51574.204602 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1478755 # number of replacements system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1533653 system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.954657 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963303 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.952476 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.952476 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59094920000 system.cpu.l2cache.overall_mshr_miss_latency::total 59185200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.954657 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.952476 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.952476 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 558bb295e..738c09057 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 32687c68b..91ee744be 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:25:13 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index bbfd1b81d..0593fb6f2 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.047233 # Nu sim_ticks 47232621500 # Number of ticks simulated final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62283 # Simulator instruction rate (inst/s) -host_op_rate 62283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33300358 # Simulator tick rate (ticks/s) -host_mem_usage 223148 # Number of bytes of host memory used -host_seconds 1418.38 # Real time elapsed on the host +host_inst_rate 102058 # Simulator instruction rate (inst/s) +host_op_rate 102058 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54566702 # Simulator tick rate (ticks/s) +host_mem_usage 223484 # Number of bytes of host memory used +host_seconds 865.59 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11167232 # Number of bytes read from this memory -system.physmem.bytes_inst_read 602240 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7713024 # Number of bytes written to this memory -system.physmem.num_reads 174488 # Number of read requests responded to by this memory -system.physmem.num_writes 120516 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 236430493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 12750510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 163298664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 399729158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 602240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10564992 # Number of bytes read from this memory +system.physmem.bytes_read::total 11167232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 602240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 602240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7713024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7713024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165078 # Number of read requests responded to by this memory +system.physmem.num_reads::total 174488 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120516 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 12750510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 223679984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 236430493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 12750510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 12750510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163298664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163298664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163298664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 12750510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 223679984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 399729158 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -156,11 +169,17 @@ system.cpu.icache.demand_accesses::total 12477840 # nu system.cpu.icache.overall_accesses::cpu.inst 12477840 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 12477840 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009478 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009478 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.009478 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009478 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009478 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17668.535383 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17668.535383 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17668.535383 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,11 +207,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 1366128500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15638.633866 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements system.cpu.dcache.tagsinuse 4073.126583 # Cycle average of tags in use @@ -236,13 +261,21 @@ system.cpu.dcache.demand_accesses::total 34890015 # nu system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004744 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43236.445110 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43236.445110 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52900.510754 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52900.510754 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51683.893332 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51683.893332 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,13 +311,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9343358000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343358000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9343358000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34375.170734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34375.170734 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.713888 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50525.713888 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 148111 # number of replacements system.cpu.l2cache.tagsinuse 18671.690365 # Cycle average of tags in use @@ -349,18 +390,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 204347 system.cpu.l2cache.overall_accesses::total 291703 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107720 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554303 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.290591 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.914655 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107720 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.807832 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598170 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107720 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.807832 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598170 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.184910 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52204.508905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52222.387643 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.547529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52124.547529 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52148.652056 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52148.652056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,18 +444,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606216500 system.cpu.l2cache.overall_mshr_miss_latency::total 6983345000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554303 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.290591 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.914655 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.598170 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.598170 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.948823 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40020.931559 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index e450ba18e..51735fdde 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 9cfde6f31..331fe5e75 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:40:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:07:55 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 451be5b16..f6437b65f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.021303 # Nu sim_ticks 21302882000 # Number of ticks simulated final_tick 21302882000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93477 # Simulator instruction rate (inst/s) -host_op_rate 93477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25019246 # Simulator tick rate (ticks/s) -host_mem_usage 224368 # Number of bytes of host memory used -host_seconds 851.46 # Real time elapsed on the host +host_inst_rate 166406 # Simulator instruction rate (inst/s) +host_op_rate 166406 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44538843 # Simulator tick rate (ticks/s) +host_mem_usage 224724 # Number of bytes of host memory used +host_seconds 478.30 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11250368 # Number of bytes read from this memory -system.physmem.bytes_inst_read 658624 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7713792 # Number of bytes written to this memory -system.physmem.num_reads 175787 # Number of read requests responded to by this memory -system.physmem.num_writes 120528 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 528114834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 30917131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 362100865 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 890215699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 658624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10591744 # Number of bytes read from this memory +system.physmem.bytes_read::total 11250368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 658624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 658624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7713792 # Number of bytes written to this memory +system.physmem.bytes_written::total 7713792 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165496 # Number of read requests responded to by this memory +system.physmem.num_reads::total 175787 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120528 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120528 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 30917131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 497197703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 528114834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 30917131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 30917131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 362100865 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 362100865 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 362100865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 30917131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 497197703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 890215699 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 14242802 # nu system.cpu.icache.overall_accesses::cpu.inst 14242802 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 14242802 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007146 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007146 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.007146 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007146 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.007146 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007146 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9476.533640 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 9476.533640 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 9476.533640 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 9476.533640 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 566036000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 566036000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 566036000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006805 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006805 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006805 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5839.757346 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5839.757346 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5839.757346 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5839.757346 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 201683 # number of replacements system.cpu.dcache.tagsinuse 4076.258401 # Cycle average of tags in use @@ -442,13 +467,21 @@ system.cpu.dcache.demand_accesses::total 35702699 # nu system.cpu.dcache.overall_accesses::cpu.data 35702699 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 35702699 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012223 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012223 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070840 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070840 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.036216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036216 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036216 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32116.383223 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.383223 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32865.120027 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32865.120027 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32715.845767 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32715.845767 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 96500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked @@ -484,13 +517,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6017733500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6017733500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6017733500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002957 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005764 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005764 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20560.343860 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20560.343860 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33018.486627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33018.486627 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29243.671609 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29243.671609 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 149461 # number of replacements system.cpu.l2cache.tagsinuse 18973.137542 # Cycle average of tags in use @@ -555,18 +596,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 205779 system.cpu.l2cache.overall_accesses::total 302707 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.106172 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.546932 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278702 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.916086 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.916086 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.106172 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.804241 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.580717 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.106172 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.804241 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.580717 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.425615 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34445.218335 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34416.287452 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34438.666788 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34438.666788 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.425615 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.016677 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34433.015524 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.425615 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.016677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34433.015524 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -601,18 +650,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176426000 system.cpu.l2cache.overall_mshr_miss_latency::total 5496333000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.546932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278702 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916086 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.916086 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.580717 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.580717 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31086.094646 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.147658 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31046.958774 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.343410 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31341.343410 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31267.004955 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31267.004955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index a0b57617c..06c6ef199 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr index 1b49765a7..1ed796979 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout index fc113b45a..dd92eb188 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:30:37 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index d588d935b..4ae9b05ab 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2035147 # Simulator instruction rate (inst/s) -host_op_rate 2035146 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1018739452 # Simulator tick rate (ticks/s) -host_mem_usage 213644 # Number of bytes of host memory used -host_seconds 43.41 # Real time elapsed on the host +host_inst_rate 3187268 # Simulator instruction rate (inst/s) +host_op_rate 3187266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1595460185 # Simulator tick rate (ticks/s) +host_mem_usage 214012 # Number of bytes of host memory used +host_seconds 27.72 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 480454939 # Number of bytes read from this memory -system.physmem.bytes_inst_read 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_written 91652896 # Number of bytes written to this memory -system.physmem.num_reads 108714711 # Number of read requests responded to by this memory -system.physmem.num_writes 14613377 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10864858470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12937468537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory +system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory +system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory +system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory +system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 7a34ec0b9..92307a506 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout index 10d7a3f16..8571fc6fb 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:21:00 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 106052dbf..026fc581b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.134277 # Nu sim_ticks 134276988000 # Number of ticks simulated final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 721996 # Simulator instruction rate (inst/s) -host_op_rate 721996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1097426166 # Simulator tick rate (ticks/s) -host_mem_usage 222532 # Number of bytes of host memory used -host_seconds 122.36 # Real time elapsed on the host +host_inst_rate 1431789 # Simulator instruction rate (inst/s) +host_op_rate 1431788 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2176303972 # Simulator tick rate (ticks/s) +host_mem_usage 222880 # Number of bytes of host memory used +host_seconds 61.70 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11121920 # Number of bytes read from this memory -system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7712384 # Number of bytes written to this memory -system.physmem.num_reads 173780 # Number of read requests responded to by this memory -system.physmem.num_writes 120506 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 82828191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4157615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 57436379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 140264570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 558272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10563648 # Number of bytes read from this memory +system.physmem.bytes_read::total 11121920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 558272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 558272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7712384 # Number of bytes written to this memory +system.physmem.bytes_written::total 7712384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8723 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165057 # Number of read requests responded to by this memory +system.physmem.num_reads::total 173780 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120506 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120506 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 4157615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 78670576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 82828191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4157615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4157615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 57436379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 57436379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 57436379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4157615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 78670576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 140264570 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 88438074 # nu system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18793.107960 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18793.107960 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18793.107960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 1207162000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1207162000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 1207162000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15793.107960 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use @@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 34890015 # nu system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37208.307277 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52460.753040 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47925.116470 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47925.116470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9180178000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9180178000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9180178000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34208.307277 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49460.753040 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 147405 # number of replacements system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use @@ -289,18 +330,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 204344 system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.308312 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.915732 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.618919 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.618919 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,18 +384,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308312 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.915732 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.915732 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.618919 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.618919 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 9b36bf976..566c57286 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index f9f6b3025..cb33c4c0f 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:44:00 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:32:39 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index d1da91b90..826f949e8 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.024561 # Nu sim_ticks 24560764000 # Number of ticks simulated final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54926 # Simulator instruction rate (inst/s) -host_op_rate 77943 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19021903 # Simulator tick rate (ticks/s) -host_mem_usage 240316 # Number of bytes of host memory used -host_seconds 1291.18 # Real time elapsed on the host +host_inst_rate 104807 # Simulator instruction rate (inst/s) +host_op_rate 148726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36296181 # Simulator tick rate (ticks/s) +host_mem_usage 240672 # Number of bytes of host memory used +host_seconds 676.68 # Real time elapsed on the host sim_insts 70920072 # Number of instructions simulated sim_ops 100639320 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8687232 # Number of bytes read from this memory -system.physmem.bytes_inst_read 367552 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5661632 # Number of bytes written to this memory -system.physmem.num_reads 135738 # Number of read requests responded to by this memory -system.physmem.num_writes 88463 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 353703655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 14965007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 230515305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 584218960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory +system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory +system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory +system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory +system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total 12432222 # nu system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 268782500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002705 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7991.392638 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158907 # number of replacements system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use @@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total 46353396 # nu system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005388 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 115487 # number of replacements system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use @@ -586,20 +629,30 @@ system.cpu.l2cache.overall_accesses::cpu.data 163003 system.cpu.l2cache.overall_accesses::total 196558 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171927 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489855 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.370843 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.851351 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.851351 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959483 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.959483 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.171927 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.797899 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.691038 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.171927 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.797899 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.691038 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34237.831659 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 547.619048 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 547.619048 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.620761 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34295.827842 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34295.827842 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,20 +700,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.369828 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.851351 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.959483 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.690575 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.690575 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.421315 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.746032 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 40b740299..311edc8c7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index 6e02c2f67..f1623eafd 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:44:19 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:34:04 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 015123589..b5b6453b4 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.053932 # Nu sim_ticks 53932162000 # Number of ticks simulated final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 956394 # Simulator instruction rate (inst/s) -host_op_rate 1357212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 727373394 # Simulator tick rate (ticks/s) -host_mem_usage 228240 # Number of bytes of host memory used -host_seconds 74.15 # Real time elapsed on the host +host_inst_rate 1760373 # Simulator instruction rate (inst/s) +host_op_rate 2498132 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1338828629 # Simulator tick rate (ticks/s) +host_mem_usage 228700 # Number of bytes of host memory used +host_seconds 40.28 # Real time elapsed on the host sim_insts 70913189 # Number of instructions simulated sim_ops 100632437 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 419153654 # Number of bytes read from this memory -system.physmem.bytes_inst_read 312580308 # Number of instructions bytes read from this memory -system.physmem.bytes_written 78660211 # Number of bytes written to this memory -system.physmem.num_reads 105301330 # Number of read requests responded to by this memory -system.physmem.num_writes 19865820 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7771868185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 5795805256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1458502832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9230371017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 312580308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 106573346 # Number of bytes read from this memory +system.physmem.bytes_read::total 419153654 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 312580308 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 312580308 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory +system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 78145077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27156253 # Number of read requests responded to by this memory +system.physmem.num_reads::total 105301330 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory +system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5795805256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1976062929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7771868185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5795805256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5795805256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1458502832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1458502832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5795805256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3434565761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9230371017 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 6148c904a..678b8b9b7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index c236a6c17..d480c9ad1 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:45:44 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:34:55 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index f30f52adf..f1e03b8eb 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.133117 # Nu sim_ticks 133117442000 # Number of ticks simulated final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 457869 # Simulator instruction rate (inst/s) -host_op_rate 649270 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 866095863 # Simulator tick rate (ticks/s) -host_mem_usage 237424 # Number of bytes of host memory used -host_seconds 153.70 # Real time elapsed on the host +host_inst_rate 828989 # Simulator instruction rate (inst/s) +host_op_rate 1175527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1568098699 # Simulator tick rate (ticks/s) +host_mem_usage 237868 # Number of bytes of host memory used +host_seconds 84.89 # Real time elapsed on the host sim_insts 70373636 # Number of instructions simulated sim_ops 99791663 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8570688 # Number of bytes read from this memory -system.physmem.bytes_inst_read 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5660736 # Number of bytes written to this memory -system.physmem.num_reads 133917 # Number of read requests responded to by this memory -system.physmem.num_writes 88449 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 64384410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2210139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 42524375 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 106908785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 294208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8276480 # Number of bytes read from this memory +system.physmem.bytes_read::total 8570688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 294208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 294208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5660736 # Number of bytes written to this memory +system.physmem.bytes_written::total 5660736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 129320 # Number of read requests responded to by this memory +system.physmem.num_reads::total 133917 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 88449 # Number of write requests responded to by this memory +system.physmem.num_writes::total 88449 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2210139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62174272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64384410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2210139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2210139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42524375 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42524375 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42524375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2210139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62174272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106908785 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 78145078 # nu system.cpu.icache.overall_accesses::cpu.inst 78145078 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24211.233340 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24211.233340 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24211.233340 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 401062000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401062000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 401062000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21211.233340 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 46990235 # nu system.cpu.dcache.overall_accesses::cpu.data 46990235 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 46990235 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35166.521920 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54271.451529 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47946.924337 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47946.924337 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7191418000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7191418000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7191418000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32166.521920 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51271.451529 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 113660 # number of replacements system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 159998 system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243125 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.503965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.435345 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.958844 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.958844 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243125 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.808260 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.748533 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243125 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.808260 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.748533 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5172800000 system.cpu.l2cache.overall_mshr_miss_latency::total 5356680000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.503965 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.435345 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.958844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.958844 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.748533 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.748533 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 31ea2a719..49574e0d6 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr index bb51748c6..401e0da87 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall time(4026528248, 4026527848, ...) warn: ignoring syscall time(1375098, 4026527400, ...) diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 3e58ac7a5..ea448ddba 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:45:58 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:58:33 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 7d80c12bc..158c6976f 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.068149 # Nu sim_ticks 68148678500 # Number of ticks simulated final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1477309 # Simulator instruction rate (inst/s) -host_op_rate 1496437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 749087650 # Simulator tick rate (ticks/s) -host_mem_usage 221876 # Number of bytes of host memory used -host_seconds 90.98 # Real time elapsed on the host +host_inst_rate 2876458 # Simulator instruction rate (inst/s) +host_op_rate 2913702 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1458542737 # Simulator tick rate (ticks/s) +host_mem_usage 222372 # Number of bytes of host memory used +host_seconds 46.72 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 685773693 # Number of bytes read from this memory -system.physmem.bytes_inst_read 538214332 # Number of instructions bytes read from this memory -system.physmem.bytes_written 89882950 # Number of bytes written to this memory -system.physmem.num_reads 171784884 # Number of read requests responded to by this memory -system.physmem.num_writes 20864304 # Number of write requests responded to by this memory -system.physmem.num_other 15916 # Number of other requests responded to by this memory -system.physmem.bw_read 10062905226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7897648844 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1318924328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11381829554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 538214332 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 147559361 # Number of bytes read from this memory +system.physmem.bytes_read::total 685773693 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 538214332 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 538214332 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory +system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 134553583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 37231301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 171784884 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory +system.physmem.num_other::total 15916 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7897648844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2165256381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10062905226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7897648844 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7897648844 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1318924328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1318924328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7897648844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3484180709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11381829554 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 136297358 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 29c16b40d..3ca0a8939 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index e764a6213..f3517e2c4 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:46:17 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:59:31 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 3a7d1778b..3b1cc6fcd 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.202942 # Nu sim_ticks 202941992000 # Number of ticks simulated final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 667455 # Simulator instruction rate (inst/s) -host_op_rate 676097 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1007854644 # Simulator tick rate (ticks/s) -host_mem_usage 230768 # Number of bytes of host memory used -host_seconds 201.36 # Real time elapsed on the host +host_inst_rate 1325068 # Simulator instruction rate (inst/s) +host_op_rate 1342225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2000847198 # Simulator tick rate (ticks/s) +host_mem_usage 231252 # Number of bytes of host memory used +host_seconds 101.43 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8970304 # Number of bytes read from this memory -system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5584960 # Number of bytes written to this memory -system.physmem.num_reads 140161 # Number of read requests responded to by this memory -system.physmem.num_writes 87265 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 44201320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4115777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 27519982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 71721303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 835264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8135040 # Number of bytes read from this memory +system.physmem.bytes_read::total 8970304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 835264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 835264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5584960 # Number of bytes written to this memory +system.physmem.bytes_written::total 5584960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 127110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 140161 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 87265 # Number of write requests responded to by this memory +system.physmem.num_writes::total 87265 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 4115777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 40085543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 44201320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4115777 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4115777 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27519982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27519982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27519982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4115777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 40085543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 71721303 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 405883984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 134553584 # nu system.cpu.icache.overall_accesses::cpu.inst 134553584 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16930.864488 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16930.864488 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16930.864488 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 2605406000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2605406000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 2605406000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13930.864488 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use @@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 58095605 # nu system.cpu.dcache.overall_accesses::cpu.data 58095605 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 58095605 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37566.671795 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54566.239398 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 30800 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 30800 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49432.508313 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49432.508313 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6995661000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6995661000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6995661000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34566.671795 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51566.239398 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 27800 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 27800 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 120138 # number of replacements system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use @@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 150678 system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.069782 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.561111 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.165923 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965782 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.965782 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069782 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.843587 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.415043 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069782 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.843587 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.415043 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5084400000 system.cpu.l2cache.overall_mshr_miss_latency::total 5606440000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.561111 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165923 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965782 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965782 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.415043 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.415043 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 7c9012664..1fcd4f24c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 9d80ff74e..0482efbeb 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:59 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:44:37 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 9080a092b..0ddfc2b1c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 1.009999 # Nu sim_ticks 1009998808500 # Number of ticks simulated final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95125 # Simulator instruction rate (inst/s) -host_op_rate 95125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52795470 # Simulator tick rate (ticks/s) -host_mem_usage 214864 # Number of bytes of host memory used -host_seconds 19130.41 # Real time elapsed on the host +host_inst_rate 98665 # Simulator instruction rate (inst/s) +host_op_rate 98665 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54760444 # Simulator tick rate (ticks/s) +host_mem_usage 215204 # Number of bytes of host memory used +host_seconds 18443.95 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172618048 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written 74938304 # Number of bytes written to this memory -system.physmem.num_reads 2697157 # Number of read requests responded to by this memory -system.physmem.num_writes 1170911 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170909160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 54432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 74196428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 245105588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 172563072 # Number of bytes read from this memory +system.physmem.bytes_read::total 172618048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74938304 # Number of bytes written to this memory +system.physmem.bytes_written::total 74938304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2696298 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2697157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1170911 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1170911 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170854728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 170909160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 74196428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 74196428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 74196428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170854728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 245105588 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -156,11 +169,17 @@ system.cpu.icache.demand_accesses::total 231980227 # nu system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54607.276119 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54607.276119 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54607.276119 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,11 +207,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 45929000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53467.986030 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53467.986030 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use @@ -236,13 +261,21 @@ system.cpu.dcache.demand_accesses::total 605324165 # nu system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018229 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016940 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24698.466940 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37643.899650 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28397.395554 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28397.395554 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked @@ -278,13 +311,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21612.503361 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31332.051551 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23627.752746 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686301 # number of replacements system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use @@ -346,18 +387,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9111448 system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.250306 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.470613 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.295991 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.295991 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52334.109430 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52247.136865 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52247.178190 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52297.536757 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52297.536757 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52263.781827 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52263.781827 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -392,18 +441,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990994500 system.cpu.l2cache.overall_mshr_miss_latency::total 108025475000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250306 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470613 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.295991 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.295991 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.597095 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40112.619831 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 7904554e8..b6ae8cce3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 70e725c8b..3e17983a4 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:19 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:48:46 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 385663c88..ad65e54b6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.614317 # Nu sim_ticks 614317285000 # Number of ticks simulated final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104366 # Simulator instruction rate (inst/s) -host_op_rate 104366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36931162 # Simulator tick rate (ticks/s) -host_mem_usage 215744 # Number of bytes of host memory used -host_seconds 16634.12 # Real time elapsed on the host +host_inst_rate 134863 # Simulator instruction rate (inst/s) +host_op_rate 134863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47722573 # Simulator tick rate (ticks/s) +host_mem_usage 216172 # Number of bytes of host memory used +host_seconds 12872.68 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 173249728 # Number of bytes read from this memory -system.physmem.bytes_inst_read 62784 # Number of instructions bytes read from this memory -system.physmem.bytes_written 75020608 # Number of bytes written to this memory -system.physmem.num_reads 2707027 # Number of read requests responded to by this memory -system.physmem.num_writes 1172197 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 282019947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 102201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 122120295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 404140242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 62784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 173186944 # Number of bytes read from this memory +system.physmem.bytes_read::total 173249728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75020608 # Number of bytes written to this memory +system.physmem.bytes_written::total 75020608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2706046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2707027 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1172197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1172197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 281917745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 282019947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122120295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122120295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122120295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 281917745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 404140242 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 401793450 # nu system.cpu.icache.overall_accesses::cpu.inst 401793450 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 401793450 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34225.423729 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34225.423729 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34225.423729 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34225.423729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34225.423729 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 34897000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34897000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 34897000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35572.884811 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35572.884811 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35572.884811 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35572.884811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35572.884811 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9176629 # number of replacements system.cpu.dcache.tagsinuse 4086.046414 # Cycle average of tags in use @@ -446,15 +471,25 @@ system.cpu.dcache.demand_accesses::total 716734309 # nu system.cpu.dcache.overall_accesses::cpu.data 716734309 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 716734309 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018867 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.018867 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030574 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030574 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.285714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.285714 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.021493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021493 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.021493 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021493 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16686.513125 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16686.513125 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27968.066921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27968.066921 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23500 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20285.420171 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 20285.420171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20285.420171 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 118562765 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2148382500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 37554 # number of cycles access was blocked @@ -496,15 +531,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 119919732956 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119919732956 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 119919732956 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013124 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013124 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.142857 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012809 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012809 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012809 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11148.160071 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11148.160071 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20476.218184 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20476.218184 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35500 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13062.121566 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13062.121566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13062.121566 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2696556 # number of replacements system.cpu.l2cache.tagsinuse 26644.209628 # Cycle average of tags in use @@ -566,18 +611,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9180725 system.cpu.l2cache.overall_accesses::total 9181706 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250005 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.250106 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.468092 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.468092 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.294753 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.294828 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.294753 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.294828 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34371.049949 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.518024 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34338.535509 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.947843 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34465.947843 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34380.037768 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34371.049949 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34380.041027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34380.037768 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 17522000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1684 # number of cycles access was blocked @@ -612,18 +665,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84423852000 system.cpu.l2cache.overall_mshr_miss_latency::total 84454420000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250005 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250106 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.468092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.468092 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294828 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.294753 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294828 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31160.040775 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.925712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31161.924699 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31273.347207 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31273.347207 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31160.040775 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31198.232403 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31198.218562 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index e320bcc80..16083f416 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr index 1b49765a7..1ed796979 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 0267f64e9..88b1b065e 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:02 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:21:33 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index ce798be64..cdd816836 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2012645 # Simulator instruction rate (inst/s) -host_op_rate 2012645 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1009971108 # Simulator tick rate (ticks/s) -host_mem_usage 205536 # Number of bytes of host memory used -host_seconds 904.17 # Real time elapsed on the host +host_inst_rate 3414010 # Simulator instruction rate (inst/s) +host_op_rate 3414010 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1713194291 # Simulator tick rate (ticks/s) +host_mem_usage 206032 # Number of bytes of host memory used +host_seconds 533.03 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 9280309971 # Number of bytes read from this memory -system.physmem.bytes_inst_read 7305514036 # Number of instructions bytes read from this memory -system.physmem.bytes_written 827777307 # Number of bytes written to this memory -system.physmem.num_reads 2270974172 # Number of read requests responded to by this memory -system.physmem.num_writes 160728502 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10162526375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 906468506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory +system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory +system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory +system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index b8d054f36..f89f54e31 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 166dc5643..267941dc1 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:46 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index ada639802..3da64d83e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.663444 # Nu sim_ticks 2663443716000 # Number of ticks simulated final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 768706 # Simulator instruction rate (inst/s) -host_op_rate 768706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1125083732 # Simulator tick rate (ticks/s) -host_mem_usage 214428 # Number of bytes of host memory used -host_seconds 2367.33 # Real time elapsed on the host +host_inst_rate 1479188 # Simulator instruction rate (inst/s) +host_op_rate 1479188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2164950496 # Simulator tick rate (ticks/s) +host_mem_usage 214896 # Number of bytes of host memory used +host_seconds 1230.26 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172614208 # Number of bytes read from this memory -system.physmem.bytes_inst_read 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 74939072 # Number of bytes written to this memory -system.physmem.num_reads 2697097 # Number of read requests responded to by this memory -system.physmem.num_writes 1170923 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 64808656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 19271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 28136158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 92944814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 172562880 # Number of bytes read from this memory +system.physmem.bytes_read::total 172614208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74939072 # Number of bytes written to this memory +system.physmem.bytes_written::total 74939072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2696295 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2697097 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1170923 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1170923 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 64789385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64808656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 28136158 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28136158 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 28136158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64789385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 92944814 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 1826378510 # nu system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42506000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42506000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 42506000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use @@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 605324165 # nu system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24508.481513 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33767.845574 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26428.412638 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26428.412638 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 213473464000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213473464000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 213473464000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21508.481513 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30767.845574 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30767.845574 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23428.412638 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23428.412638 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686269 # number of replacements system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use @@ -286,18 +327,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9111734 system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250202 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.250285 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470663 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.470663 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.295915 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.295977 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.295915 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.295977 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +381,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107851800000 system.cpu.l2cache.overall_mshr_miss_latency::total 107883880000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250202 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250285 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470663 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.470663 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.295977 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.295977 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 11fd3546f..48015577c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 35c5c026a..2f52f2c05 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:46:03 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:36:31 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 54d82ede5..7863d76cc 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.463994 # Nu sim_ticks 463993693500 # Number of ticks simulated final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113228 # Simulator instruction rate (inst/s) -host_op_rate 126315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34014323 # Simulator tick rate (ticks/s) -host_mem_usage 231672 # Number of bytes of host memory used -host_seconds 13641.13 # Real time elapsed on the host +host_inst_rate 128371 # Simulator instruction rate (inst/s) +host_op_rate 143208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38563333 # Simulator tick rate (ticks/s) +host_mem_usage 232076 # Number of bytes of host memory used +host_seconds 12031.99 # Real time elapsed on the host sim_insts 1544563066 # Number of instructions simulated sim_ops 1723073879 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 189795648 # Number of bytes read from this memory -system.physmem.bytes_inst_read 49344 # Number of instructions bytes read from this memory -system.physmem.bytes_written 78222144 # Number of bytes written to this memory -system.physmem.num_reads 2965557 # Number of read requests responded to by this memory -system.physmem.num_writes 1222221 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 409047904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 106346 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 168584498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 577632403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory +system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory +system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total 283730265 # nu system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 27579500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9619302 # number of replacements system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use @@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total 676628084 # nu system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021216 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030175 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023501 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023501 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20022.197405 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20022.197405 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked @@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015335 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.817537 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23955.185749 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2953110 # number of replacements system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use @@ -578,18 +621,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9623398 system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.265181 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.483459 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308136 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308136 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34328.459152 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34690.748311 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34440.319656 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34440.319656 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked @@ -633,18 +684,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.265180 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.483459 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308135 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308135 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index e2f8298fd..b103ca45f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 89e0dc3cd..4559b3892 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:48:29 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:41:45 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 991f53624..6c3e8b909 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.861538 # Nu sim_ticks 861538205000 # Number of ticks simulated final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1163959 # Simulator instruction rate (inst/s) -host_op_rate 1298482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 649242111 # Simulator tick rate (ticks/s) -host_mem_usage 220952 # Number of bytes of host memory used -host_seconds 1326.99 # Real time elapsed on the host +host_inst_rate 2187855 # Simulator instruction rate (inst/s) +host_op_rate 2440714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220358665 # Simulator tick rate (ticks/s) +host_mem_usage 221416 # Number of bytes of host memory used +host_seconds 705.97 # Real time elapsed on the host sim_insts 1544563049 # Number of instructions simulated sim_ops 1723073862 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 7759650064 # Number of bytes read from this memory -system.physmem.bytes_inst_read 6178262392 # Number of instructions bytes read from this memory -system.physmem.bytes_written 624158392 # Number of bytes written to this memory -system.physmem.num_reads 2026949786 # Number of read requests responded to by this memory -system.physmem.num_writes 172586108 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9006739363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7171199555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 724469778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9731209141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 6178262392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1581387672 # Number of bytes read from this memory +system.physmem.bytes_read::total 7759650064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6178262392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6178262392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory +system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1544565598 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 482384188 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2026949786 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory +system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7171199555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1835539809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9006739363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7171199555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7171199555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 724469778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 724469778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7171199555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2560009587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9731209141 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 745e9eef0..88ea9515a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 4467d8b99..d07a6ceff 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:48:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:44:07 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 47aaa5f47..db0ae235a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.431420 # Nu sim_ticks 2431419954000 # Number of ticks simulated final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 629125 # Simulator instruction rate (inst/s) -host_op_rate 702110 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 994091440 # Simulator tick rate (ticks/s) -host_mem_usage 230132 # Number of bytes of host memory used -host_seconds 2445.87 # Real time elapsed on the host +host_inst_rate 1031283 # Simulator instruction rate (inst/s) +host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1629547552 # Simulator tick rate (ticks/s) +host_mem_usage 230584 # Number of bytes of host memory used +host_seconds 1492.08 # Real time elapsed on the host sim_insts 1538759609 # Number of instructions simulated sim_ops 1717270343 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172766016 # Number of bytes read from this memory -system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written 75006720 # Number of bytes written to this memory -system.physmem.num_reads 2699469 # Number of read requests responded to by this memory -system.physmem.num_writes 1171980 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 71055605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 16214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 30848937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 101904542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory +system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory +system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 1544565599 # nu system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54551.724138 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54551.724138 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32890000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 654970174 # nu system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2687066 # number of replacements system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9115236 system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.250398 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.471063 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.296128 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.296128 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250398 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471063 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.296128 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.296128 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 9635789c5..c6605043f 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:49:05 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 681bc52fe..d066014cc 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007259500 # Number of ticks simulated final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1189657 # Simulator instruction rate (inst/s) -host_op_rate 1853594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1125559296 # Simulator tick rate (ticks/s) -host_mem_usage 239492 # Number of bytes of host memory used -host_seconds 2528.53 # Real time elapsed on the host +host_inst_rate 1390065 # Simulator instruction rate (inst/s) +host_op_rate 2165848 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1315169413 # Simulator tick rate (ticks/s) +host_mem_usage 216596 # Number of bytes of host memory used +host_seconds 2163.99 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37129731755 # Number of bytes read from this memory -system.physmem.bytes_inst_read 32105863408 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1544656790 # Number of bytes written to this memory -system.physmem.num_reads 5252417675 # Number of read requests responded to by this memory -system.physmem.num_writes 438528337 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 13046253354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 11281019506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 542745204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13588998558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 32105863408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5023868347 # Number of bytes read from this memory +system.physmem.bytes_read::total 37129731755 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 32105863408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 32105863408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1544656790 # Number of bytes written to this memory +system.physmem.bytes_written::total 1544656790 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4013232926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1239184749 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5252417675 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 438528337 # Number of write requests responded to by this memory +system.physmem.num_writes::total 438528337 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11281019506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1765233848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13046253354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11281019506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11281019506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 542745204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 542745204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11281019506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2307979052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13588998558 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 5692014520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index efac2f0f1..11192711e 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 16:08:32 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 2bc91e6e3..e2cb03bbf 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 5.923548 # Nu sim_ticks 5923548078000 # Number of ticks simulated final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 747861 # Simulator instruction rate (inst/s) -host_op_rate 1165236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1472697488 # Simulator tick rate (ticks/s) -host_mem_usage 248420 # Number of bytes of host memory used -host_seconds 4022.24 # Real time elapsed on the host +host_inst_rate 633731 # Simulator instruction rate (inst/s) +host_op_rate 987410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1247949692 # Simulator tick rate (ticks/s) +host_mem_usage 225520 # Number of bytes of host memory used +host_seconds 4746.62 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 173910080 # Number of bytes read from this memory -system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 75176384 # Number of bytes written to this memory -system.physmem.num_reads 2717345 # Number of read requests responded to by this memory -system.physmem.num_writes 1174631 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 29359107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 12691107 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 42050214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 173866880 # Number of bytes read from this memory +system.physmem.bytes_read::total 173910080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75176384 # Number of bytes written to this memory +system.physmem.bytes_written::total 75176384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2716670 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2717345 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1174631 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1174631 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 29351814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29359107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12691107 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12691107 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12691107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 29351814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42050214 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 11847096156 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 4013232927 # nu system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 35775000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 1677713086 # nu system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24617.504171 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33796.256483 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26521.034159 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26521.034159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21617.504171 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30796.256483 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2706631 # number of replacements system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use @@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9112677 system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.252798 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.252868 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.471339 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.298120 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.298172 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.298120 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.298172 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.252868 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471339 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.298172 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.298172 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 5ef210362..0cab3c39f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index a267cf67d..c65e040d8 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:52:53 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 46f5e7fc2..a7912f8e0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.042005 # Nu sim_ticks 42005374000 # Number of ticks simulated final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62394 # Simulator instruction rate (inst/s) -host_op_rate 62394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28517940 # Simulator tick rate (ticks/s) -host_mem_usage 218584 # Number of bytes of host memory used -host_seconds 1472.95 # Real time elapsed on the host +host_inst_rate 106867 # Simulator instruction rate (inst/s) +host_op_rate 106867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48844875 # Simulator tick rate (ticks/s) +host_mem_usage 218932 # Number of bytes of host memory used +host_seconds 859.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 316032 # Number of bytes read from this memory -system.physmem.bytes_inst_read 178816 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 4938 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7523609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4256979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 7523609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory +system.physmem.bytes_read::total 316032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 4256979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3266630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7523609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4256979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4256979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4256979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3266630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7523609 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -155,11 +162,17 @@ system.cpu.icache.demand_accesses::total 10037346 # nu system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001168 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001168 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001168 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25187.031037 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25187.031037 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25187.031037 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,11 +200,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 228898000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000996 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000996 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000996 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22898.959584 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use @@ -235,13 +254,21 @@ system.cpu.dcache.demand_accesses::total 26497301 # nu system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000852 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000230 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000230 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51433.876812 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54825.933947 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54518.627934 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54518.627934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -277,13 +304,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 116211500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48875.789474 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53201.086957 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use @@ -348,18 +383,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2223 system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.307134 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.404125 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.404125 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52337.064677 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52593.495935 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52426.488457 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52426.488457 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,18 +435,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307134 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.404125 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.404125 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40127.798507 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40270.325203 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index ab521397c..f02146b21 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index ec78af77e..11770df5a 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:19 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:06:35 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 9debfab2e..5f8b8cbb4 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.023638 # Nu sim_ticks 23638033500 # Number of ticks simulated final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91328 # Simulator instruction rate (inst/s) -host_op_rate 91328 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25645337 # Simulator tick rate (ticks/s) -host_mem_usage 219700 # Number of bytes of host memory used -host_seconds 921.73 # Real time elapsed on the host +host_inst_rate 160213 # Simulator instruction rate (inst/s) +host_op_rate 160213 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44988546 # Simulator tick rate (ticks/s) +host_mem_usage 220112 # Number of bytes of host memory used +host_seconds 525.42 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 336064 # Number of bytes read from this memory -system.physmem.bytes_inst_read 197952 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5251 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 14217088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 8374301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 14217088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 197952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138112 # Number of bytes read from this memory +system.physmem.bytes_read::total 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 197952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197952 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8374301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5842787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14217088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8374301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8374301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8374301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5842787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14217088 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -357,11 +364,17 @@ system.cpu.icache.demand_accesses::total 14943347 # nu system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14911.104613 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14911.104613 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14911.104613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,11 +402,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 130905500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130905500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 130905500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000823 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000823 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000823 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10645.319997 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10645.319997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158 # number of replacements system.cpu.dcache.tagsinuse 1455.343539 # Cycle average of tags in use @@ -445,15 +464,25 @@ system.cpu.dcache.demand_accesses::total 28193388 # nu system.cpu.dcache.overall_accesses::cpu.data 28193388 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 28193388 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001239 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001239 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001825 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001825 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000319 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000319 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30077.695560 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35913.531968 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35300.188868 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35300.188868 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -493,15 +522,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 77918500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77918500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 77918500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000265 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001825 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001825 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32181.017613 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32181.017613 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35616.454229 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35616.454229 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34831.694233 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34831.694233 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2429.489974 # Cycle average of tags in use @@ -566,18 +605,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2238 system.cpu.l2cache.overall_accesses::total 14535 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.251525 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.277227 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984936 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984936 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.251525 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964254 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.361266 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.251525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964254 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.361266 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.562561 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34414.847162 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34332.723177 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34718.823529 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34457.722339 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34457.722339 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -610,18 +657,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.277227 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984936 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.361266 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.361266 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.451704 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31549.411765 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31243.096553 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index d2933f641..418ddecee 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr index 1b49765a7..1ed796979 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout index 0cde8149d..fbcfa0aae 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:43 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:46:55 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 47fe26ecb..4c4ae20f6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2042062 # Simulator instruction rate (inst/s) -host_op_rate 2042061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1021030561 # Simulator tick rate (ticks/s) -host_mem_usage 209388 # Number of bytes of host memory used -host_seconds 45.01 # Real time elapsed on the host +host_inst_rate 3561938 # Simulator instruction rate (inst/s) +host_op_rate 3561935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1780967913 # Simulator tick rate (ticks/s) +host_mem_usage 209744 # Number of bytes of host memory used +host_seconds 25.80 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 475949877 # Number of bytes read from this memory -system.physmem.bytes_inst_read 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_written 30920974 # Number of bytes written to this memory -system.physmem.num_reads 111899287 # Number of read requests responded to by this memory -system.physmem.num_writes 6501103 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10357641815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11030545389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory +system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory +system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory +system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory +system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index f8f410537..39023eb08 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index de47399fe..3fe1e7489 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:39:37 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:18:52 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 180c17bb1..5d71f2054 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.118740 # Nu sim_ticks 118740049000 # Number of ticks simulated final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 796943 # Simulator instruction rate (inst/s) -host_op_rate 796942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1029660597 # Simulator tick rate (ticks/s) -host_mem_usage 218284 # Number of bytes of host memory used -host_seconds 115.32 # Real time elapsed on the host +host_inst_rate 1590844 # Simulator instruction rate (inst/s) +host_op_rate 1590843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2055391195 # Simulator tick rate (ticks/s) +host_mem_usage 218628 # Number of bytes of host memory used +host_seconds 57.77 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 304960 # Number of bytes read from this memory -system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 4765 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2568299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1412699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2568299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory +system.physmem.bytes_read::total 304960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1412699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2568299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412699 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412699 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2568299 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 91903090 # nu system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26935.605170 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 203692000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 26497301 # nu system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51313.684211 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54507.422402 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54507.422402 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,13 +244,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 114501000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use @@ -288,18 +323,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2223 system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +375,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 0883e5a4a..292cbefed 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 2311bc195..f8119727b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:50:10 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:52:11 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a127da205..15323b4b4 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.076323 # Nu sim_ticks 76322764500 # Number of ticks simulated final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57710 # Simulator instruction rate (inst/s) -host_op_rate 63186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25558377 # Simulator tick rate (ticks/s) -host_mem_usage 235176 # Number of bytes of host memory used -host_seconds 2986.21 # Real time elapsed on the host +host_inst_rate 95790 # Simulator instruction rate (inst/s) +host_op_rate 104880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42423254 # Simulator tick rate (ticks/s) +host_mem_usage 235620 # Number of bytes of host memory used +host_seconds 1799.08 # Real time elapsed on the host sim_insts 172333279 # Number of instructions simulated sim_ops 188686762 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 246592 # Number of bytes read from this memory -system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3853 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory +system.physmem.bytes_read::total 246592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -368,11 +375,17 @@ system.cpu.icache.demand_accesses::total 37841460 # nu system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,11 +413,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 78893000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 59 # number of replacements system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use @@ -460,15 +479,25 @@ system.cpu.dcache.demand_accesses::total 47285356 # nu system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -506,13 +535,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 63473000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use @@ -577,18 +614,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1881 system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -630,18 +675,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index bd55e37b1..b72ac514a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 1a4090c67..18d32cd6b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 17:02:03 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:53:41 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 11a4c0835..bbd6c00f1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.103107 # Nu sim_ticks 103106771000 # Number of ticks simulated final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1081638 # Simulator instruction rate (inst/s) -host_op_rate 1184289 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 647201988 # Simulator tick rate (ticks/s) -host_mem_usage 224040 # Number of bytes of host memory used -host_seconds 159.31 # Real time elapsed on the host +host_inst_rate 2060024 # Simulator instruction rate (inst/s) +host_op_rate 2255526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1232622542 # Simulator tick rate (ticks/s) +host_mem_usage 224496 # Number of bytes of host memory used +host_seconds 83.65 # Real time elapsed on the host sim_insts 172317417 # Number of instructions simulated sim_ops 188670900 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 869973902 # Number of bytes read from this memory -system.physmem.bytes_inst_read 759440240 # Number of instructions bytes read from this memory -system.physmem.bytes_written 45252940 # Number of bytes written to this memory -system.physmem.num_reads 219482514 # Number of read requests responded to by this memory -system.physmem.num_writes 12386694 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8437602047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7365570977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 438893969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 8876496016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 759440240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110533662 # Number of bytes read from this memory +system.physmem.bytes_read::total 869973902 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 759440240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 759440240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory +system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 189860060 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29622454 # Number of read requests responded to by this memory +system.physmem.num_reads::total 219482514 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory +system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7365570977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1072031070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8437602047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7365570977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7365570977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 438893969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 438893969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7365570977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1510925039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8876496016 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 98e25ecfe..3e3d3dcbe 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 97209751d..08e4c719e 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 17:04:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:54:15 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 5b0760555..1e695b431 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.232077 # Nu sim_ticks 232077154000 # Number of ticks simulated final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 578450 # Simulator instruction rate (inst/s) -host_op_rate 633465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 781209577 # Simulator tick rate (ticks/s) -host_mem_usage 233216 # Number of bytes of host memory used -host_seconds 297.07 # Real time elapsed on the host +host_inst_rate 665536 # Simulator instruction rate (inst/s) +host_op_rate 728833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 898821179 # Simulator tick rate (ticks/s) +host_mem_usage 233632 # Number of bytes of host memory used +host_seconds 258.20 # Real time elapsed on the host sim_insts 171842491 # Number of instructions simulated sim_ops 188185929 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 220992 # Number of bytes read from this memory -system.physmem.bytes_inst_read 110656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3453 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 952235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 476807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 952235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory +system.physmem.bytes_read::total 220992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 476807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 475428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 952235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 475428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 952235 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total 189860061 # nu system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37801.376598 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37801.376598 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37801.376598 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 106179000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use @@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total 41964334 # nu system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52525.399129 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54474.007826 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54474.007826 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,13 +262,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 92087000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use @@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1789 system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index b2ac1c016..505ad335a 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index fe38fbd1a..435dd5018 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:47:40 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 15:01:23 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 417f58ce8..7fc4c3f51 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.096723 # Nu sim_ticks 96722951500 # Number of ticks simulated final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1581365 # Simulator instruction rate (inst/s) -host_op_rate 1581366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 790687708 # Simulator tick rate (ticks/s) -host_mem_usage 217932 # Number of bytes of host memory used -host_seconds 122.33 # Real time elapsed on the host +host_inst_rate 2785942 # Simulator instruction rate (inst/s) +host_op_rate 2785945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1392980356 # Simulator tick rate (ticks/s) +host_mem_usage 218424 # Number of bytes of host memory used +host_seconds 69.44 # Real time elapsed on the host sim_insts 193444531 # Number of instructions simulated sim_ops 193444769 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 997245606 # Number of bytes read from this memory -system.physmem.bytes_inst_read 773782192 # Number of instructions bytes read from this memory -system.physmem.bytes_written 72065412 # Number of bytes written to this memory -system.physmem.num_reads 251180617 # Number of read requests responded to by this memory -system.physmem.num_writes 18976439 # Number of write requests responded to by this memory -system.physmem.num_other 22406 # Number of other requests responded to by this memory -system.physmem.bw_read 10310330594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 745070440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11055401034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 773782192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 223463414 # Number of bytes read from this memory +system.physmem.bytes_read::total 997245606 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 773782192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 773782192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory +system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 193445548 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 57735069 # Number of read requests responded to by this memory +system.physmem.num_reads::total 251180617 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory +system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory +system.physmem.num_other::total 22406 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2310345275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10310330594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 745070440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 745070440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3055415715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11055401034 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index af9f6c271..35d8a380c 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index f7fdf9677..8467606a8 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:49:18 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 15:02:43 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 415ede7b3..170992582 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.270577 # Nu sim_ticks 270576960000 # Number of ticks simulated final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 668557 # Simulator instruction rate (inst/s) -host_op_rate 668558 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 935131366 # Simulator tick rate (ticks/s) -host_mem_usage 226812 # Number of bytes of host memory used -host_seconds 289.35 # Real time elapsed on the host +host_inst_rate 1394951 # Simulator instruction rate (inst/s) +host_op_rate 1394952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1951161352 # Simulator tick rate (ticks/s) +host_mem_usage 227304 # Number of bytes of host memory used +host_seconds 138.67 # Real time elapsed on the host sim_insts 193444531 # Number of instructions simulated sim_ops 193444769 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 331072 # Number of bytes read from this memory -system.physmem.bytes_inst_read 230208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5173 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1223578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 850804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1223578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory +system.physmem.bytes_read::total 331072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 850804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223578 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 541153920 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 193445549 # nu system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26294.433594 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26294.433594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 286242000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use @@ -159,15 +178,25 @@ system.cpu.dcache.demand_accesses::total 76711508 # nu system.cpu.dcache.overall_accesses::cpu.data 76711508 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 76711508 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,15 +228,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 83475000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use @@ -267,18 +306,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1576 system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,18 +358,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 59b747474..e9982c78d 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 16:25:20 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 1d5121a0a..9505812e4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.087752 # Nu sim_ticks 87751730000 # Number of ticks simulated final_tick 87751730000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56809 # Simulator instruction rate (inst/s) -host_op_rate 95217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37745520 # Simulator tick rate (ticks/s) -host_mem_usage 259224 # Number of bytes of host memory used -host_seconds 2324.83 # Real time elapsed on the host +host_inst_rate 66952 # Simulator instruction rate (inst/s) +host_op_rate 112217 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44484510 # Simulator tick rate (ticks/s) +host_mem_usage 236376 # Number of bytes of host memory used +host_seconds 1972.64 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 345024 # Number of bytes read from this memory -system.physmem.bytes_inst_read 219584 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5391 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3931820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2502332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3931820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 219584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory +system.physmem.bytes_read::total 345024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219584 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5391 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2502332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1429487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3931820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2502332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2502332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2502332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1429487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3931820 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 175503461 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -323,11 +330,17 @@ system.cpu.icache.demand_accesses::total 25822554 # nu system.cpu.icache.overall_accesses::cpu.inst 25822554 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25822554 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000352 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000352 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20598.922248 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20598.922248 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20598.922248 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 20598.922248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20598.922248 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,11 +368,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 130634500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130634500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 130634500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16908.426094 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16908.426094 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16908.426094 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16908.426094 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 56 # number of replacements system.cpu.dcache.tagsinuse 1426.584624 # Cycle average of tags in use @@ -403,13 +422,21 @@ system.cpu.dcache.demand_accesses::total 68644382 # nu system.cpu.dcache.overall_accesses::cpu.data 68644382 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 68644382 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000036 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32154.792746 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32154.792746 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37945.804196 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37945.804196 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36148.914791 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36148.914791 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36148.914791 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,13 +472,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 74414500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74414500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 74414500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32985.260771 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32985.260771 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34949.211909 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34949.211909 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34547.121634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34547.121634 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2579.336511 # Cycle average of tags in use @@ -520,19 +555,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 1999 system.cpu.l2cache.overall_accesses::total 9570 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.453177 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929545 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.479341 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994869 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.453177 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.980490 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.563323 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.453177 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.980490 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.563323 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.967356 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34172.371638 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34243.489583 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34168.923275 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34168.923275 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34222.036728 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.967356 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34169.642857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34222.036728 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -569,20 +613,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60787000 system.cpu.l2cache.overall_mshr_miss_latency::total 167227500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.479341 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994869 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.563323 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.453177 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980490 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.563323 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.171087 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30993.887531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31020.052083 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.171087 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.775510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31019.755147 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index c6c7c62e1..f20b23119 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 16:58:23 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 98c43bfba..52d17f26b 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.131393 # Nu sim_ticks 131393100000 # Number of ticks simulated final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 560372 # Simulator instruction rate (inst/s) -host_op_rate 939232 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 557494351 # Simulator tick rate (ticks/s) -host_mem_usage 246748 # Number of bytes of host memory used -host_seconds 235.69 # Real time elapsed on the host +host_inst_rate 1290267 # Simulator instruction rate (inst/s) +host_op_rate 2162601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1283641901 # Simulator tick rate (ticks/s) +host_mem_usage 223844 # Number of bytes of host memory used +host_seconds 102.36 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1698379042 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1387955288 # Number of instructions bytes read from this memory -system.physmem.bytes_written 99822189 # Number of bytes written to this memory -system.physmem.num_reads 230176419 # Number of read requests responded to by this memory -system.physmem.num_writes 20515730 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 12925937831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 10563380330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 759721698 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13685659529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1387955288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 310423754 # Number of bytes read from this memory +system.physmem.bytes_read::total 1698379042 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1387955288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1387955288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 99822189 # Number of bytes written to this memory +system.physmem.bytes_written::total 99822189 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 173494411 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 56682008 # Number of read requests responded to by this memory +system.physmem.num_reads::total 230176419 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20515730 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20515730 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10563380330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2362557501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12925937831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10563380330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10563380330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 759721698 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 759721698 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10563380330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3122279199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13685659529 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 262786201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index a97127599..3bc28071d 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 17:00:16 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 1165c8c9e..8ebc5f697 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 361817 # Simulator instruction rate (inst/s) -host_op_rate 606437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 687521912 # Simulator tick rate (ticks/s) -host_mem_usage 255672 # Number of bytes of host memory used -host_seconds 365.02 # Real time elapsed on the host +host_inst_rate 653434 # Simulator instruction rate (inst/s) +host_op_rate 1095213 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1241649233 # Simulator tick rate (ticks/s) +host_mem_usage 232776 # Number of bytes of host memory used +host_seconds 202.12 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 303040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 4735 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1207520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 724257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1207520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory +system.physmem.bytes_read::total 303040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 724257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207520 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 501921262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 173494412 # nu system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39420.856412 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39420.856412 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39420.856412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 170928000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170928000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 170928000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.145718 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.145718 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.145718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use @@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total 77197738 # nu system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55107.033639 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.152091 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55780.577428 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55780.577428 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -185,13 +212,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 100546500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use @@ -256,18 +291,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1905 system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.905063 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52003.273495 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52003.273495 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +343,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 631fa3b25..08fd1ccfb 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -282,9 +282,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -344,10 +343,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -403,9 +401,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 8c9800a70..06d87b670 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:39:49 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b34633a17..b45122ce6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,23 +4,50 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1989571 # Simulator instruction rate (inst/s) -host_op_rate 1989570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58921958204 # Simulator tick rate (ticks/s) -host_mem_usage 298304 # Number of bytes of host memory used -host_seconds 31.74 # Real time elapsed on the host +host_inst_rate 2870976 # Simulator instruction rate (inst/s) +host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85025108641 # Simulator tick rate (ticks/s) +host_mem_usage 298608 # Number of bytes of host memory used +host_seconds 22.00 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 72297472 # Number of bytes read from this memory -system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10452352 # Number of bytes written to this memory -system.physmem.num_reads 1129648 # Number of read requests responded to by this memory -system.physmem.num_writes 163318 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 38654814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 531994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 44243304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory +system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory +system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory +system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 1051788 # number of replacements system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use system.l2c.total_refs 2341203 # Total number of references to valid blocks. @@ -118,20 +145,26 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -169,9 +202,13 @@ system.iocache.demand_accesses::total 41727 # nu system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -275,6 +312,7 @@ system.cpu0.kern.ipl_used::21 1 # fr system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -333,7 +371,7 @@ system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode @@ -397,8 +435,11 @@ system.cpu0.icache.demand_accesses::total 57230132 # n system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,11 +497,17 @@ system.cpu0.dcache.demand_accesses::total 14729930 # n system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,6 +595,7 @@ system.cpu1.kern.ipl_used::0 0.999032 # fr system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -593,7 +641,7 @@ system.cpu1.kern.mode_good::idle 32 system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode @@ -626,8 +674,11 @@ system.cpu1.icache.demand_accesses::total 5935766 # n system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,11 +736,17 @@ system.cpu1.dcache.demand_accesses::total 1884270 # n system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 3d4adbd35..3950ce4a4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -185,9 +185,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -247,10 +246,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -306,9 +304,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index f348f1381..92dc7ad3d 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:42:39 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:07:23 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 1b6d7ca40..4492aa0b0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1921293 # Simulator instruction rate (inst/s) -host_op_rate 1921291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58540553267 # Simulator tick rate (ticks/s) -host_mem_usage 295828 # Number of bytes of host memory used -host_seconds 31.25 # Real time elapsed on the host +host_inst_rate 2878195 # Simulator instruction rate (inst/s) +host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87696777763 # Simulator tick rate (ticks/s) +host_mem_usage 296144 # Number of bytes of host memory used +host_seconds 20.86 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 71650816 # Number of bytes read from this memory -system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10156864 # Number of bytes written to this memory -system.physmem.num_reads 1119544 # Number of read requests responded to by this memory -system.physmem.num_writes 158701 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 39167743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 44719968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory +system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory +system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 1045877 # number of replacements system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use system.l2c.total_refs 2291835 # Total number of references to valid blocks. @@ -79,12 +96,17 @@ system.l2c.overall_accesses::cpu.data 2043063 # nu system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -122,9 +144,13 @@ system.iocache.demand_accesses::total 41726 # nu system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,6 +250,7 @@ system.cpu.kern.ipl_used::0 0.981732 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -281,7 +308,7 @@ system.cpu.kern.mode_good::idle 171 system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode @@ -345,8 +372,11 @@ system.cpu.icache.demand_accesses::total 60050143 # nu system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,10 +432,15 @@ system.cpu.dcache.demand_accesses::total 15682061 # nu system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 6299f010e..090f52454 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -274,9 +274,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -336,10 +335,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -395,9 +393,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index dc632ce62..b3456c80f 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:25 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:45 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 7ab3bb0af..e92359043 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,23 +4,50 @@ sim_seconds 1.958647 # Nu sim_ticks 1958647095000 # Number of ticks simulated final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 669282 # Simulator instruction rate (inst/s) -host_op_rate 669282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22085281308 # Simulator tick rate (ticks/s) -host_mem_usage 295084 # Number of bytes of host memory used -host_seconds 88.69 # Real time elapsed on the host +host_inst_rate 1245422 # Simulator instruction rate (inst/s) +host_op_rate 1245421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41097010927 # Simulator tick rate (ticks/s) +host_mem_usage 295412 # Number of bytes of host memory used +host_seconds 47.66 # Real time elapsed on the host sim_insts 59355643 # Number of instructions simulated sim_ops 59355643 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30050624 # Number of bytes read from this memory -system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10333120 # Number of bytes written to this memory -system.physmem.num_reads 469541 # Number of read requests responded to by this memory -system.physmem.num_writes 161455 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15342541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 495852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 20618183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 919744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25960192 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 51456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 468416 # Number of bytes read from this memory +system.physmem.bytes_read::total 30050624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 919744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 51456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 971200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10333120 # Number of bytes written to this memory +system.physmem.bytes_written::total 10333120 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14371 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 405628 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7319 # Number of read requests responded to by this memory +system.physmem.num_reads::total 469541 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 161455 # Number of write requests responded to by this memory +system.physmem.num_writes::total 161455 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 469581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13254145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1353391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 239153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15342541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 469581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 495852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5275642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5275642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5275642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 469581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13254145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1353391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 239153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20618183 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 393576 # number of replacements system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use system.l2c.total_refs 2371449 # Total number of references to valid blocks. @@ -142,38 +169,50 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.015693 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.275649 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.009368 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.033331 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.146292 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934476 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.903285 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.929089 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.454545 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.795699 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.706349 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.408381 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.330189 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.403596 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.015693 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.304282 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.009368 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.138621 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.179301 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.015693 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.304282 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.009368 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.138621 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.179301 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52016.667760 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 914.798206 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1575.757576 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1025.780190 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6933.333333 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4216.216216 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4674.157303 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52002.375911 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52012.540780 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52012.540780 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,44 +290,59 @@ system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015693 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275649 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.033331 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.146287 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934476 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.929089 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706349 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.403596 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.179296 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.179296 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.717580 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.691995 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.375911 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements system.iocache.tagsinuse 0.563721 # Cycle average of tags in use @@ -324,13 +378,21 @@ system.iocache.demand_accesses::total 41726 # nu system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137701.766606 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137608.129320 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137608.129320 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked @@ -358,13 +420,21 @@ system.iocache.demand_mshr_miss_latency::total 3571932998 system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -458,6 +528,7 @@ system.cpu0.kern.ipl_used::21 1 # fr system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808938 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -515,7 +586,7 @@ system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.298893 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode @@ -585,11 +656,17 @@ system.cpu0.icache.demand_accesses::total 54081252 # n system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016933 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016933 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016933 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14664.130944 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14664.130944 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,11 +690,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016933 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016933 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016933 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1338438 # number of replacements system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use @@ -677,17 +760,29 @@ system.cpu0.dcache.demand_accesses::total 14308776 # n system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122512 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049821 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085698 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002134 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092785 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092785 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7251.219512 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -729,20 +824,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122512 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049821 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085698 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002134 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092785 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092785 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4251.219512 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -820,6 +930,7 @@ system.cpu1.kern.ipl_used::0 0.998923 # fr system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.710351 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -860,7 +971,7 @@ system.cpu1.kern.mode_good::idle 13 system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.599582 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode @@ -899,11 +1010,17 @@ system.cpu1.icache.demand_accesses::total 5286354 # n system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016458 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016458 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016458 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14488.908683 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14488.908683 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -927,11 +1044,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 999558500 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016458 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11488.517901 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 52960 # number of replacements system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use @@ -991,17 +1114,29 @@ system.cpu1.dcache.demand_accesses::total 1677594 # n system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035676 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032042 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.041975 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034296 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034296 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14368.630938 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27265.853778 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13318.737271 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12704.950495 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18946.344770 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18946.344770 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1043,20 +1178,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035676 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032042 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076923 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.041975 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034296 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034296 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9704.950495 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index d5815e263..d6cd88975 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -181,9 +181,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -243,10 +242,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -302,9 +300,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 7b3033c70..33fb3404f 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:23:20 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index d0852c317..42fcfede1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.915549 # Nu sim_ticks 1915548867000 # Number of ticks simulated final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 646342 # Simulator instruction rate (inst/s) -host_op_rate 646342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22054916762 # Simulator tick rate (ticks/s) -host_mem_usage 292620 # Number of bytes of host memory used -host_seconds 86.85 # Real time elapsed on the host +host_inst_rate 1238015 # Simulator instruction rate (inst/s) +host_op_rate 1238014 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42244373047 # Simulator tick rate (ticks/s) +host_mem_usage 292960 # Number of bytes of host memory used +host_seconds 45.34 # Real time elapsed on the host sim_insts 56137087 # Number of instructions simulated sim_ops 56137087 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29663360 # Number of bytes read from this memory -system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10122368 # Number of bytes written to this memory -system.physmem.num_reads 463490 # Number of read requests responded to by this memory -system.physmem.num_writes 158162 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 943040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 26067904 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652416 # Number of bytes read from this memory +system.physmem.bytes_read::total 29663360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 943040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 943040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10122368 # Number of bytes written to this memory +system.physmem.bytes_written::total 10122368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14735 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 407311 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41444 # Number of read requests responded to by this memory +system.physmem.num_reads::total 463490 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 158162 # Number of write requests responded to by this memory +system.physmem.num_writes::total 158162 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 492308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13608582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1384677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15485567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 492308 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492308 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5284317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5284317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5284317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 492308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13608582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1384677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20769884 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 389289 # number of replacements system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use system.l2c.total_refs 2311163 # Total number of references to valid blocks. @@ -92,20 +109,30 @@ system.l2c.overall_accesses::cpu.data 1390437 # nu system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.150967 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.538462 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.388905 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.182179 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.182179 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52016.540189 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52003.930884 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52013.009194 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52013.009194 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -150,23 +177,36 @@ system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.150967 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.538462 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.388905 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.182179 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.182179 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.522105 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.930884 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.340325 # Cycle average of tags in use @@ -202,13 +242,21 @@ system.iocache.demand_accesses::total 41725 # nu system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115265.884393 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137714.208847 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137621.133709 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137621.133709 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked @@ -236,13 +284,21 @@ system.iocache.demand_mshr_miss_latency::total 3572392988 system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -332,6 +388,7 @@ system.cpu.kern.ipl_used::0 0.981746 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814116 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -389,7 +446,7 @@ system.cpu.kern.mode_good::idle 168 system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391657 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode @@ -459,11 +516,17 @@ system.cpu.icache.demand_accesses::total 56148907 # nu system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016534 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016534 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016534 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14667.218001 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14667.218001 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14667.218001 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,11 +550,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 10830625500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016534 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016534 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016534 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11666.482290 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1390115 # number of replacements system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use @@ -547,15 +616,25 @@ system.cpu.dcache.demand_accesses::total 15029535 # nu system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120441 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049462 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085908 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25368.690313 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30323.439631 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14300.331376 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26466.589124 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26466.589124 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,18 +672,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120441 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049462 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085908 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index b18e2b725..31269f9bd 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -299,9 +300,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -360,10 +360,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -775,9 +774,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 17a6394ef..be4dcf157 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:25:17 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 911653589000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 96669edc4..002831edb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 0.911654 # Nu sim_ticks 911653589000 # Number of ticks simulated final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1682178 # Simulator instruction rate (inst/s) -host_op_rate 2174115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25299801897 # Simulator tick rate (ticks/s) -host_mem_usage 379752 # Number of bytes of host memory used -host_seconds 36.03 # Real time elapsed on the host +host_inst_rate 1520101 # Simulator instruction rate (inst/s) +host_op_rate 1964640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22862175544 # Simulator tick rate (ticks/s) +host_mem_usage 382804 # Number of bytes of host memory used +host_seconds 39.88 # Real time elapsed on the host sim_insts 60615585 # Number of instructions simulated sim_ops 78342060 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 50963556 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1003776 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10224784 # Number of bytes written to this memory -system.physmem.num_reads 5103504 # Number of read requests responded to by this memory -system.physmem.num_writes 869236 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55902326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1101050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 11215646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 67117972 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 75 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 75 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 75 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory +system.physmem.bytes_read::total 50963556 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 10224784 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 869236 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 127935 # number of replacements system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use system.l2c.total_refs 1477463 # Total number of references to valid blocks. @@ -175,12 +233,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027957 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.855220 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.765972 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.595343 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses @@ -189,6 +251,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.123526 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses @@ -197,6 +260,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.123526 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,8 +372,11 @@ system.cpu0.icache.demand_accesses::total 34685670 # n system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,11 +434,17 @@ system.cpu0.dcache.demand_accesses::total 14721592 # n system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,8 +550,11 @@ system.cpu1.icache.demand_accesses::total 26945412 # n system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -536,11 +612,17 @@ system.cpu1.dcache.demand_accesses::total 9644704 # n system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 720edf3cb..99dc32f6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -184,9 +185,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -245,10 +245,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -660,9 +659,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 4b3b38463..f08c091ef 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:24:24 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2332330037000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e1058fc4f..154c8ff44 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.332330 # Nu sim_ticks 2332330037000 # Number of ticks simulated final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1538399 # Simulator instruction rate (inst/s) -host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60412799239 # Simulator tick rate (ticks/s) -host_mem_usage 379756 # Number of bytes of host memory used -host_seconds 38.61 # Real time elapsed on the host +host_inst_rate 1412842 # Simulator instruction rate (inst/s) +host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55482154888 # Simulator tick rate (ticks/s) +host_mem_usage 382804 # Number of bytes of host memory used +host_seconds 42.04 # Real time elapsed on the host sim_insts 59392246 # Number of instructions simulated sim_ops 76665494 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 122661296 # Number of bytes read from this memory -system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9590216 # Number of bytes written to this memory -system.physmem.num_reads 14137091 # Number of read requests responded to by this memory -system.physmem.num_writes 856679 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory +system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory +system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 117012 # number of replacements system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use system.l2c.total_refs 1527554 # Total number of references to valid blocks. @@ -112,16 +143,21 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,8 +269,11 @@ system.cpu.icache.demand_accesses::total 60406063 # nu system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,10 +329,15 @@ system.cpu.dcache.demand_accesses::total 23757776 # nu system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index e58e54e5c..08257cec9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -291,9 +292,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -352,10 +352,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -767,9 +766,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index d6c8fa18c..dc9f6d387 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:26:08 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1169707043000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 4dc707863..c1f17df29 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 1.169707 # Nu sim_ticks 1169707043000 # Number of ticks simulated final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 754175 # Simulator instruction rate (inst/s) -host_op_rate 964493 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14598169556 # Simulator tick rate (ticks/s) -host_mem_usage 379804 # Number of bytes of host memory used -host_seconds 80.13 # Real time elapsed on the host +host_inst_rate 657704 # Simulator instruction rate (inst/s) +host_op_rate 841119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12730829062 # Simulator tick rate (ticks/s) +host_mem_usage 382856 # Number of bytes of host memory used +host_seconds 91.88 # Real time elapsed on the host sim_insts 60429704 # Number of instructions simulated sim_ops 77281862 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 61898788 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10078928 # Number of bytes written to this memory -system.physmem.num_reads 6478591 # Number of read requests responded to by this memory -system.physmem.num_writes 867017 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory +system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 125934 # number of replacements system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use system.l2c.total_refs 1500548 # Total number of references to valid blocks. @@ -211,12 +269,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028163 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.826789 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.710105 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.587311 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses @@ -225,6 +287,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.122213 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses @@ -233,6 +296,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.122213 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency @@ -241,12 +305,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52152.561534 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7361.740598 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 8935.230618 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52082.720239 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency @@ -255,6 +323,7 @@ system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52096.107637 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency @@ -263,6 +332,7 @@ system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52096.107637 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -372,12 +442,16 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.028163 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.826789 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710105 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.587311 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses @@ -386,6 +460,7 @@ system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.122213 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses @@ -394,6 +469,7 @@ system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.122213 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency @@ -402,12 +478,16 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40153.009531 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40051.711668 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40039.254171 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40082.720239 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency @@ -416,6 +496,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency @@ -424,16 +505,20 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -541,11 +626,17 @@ system.cpu0.icache.demand_accesses::total 29439615 # n system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,13 +664,21 @@ system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013882 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013882 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013882 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11823.686947 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 335831 # number of replacements system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use @@ -639,17 +738,29 @@ system.cpu0.dcache.demand_accesses::total 12319714 # n system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033860 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025969 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060456 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047493 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030342 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23054.541807 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23054.541807 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,20 +802,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033860 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025969 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060456 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.558127 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6149.443774 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -806,11 +932,17 @@ system.cpu1.icache.demand_accesses::total 32286236 # n system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,13 +970,21 @@ system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11684.088965 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 294642 # number of replacements system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use @@ -904,17 +1044,29 @@ system.cpu1.dcache.demand_accesses::total 12098117 # n system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.024175 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030209 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119732 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104658 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026659 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026659 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14503.858110 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 35153.999575 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11199.721298 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7579.207411 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24134.585035 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24134.585035 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -956,20 +1108,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024175 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030209 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119732 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -990,7 +1157,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index bdfa88421..6a942652a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -180,9 +181,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -241,10 +241,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -656,9 +655,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index db3a98367..b6cf436ae 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:25:42 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2591419000000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index c192aecc6..20ffbfc50 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.591419 # Nu sim_ticks 2591419000000 # Number of ticks simulated final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 632591 # Simulator instruction rate (inst/s) -host_op_rate 807921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27699122939 # Simulator tick rate (ticks/s) -host_mem_usage 380048 # Number of bytes of host memory used -host_seconds 93.56 # Real time elapsed on the host +host_inst_rate 555808 # Simulator instruction rate (inst/s) +host_op_rate 709857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24337050134 # Simulator tick rate (ticks/s) +host_mem_usage 383104 # Number of bytes of host memory used +host_seconds 106.48 # Real time elapsed on the host sim_insts 59182652 # Number of instructions simulated sim_ops 75585847 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 133632176 # Number of bytes read from this memory -system.physmem.bytes_inst_read 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9600072 # Number of bytes written to this memory -system.physmem.num_reads 15512735 # Number of read requests responded to by this memory -system.physmem.num_writes 856893 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51567182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3704562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55271744 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory +system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 117210 # number of replacements system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use system.l2c.total_refs 1536782 # Total number of references to valid blocks. @@ -131,30 +162,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002518 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003377 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016996 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.044928 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025341 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991025 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.568473 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.568473 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.002518 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.003377 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.016996 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.252085 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.115451 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.002518 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.003377 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.016996 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.252085 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.115451 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52155.074026 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 362.243121 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 362.243121 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52071.302204 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52086.639310 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52086.639310 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,35 +256,48 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.025341 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568473 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.115451 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.115451 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40154.867958 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40054.684779 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40071.298651 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -351,11 +405,17 @@ system.cpu.icache.demand_accesses::total 60464458 # nu system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14703.491239 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14703.491239 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,13 +443,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 627094 # number of replacements system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use @@ -445,15 +513,25 @@ system.cpu.dcache.demand_accesses::total 23787844 # nu system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027178 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024500 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045914 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026027 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24845.068079 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24845.068079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -491,18 +569,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -523,7 +614,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index a62c40c07..0d2987eae 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:41 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 344f40088..82168f91d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,23 +4,48 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 704165 # Simulator instruction rate (inst/s) -host_op_rate 1441828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18015373871 # Simulator tick rate (ticks/s) -host_mem_usage 378116 # Number of bytes of host memory used -host_seconds 283.76 # Real time elapsed on the host +host_inst_rate 1304311 # Simulator instruction rate (inst/s) +host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33369516688 # Simulator tick rate (ticks/s) +host_mem_usage 357276 # Number of bytes of host memory used +host_seconds 153.20 # Real time elapsed on the host sim_insts 199813913 # Number of instructions simulated sim_ops 409133277 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15568704 # Number of bytes read from this memory -system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory -system.physmem.bytes_written 12232896 # Number of bytes written to this memory -system.physmem.num_reads 243261 # Number of read requests responded to by this memory -system.physmem.num_writes 191139 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory +system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory +system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory +system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory +system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 164044 # number of replacements system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use system.l2c.total_refs 3332458 # Total number of references to valid blocks. @@ -103,16 +128,21 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -150,9 +180,13 @@ system.iocache.demand_accesses::total 47625 # nu system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -228,8 +262,11 @@ system.cpu.icache.demand_accesses::total 244157091 # nu system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -273,8 +310,11 @@ system.cpu.itb_walker_cache.demand_accesses::total 12227 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,8 +354,11 @@ system.cpu.dtb_walker_cache.demand_accesses::total 21808 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -361,9 +404,13 @@ system.cpu.dcache.demand_accesses::total 21764019 # nu system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 70b899ba9..d30404a01 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:05:12 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 92c083c66..9cc951eb3 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,23 +4,48 @@ sim_seconds 5.195470 # Nu sim_ticks 5195470393000 # Number of ticks simulated final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 435377 # Simulator instruction rate (inst/s) -host_op_rate 835677 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16374771456 # Simulator tick rate (ticks/s) -host_mem_usage 374904 # Number of bytes of host memory used -host_seconds 317.29 # Real time elapsed on the host +host_inst_rate 792632 # Simulator instruction rate (inst/s) +host_op_rate 1521406 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29811367673 # Simulator tick rate (ticks/s) +host_mem_usage 354100 # Number of bytes of host memory used +host_seconds 174.28 # Real time elapsed on the host sim_insts 138138472 # Number of instructions simulated sim_ops 265147881 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13764096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10427072 # Number of bytes written to this memory -system.physmem.num_reads 215064 # Number of read requests responded to by this memory -system.physmem.num_writes 162923 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2649249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 187548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2006954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 4656204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::pc.south_bridge.ide 2876352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 974400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9911872 # Number of bytes read from this memory +system.physmem.bytes_read::total 13764096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 974400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 974400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10427072 # Number of bytes written to this memory +system.physmem.bytes_written::total 10427072 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 15225 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 154873 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215064 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 162923 # Number of write requests responded to by this memory +system.physmem.num_writes::total 162923 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 553627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 187548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1907791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2649249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 187548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2006954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2006954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2006954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 553627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 187548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1907791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4656204 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 136133 # number of replacements system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use system.l2c.total_refs 3363370 # Total number of references to valid blocks. @@ -122,30 +147,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.024110 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.810539 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383769 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.070620 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.070620 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52255.016722 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 24673.484295 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52004.897310 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52079.246541 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52079.246541 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,33 +239,46 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001987 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027160 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.024110 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.810539 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.810539 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383769 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383769 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.070620 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.070620 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40254.652764 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40254.930606 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40004.868185 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47510 # number of replacements system.iocache.tagsinuse 0.120586 # Cycle average of tags in use @@ -266,13 +314,21 @@ system.iocache.demand_accesses::total 47564 # nu system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126274.800948 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 136801.779966 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 136614.983853 # average overall miss latency system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 136614.983853 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked @@ -300,13 +356,21 @@ system.iocache.demand_mshr_miss_latency::total 4024343976 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -378,11 +442,17 @@ system.cpu.icache.demand_accesses::total 159222590 # nu system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004953 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004953 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004953 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14812.203135 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14812.203135 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,11 +476,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 9314744000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004953 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.004953 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.004953 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3754 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use @@ -450,11 +526,17 @@ system.cpu.itb_walker_cache.demand_accesses::total 12223 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376565 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.376503 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.376503 # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881 # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,11 +560,17 @@ system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376565 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376503 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376503 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8042.372881 # average ReadReq mshr miss latency system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.replacements 7704 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use @@ -518,11 +606,17 @@ system.cpu.dtb_walker_cache.demand_accesses::total 21947 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405340 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405340 # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405340 # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629 # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,11 +640,17 @@ system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.405340 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.405340 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.405340 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8678.844424 # average ReadReq mshr miss latency system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1623424 # number of replacements system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use @@ -594,13 +694,21 @@ system.cpu.dcache.demand_accesses::total 21635359 # nu system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098647 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037778 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075163 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075163 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15144.526649 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30172.881044 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18058.802043 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18058.802043 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,16 +742,27 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098647 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037778 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.075163 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075163 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12144.494227 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27172.847747 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index fdc643fe0..ab2a707ae 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -11,7 +11,7 @@ mem_mode=atomic memories=drivesys.physmem num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/n/piton/z/nate/work/m5/work/configs/boot/netperf-server.rcS +readfile=/tmp/gem5.ali/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -138,9 +138,8 @@ master=drivesys.membus.slave[3] slave=drivesys.iobus.master[29] [drivesys.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -150,10 +149,9 @@ master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fa slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma [drivesys.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -745,7 +743,7 @@ mem_mode=atomic memories=testsys.physmem num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/n/piton/z/nate/work/m5/work/configs/boot/netperf-stream-client.rcS +readfile=/tmp/gem5.ali/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -872,9 +870,8 @@ master=testsys.membus.slave[3] slave=testsys.iobus.master[29] [testsys.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -884,10 +881,9 @@ master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_ slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma [testsys.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr index 7390a9ac7..22a941a4b 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr @@ -1,5 +1,7 @@ warn: Sockets disabled, not accepting terminal connections +warn: CoherentBus testsys.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections +warn: CoherentBus drivesys.membus has no snooping ports attached! warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Obsolete M5 ivlb instruction encountered. diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index 03a60d922..b25f011d8 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:53 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:20:01 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 7cbeb04be..99c7b577c 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,23 +4,42 @@ sim_seconds 0.200001 # Nu sim_ticks 200000789468 # Number of ticks simulated final_tick 4300236018046 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158529438 # Simulator instruction rate (inst/s) -host_op_rate 158527026 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115976612682 # Simulator tick rate (ticks/s) -host_mem_usage 480288 # Number of bytes of host memory used -host_seconds 1.72 # Real time elapsed on the host +host_inst_rate 165824466 # Simulator instruction rate (inst/s) +host_op_rate 165822505 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121314189503 # Simulator tick rate (ticks/s) +host_mem_usage 480536 # Number of bytes of host memory used +host_seconds 1.65 # Real time elapsed on the host sim_insts 273374833 # Number of instructions simulated sim_ops 273374833 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read 19104208 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read 14257548 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written 3887982 # Number of bytes written to this memory -testsys.physmem.num_reads 4226224 # Number of read requests responded to by this memory -testsys.physmem.num_writes 504418 # Number of write requests responded to by this memory -testsys.physmem.num_other 0 # Number of other requests responded to by this memory -testsys.physmem.bw_read 95520663 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read 71287459 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write 19439833 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total 114960496 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bytes_read::cpu.inst 14257548 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 4845244 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 1416 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 19104208 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 14257548 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 14257548 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 3887080 # Number of bytes written to this memory +testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory +testsys.physmem.bytes_written::total 3887982 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 3564387 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 661796 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 41 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 4226224 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 504387 # Number of write requests responded to by this memory +testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory +testsys.physmem.num_writes::total 504418 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 71287459 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 24226124 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 7080 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 95520663 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 71287459 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 71287459 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 19435323 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::tsunami.ethernet 4510 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::total 19439833 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 71287459 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 43661448 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 11590 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 114960496 # Total bandwidth to/from this memory (bytes/s) testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -109,6 +128,7 @@ testsys.cpu.kern.ipl_used::0 0.998814 # fr testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.839651 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -150,7 +170,7 @@ testsys.cpu.kern.mode_good::idle 5 testsys.cpu.kern.mode_switch_good::kernel 0.595086 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 1.608210 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::total 0.614373 # fraction of useful protection mode switches testsys.cpu.kern.mode_ticks::kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::user 1065606 1.23% 3.32% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 83963628 96.68% 100.00% # number of ticks spent at the given mode @@ -204,16 +224,35 @@ testsys.tsunami.ethernet.totalRxOrn 0 # to testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read 10620314 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read 7834952 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written 1607724 # Number of bytes written to this memory -drivesys.physmem.num_reads 2352907 # Number of read requests responded to by this memory -drivesys.physmem.num_writes 230617 # Number of write requests responded to by this memory -drivesys.physmem.num_other 0 # Number of other requests responded to by this memory -drivesys.physmem.bw_read 53101360 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read 39174605 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write 8038588 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total 61139949 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bytes_read::cpu.inst 7834952 # Number of bytes read from this memory +drivesys.physmem.bytes_read::cpu.data 2784156 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 1206 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 10620314 # Number of bytes read from this memory +drivesys.physmem.bytes_inst_read::cpu.inst 7834952 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_inst_read::total 7834952 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_written::cpu.data 1606660 # Number of bytes written to this memory +drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory +drivesys.physmem.bytes_written::total 1607724 # Number of bytes written to this memory +drivesys.physmem.num_reads::cpu.inst 1958738 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::cpu.data 394136 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 33 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 2352907 # Number of read requests responded to by this memory +drivesys.physmem.num_writes::cpu.data 230580 # Number of write requests responded to by this memory +drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory +drivesys.physmem.num_writes::total 230617 # Number of write requests responded to by this memory +drivesys.physmem.bw_read::cpu.inst 39174605 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 13920725 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 6030 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 53101360 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 39174605 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 39174605 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 8033268 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::tsunami.ethernet 5320 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::total 8038588 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 39174605 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 21953993 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 11350 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 61139949 # Total bandwidth to/from this memory (bytes/s) drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -302,6 +341,7 @@ drivesys.cpu.kern.ipl_used::0 1 # fr drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::31 0.426624 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::total 0.618707 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed @@ -333,7 +373,7 @@ drivesys.cpu.kern.mode_good::idle 3 drivesys.cpu.kern.mode_switch_good::kernel 0.632184 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::idle 0.013761 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 1.645945 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::total 0.440882 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks::kernel 263256 0.24% 0.24% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::user 1278343 1.15% 1.39% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 109686421 98.61% 100.00% # number of ticks spent at the given mode @@ -395,19 +435,13 @@ sim_seconds 0.000001 # Nu sim_ticks 785978 # Number of ticks simulated final_tick 4300236804024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 518678770918 # Simulator instruction rate (inst/s) -host_op_rate 495238879650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1368243673 # Simulator tick rate (ticks/s) -host_mem_usage 480288 # Number of bytes of host memory used +host_inst_rate 831242365640 # Simulator instruction rate (inst/s) +host_op_rate 739004692869 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2025669508 # Simulator tick rate (ticks/s) +host_mem_usage 480536 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host sim_insts 273374833 # Number of instructions simulated sim_ops 273374833 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read 0 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written 0 # Number of bytes written to this memory -testsys.physmem.num_reads 0 # Number of read requests responded to by this memory -testsys.physmem.num_writes 0 # Number of write requests responded to by this memory -testsys.physmem.num_other 0 # Number of other requests responded to by this memory testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -522,12 +556,6 @@ testsys.tsunami.ethernet.totalRxOrn 0 # to testsys.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read 0 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written 0 # Number of bytes written to this memory -drivesys.physmem.num_reads 0 # Number of read requests responded to by this memory -drivesys.physmem.num_writes 0 # Number of write requests responded to by this memory -drivesys.physmem.num_other 0 # Number of other requests responded to by this memory drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index 1a7fdb0b3..5cc0911e9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index 69eabeb32..b9f1a2caf 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:08 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:15:31 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index c4f4b062b..6887d118d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000021 # Nu sim_ticks 21234500 # Number of ticks simulated final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 37422 # Simulator instruction rate (inst/s) -host_op_rate 37415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 124041463 # Simulator tick rate (ticks/s) -host_mem_usage 214024 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 73768 # Simulator instruction rate (inst/s) +host_op_rate 73752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 244499363 # Simulator tick rate (ticks/s) +host_mem_usage 214444 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30016 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 469 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1413548706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 907202901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1413548706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory +system.physmem.bytes_read::total 30016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 469 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 907202901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 506345805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1413548706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 907202901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 907202901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 907202901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 506345805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1413548706 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -155,11 +162,17 @@ system.cpu.icache.demand_accesses::total 908 # nu system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55267.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55267.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,11 +200,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 16051500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use @@ -235,13 +254,21 @@ system.cpu.dcache.demand_accesses::total 2050 # nu system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081857 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289017 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.169268 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54220 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54935.158501 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54935.158501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -275,13 +302,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9022500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use @@ -335,18 +370,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 168 system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,18 +422,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index f1e336f90..280f44c05 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index a5a801059..bcee17b83 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:03:27 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index ff51eef95..e9f17ec08 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000012 # Nu sim_ticks 12450500 # Number of ticks simulated final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42940 # Simulator instruction rate (inst/s) -host_op_rate 42933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83690683 # Simulator tick rate (ticks/s) -host_mem_usage 215012 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 73568 # Simulator instruction rate (inst/s) +host_op_rate 73552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 143373020 # Simulator tick rate (ticks/s) +host_mem_usage 215332 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 31360 # Number of bytes read from this memory -system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 490 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory +system.physmem.bytes_read::total 31360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory +system.physmem.num_reads::total 490 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -356,11 +363,17 @@ system.cpu.icache.demand_accesses::total 2367 # nu system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,11 +401,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 11133500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use @@ -436,13 +455,21 @@ system.cpu.dcache.demand_accesses::total 2744 # nu system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,13 +503,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6297500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use @@ -536,18 +571,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 176 system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,18 +623,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini index 73aad5a2d..6e91910a0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout index fcc8cf92e..1bf93074b 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:46:44 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index d2827f261..d49eba0fa 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 3215000 # Number of ticks simulated final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 399216 # Simulator instruction rate (inst/s) -host_op_rate 398861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 200076048 # Simulator tick rate (ticks/s) -host_mem_usage 204908 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 1264163 # Simulator instruction rate (inst/s) +host_op_rate 1259559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 630191855 # Simulator tick rate (ticks/s) +host_mem_usage 205200 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10718506998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7980093313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2082737170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12801244168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7980093313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2738413686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10718506998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7980093313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7980093313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2082737170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2082737170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7980093313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4821150855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12801244168 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index ad599d493..a36a875c9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:34 +Real time: Jun/04/2012 13:42:36 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.34 -Virtual_time_in_minutes: 0.00566667 -Virtual_time_in_hours: 9.44444e-05 -Virtual_time_in_days: 3.93519e-06 +Virtual_time_in_seconds: 0.43 +Virtual_time_in_minutes: 0.00716667 +Virtual_time_in_hours: 0.000119444 +Virtual_time_in_days: 4.97685e-06 Ruby_current_time: 279353 Ruby_start_time: 0 Ruby_cycles: 279353 -mbytes_resident: 48.7227 -mbytes_total: 220.605 -resident_ratio: 0.220859 +mbytes_resident: 49.4727 +mbytes_total: 221.031 +resident_ratio: 0.223827 ruby_cycles_executed: [ 279354 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12930 -page_faults: 0 +page_reclaims: 13079 +page_faults: 9 swaps: 0 -block_inputs: 8 -block_outputs: 88 +block_inputs: 1264 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index 5a83168a9..0c7f2991f 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 13:42:35 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index f4fb755b0..bae589857 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000279 # Nu sim_ticks 279353 # Number of ticks simulated final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 40898 # Simulator instruction rate (inst/s) -host_op_rate 40895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1783759 # Simulator tick rate (ticks/s) -host_mem_usage 225904 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 12119 # Simulator instruction rate (inst/s) +host_op_rate 12118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 528605 # Simulator tick rate (ticks/s) +host_mem_usage 226340 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 123356470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 91840789 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 23969673 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 147326143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91840789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 31515681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 123356470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91840789 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91840789 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 23969673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 23969673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91840789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 55485354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 147326143 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 122dbb303..cc70c5701 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:38 +Real time: Jun/04/2012 14:41:05 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.36 -Virtual_time_in_minutes: 0.006 -Virtual_time_in_hours: 0.0001 -Virtual_time_in_days: 4.16667e-06 +Virtual_time_in_seconds: 0.44 +Virtual_time_in_minutes: 0.00733333 +Virtual_time_in_hours: 0.000122222 +Virtual_time_in_days: 5.09259e-06 Ruby_current_time: 223694 Ruby_start_time: 0 Ruby_cycles: 223694 -mbytes_resident: 48.6758 -mbytes_total: 220.844 -resident_ratio: 0.220408 +mbytes_resident: 49.4922 +mbytes_total: 221.148 +resident_ratio: 0.223796 ruby_cycles_executed: [ 223695 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12940 -page_faults: 0 +page_reclaims: 13086 +page_faults: 12 swaps: 0 -block_inputs: 8 -block_outputs: 88 +block_inputs: 1728 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index 4a55f22f7..691f6347c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:04 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index b6ec472df..ddb3e7d12 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000224 # Nu sim_ticks 223694 # Number of ticks simulated final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 36304 # Simulator instruction rate (inst/s) -host_op_rate 36301 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1267928 # Simulator tick rate (ticks/s) -host_mem_usage 226148 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 30014 # Simulator instruction rate (inst/s) +host_op_rate 30012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1048235 # Simulator tick rate (ticks/s) +host_mem_usage 226460 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 154049729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 114692392 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 29933749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 183983477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 114692392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39357336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 154049729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 114692392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 114692392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 29933749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 29933749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 114692392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 69291085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 183983477 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 75506a0a9..7f8f438c6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:41 +Real time: Jun/04/2012 14:42:12 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.3 -Virtual_time_in_minutes: 0.005 -Virtual_time_in_hours: 8.33333e-05 -Virtual_time_in_days: 3.47222e-06 +Virtual_time_in_seconds: 0.35 +Virtual_time_in_minutes: 0.00583333 +Virtual_time_in_hours: 9.72222e-05 +Virtual_time_in_days: 4.05093e-06 Ruby_current_time: 231701 Ruby_start_time: 0 Ruby_cycles: 231701 -mbytes_resident: 46.9062 -mbytes_total: 219.027 -resident_ratio: 0.214157 +mbytes_resident: 47.9062 +mbytes_total: 219.422 +resident_ratio: 0.218329 ruby_cycles_executed: [ 231702 ] @@ -127,11 +127,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12491 -page_faults: 0 +page_reclaims: 12630 +page_faults: 12 swaps: 0 -block_inputs: 16 -block_outputs: 88 +block_inputs: 1736 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index b67f551de..63d892f7f 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:41 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:12 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 4bd1591ab..9ad88fcd3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000232 # Nu sim_ticks 231701 # Number of ticks simulated final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 57269 # Simulator instruction rate (inst/s) -host_op_rate 57262 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2071522 # Simulator tick rate (ticks/s) -host_mem_usage 224288 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 50012 # Simulator instruction rate (inst/s) +host_op_rate 50005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1808952 # Simulator tick rate (ticks/s) +host_mem_usage 224692 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 148726160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 110728914 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 28899314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 177625474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 110728914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37997246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 148726160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110728914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110728914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 28899314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28899314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110728914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66896561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177625474 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats index 24c3821ed..68ec07392 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:31 +Real time: Jun/04/2012 13:41:27 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.31 -Virtual_time_in_minutes: 0.00516667 -Virtual_time_in_hours: 8.61111e-05 -Virtual_time_in_days: 3.58796e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 208400 Ruby_start_time: 0 Ruby_cycles: 208400 -mbytes_resident: 46.2461 -mbytes_total: 218.586 -resident_ratio: 0.211569 +mbytes_resident: 47.2969 +mbytes_total: 218.926 +resident_ratio: 0.216041 ruby_cycles_executed: [ 208401 ] @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12336 -page_faults: 10 +page_reclaims: 12505 +page_faults: 5 swaps: 0 -block_inputs: 1632 -block_outputs: 88 +block_inputs: 1000 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 7aaac31e8..f1ba4ed84 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:41:27 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 30017b1e1..842792d27 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000208 # Nu sim_ticks 208400 # Number of ticks simulated final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 60692 # Simulator instruction rate (inst/s) -host_op_rate 60683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1974491 # Simulator tick rate (ticks/s) -host_mem_usage 223836 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 52133 # Simulator instruction rate (inst/s) +host_op_rate 52125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1696034 # Simulator tick rate (ticks/s) +host_mem_usage 224184 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 165355086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 123109405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 32130518 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 197485605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 123109405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 42245681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 165355086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 123109405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 123109405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 32130518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 32130518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats index e165866f9..dd0f48010 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:37:08 +Real time: Jun/04/2012 13:42:47 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.5 -Virtual_time_in_minutes: 0.00833333 -Virtual_time_in_hours: 0.000138889 -Virtual_time_in_days: 5.78704e-06 +Virtual_time_in_seconds: 0.35 +Virtual_time_in_minutes: 0.00583333 +Virtual_time_in_hours: 9.72222e-05 +Virtual_time_in_days: 4.05093e-06 Ruby_current_time: 342698 Ruby_start_time: 0 Ruby_cycles: 342698 -mbytes_resident: 47.6289 -mbytes_total: 219.488 -resident_ratio: 0.217 +mbytes_resident: 48.4648 +mbytes_total: 219.84 +resident_ratio: 0.220455 ruby_cycles_executed: [ 342699 ] @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12667 +page_reclaims: 12835 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 5e2ce6170..0b4993316 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:08 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:46 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 333553551..a6b69bd54 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000343 # Nu sim_ticks 342698 # Number of ticks simulated final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 30902 # Simulator instruction rate (inst/s) -host_op_rate 30898 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1653235 # Simulator tick rate (ticks/s) -host_mem_usage 224760 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 17946 # Simulator instruction rate (inst/s) +host_op_rate 17945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 960252 # Simulator tick rate (ticks/s) +host_mem_usage 225120 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 100555008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 74864750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 19539069 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 120094077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 74864750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 25690258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 100555008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 74864750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74864750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 19539069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 19539069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 74864750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45229327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 120094077 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index 2cc7bb879..b0aed7d88 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index 87ec501fc..00df1b420 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:42:48 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:52:31 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index cd14cede6..0370e845f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000033 # Nu sim_ticks 33007000 # Number of ticks simulated final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236370 # Simulator instruction rate (inst/s) -host_op_rate 236114 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1215776788 # Simulator tick rate (ticks/s) -host_mem_usage 213800 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 524144 # Simulator instruction rate (inst/s) +host_op_rate 523337 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2693393609 # Simulator tick rate (ticks/s) +host_mem_usage 214140 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28544 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 446 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory +system.physmem.bytes_read::total 28544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 446 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 6415 # nu system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.043492 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.043492 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.043492 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 14745000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043492 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.043492 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.043492 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 2050 # nu system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,13 +242,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8904000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use @@ -275,18 +310,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 168 system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +362,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index e812354d2..3b6b2b818 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 992260cf4..157d28a7a 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:16 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:45:03 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 28a756060..119328db2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000007 # Nu sim_ticks 7015000 # Number of ticks simulated final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31687 # Simulator instruction rate (inst/s) -host_op_rate 31676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93063477 # Simulator tick rate (ticks/s) -host_mem_usage 214220 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 16156 # Simulator instruction rate (inst/s) +host_op_rate 16154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47467285 # Simulator tick rate (ticks/s) +host_mem_usage 214556 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 17600 # Number of bytes read from this memory -system.physmem.bytes_inst_read 12096 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 275 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2508909480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2508909480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 12096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5504 # Number of bytes read from this memory +system.physmem.bytes_read::total 17600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 12096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 12096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 86 # Number of read requests responded to by this memory +system.physmem.num_reads::total 275 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1724305061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 784604419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2508909480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1724305061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 784604419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2508909480 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -355,11 +362,17 @@ system.cpu.icache.demand_accesses::total 1067 # nu system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234302 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234302 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234302 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35830 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35830 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35830 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,11 +400,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 6695500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177132 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.177132 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.177132 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use @@ -435,13 +454,21 @@ system.cpu.dcache.demand_accesses::total 972 # nu system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.157817 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184156 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184156 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36270.949721 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36270.949721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,13 +502,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3078500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.091445 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.088477 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.088477 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use @@ -529,18 +564,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 86 system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,18 +616,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 4f5452325..198cad098 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr index 31ae36f2e..bcbfa5445 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout index d7b73cec1..4dbe62d94 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:01 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:15:42 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 2f22610c9..cc1232526 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 381497 # Simulator instruction rate (inst/s) -host_op_rate 379897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 190598632 # Simulator tick rate (ticks/s) -host_mem_usage 204064 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 760610 # Simulator instruction rate (inst/s) +host_op_rate 756680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379104629 # Simulator tick rate (ticks/s) +host_mem_usage 204432 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10293641618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7969171484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1586127168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11879768786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7969171484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2324470135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10293641618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7969171484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7969171484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1586127168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1586127168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index bda71aafd..5ef992e40 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:34 +Real time: Jun/04/2012 13:42:36 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.24 -Virtual_time_in_minutes: 0.004 -Virtual_time_in_hours: 6.66667e-05 -Virtual_time_in_days: 2.77778e-06 +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 Ruby_current_time: 104867 Ruby_start_time: 0 Ruby_cycles: 104867 -mbytes_resident: 45.8906 -mbytes_total: 218.43 -resident_ratio: 0.210093 +mbytes_resident: 46.8984 +mbytes_total: 218.785 +resident_ratio: 0.214358 ruby_cycles_executed: [ 104868 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12254 -page_faults: 0 +page_reclaims: 12410 +page_faults: 4 swaps: 0 -block_inputs: 0 -block_outputs: 88 +block_inputs: 480 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index 59ad2cc4d..d8d70a93e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 13:42:35 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index bd57039cb..748d8a973 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000105 # Nu sim_ticks 104867 # Number of ticks simulated final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 38145 # Simulator instruction rate (inst/s) -host_op_rate 38137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1551633 # Simulator tick rate (ticks/s) -host_mem_usage 223676 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 4864 # Simulator instruction rate (inst/s) +host_op_rate 4864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197908 # Simulator tick rate (ticks/s) +host_mem_usage 224040 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 127361324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 98601085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 19624858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 146986182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 98601085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28760239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 127361324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 98601085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 98601085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 19624858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 19624858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 98601085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48385097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 146986182 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 232722c59..0769bb48a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:38 +Real time: Jun/04/2012 14:41:15 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.3 +Virtual_time_in_minutes: 0.005 +Virtual_time_in_hours: 8.33333e-05 +Virtual_time_in_days: 3.47222e-06 Ruby_current_time: 85418 Ruby_start_time: 0 Ruby_cycles: 85418 -mbytes_resident: 46.1016 -mbytes_total: 218.602 -resident_ratio: 0.210893 +mbytes_resident: 46.9141 +mbytes_total: 218.969 +resident_ratio: 0.21425 ruby_cycles_executed: [ 85419 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12263 +page_reclaims: 12428 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 80 +block_outputs: 88 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index fe8db74fc..dc8b54148 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:15 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 5143cdcae..07e9173f4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000085 # Nu sim_ticks 85418 # Number of ticks simulated final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 33831 # Simulator instruction rate (inst/s) -host_op_rate 33824 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1120953 # Simulator tick rate (ticks/s) -host_mem_usage 223852 # Number of bytes of host memory used +host_inst_rate 30509 # Simulator instruction rate (inst/s) +host_op_rate 30502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010829 # Simulator tick rate (ticks/s) +host_mem_usage 224228 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 156360486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 121051769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 24093282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 180453769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 121051769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35308717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 156360486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 121051769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 121051769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 24093282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24093282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index a538bb5ac..1584bb895 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:42 +Real time: Jun/04/2012 14:42:22 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.23 -Virtual_time_in_minutes: 0.00383333 -Virtual_time_in_hours: 6.38889e-05 -Virtual_time_in_days: 2.66204e-06 +Virtual_time_in_seconds: 0.27 +Virtual_time_in_minutes: 0.0045 +Virtual_time_in_hours: 7.5e-05 +Virtual_time_in_days: 3.125e-06 Ruby_current_time: 87899 Ruby_start_time: 0 Ruby_cycles: 87899 -mbytes_resident: 45.1094 -mbytes_total: 217.598 -resident_ratio: 0.207306 +mbytes_resident: 46.1055 +mbytes_total: 217.996 +resident_ratio: 0.211497 ruby_cycles_executed: [ 87900 ] @@ -127,11 +127,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12024 +page_reclaims: 12179 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 88 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index f849b0d8f..3e1c7a0df 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:41 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:22 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 253fc28f1..0b4d202c9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000088 # Nu sim_ticks 87899 # Number of ticks simulated final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 46491 # Simulator instruction rate (inst/s) -host_op_rate 46479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1584970 # Simulator tick rate (ticks/s) -host_mem_usage 222824 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 49141 # Simulator instruction rate (inst/s) +host_op_rate 49125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1675041 # Simulator tick rate (ticks/s) +host_mem_usage 223232 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 151947121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 117635013 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 23413236 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 175360357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 117635013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34312108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 151947121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 117635013 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 117635013 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 23413236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 23413236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 117635013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57725344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 175360357 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 6835e2100..f062dbc78 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:31 +Real time: Jun/04/2012 13:42:34 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.24 -Virtual_time_in_minutes: 0.004 -Virtual_time_in_hours: 6.66667e-05 -Virtual_time_in_days: 2.77778e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 78448 Ruby_start_time: 0 Ruby_cycles: 78448 -mbytes_resident: 44.707 -mbytes_total: 217.324 -resident_ratio: 0.205716 +mbytes_resident: 45.7539 +mbytes_total: 217.664 +resident_ratio: 0.210204 ruby_cycles_executed: [ 78449 ] @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11920 -page_faults: 3 +page_reclaims: 12072 +page_faults: 20 swaps: 0 -block_inputs: 824 -block_outputs: 88 +block_inputs: 2944 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 7b52a0c21..423daf7c7 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index f21155c2f..002b923d5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000078 # Nu sim_ticks 78448 # Number of ticks simulated final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 48255 # Simulator instruction rate (inst/s) -host_op_rate 48240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1468118 # Simulator tick rate (ticks/s) -host_mem_usage 222544 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 9618 # Simulator instruction rate (inst/s) +host_op_rate 9618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292754 # Simulator tick rate (ticks/s) +host_mem_usage 222892 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170252906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 131807057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26233938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 196486845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 131807057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38445849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 170252906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 131807057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 131807057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 26233938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26233938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 131807057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64679788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 196486845 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats index cc4333b9c..0115257b7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:37:51 +Real time: Jun/04/2012 14:06:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.4 -Virtual_time_in_minutes: 0.00666667 -Virtual_time_in_hours: 0.000111111 -Virtual_time_in_days: 4.62963e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 123378 Ruby_start_time: 0 Ruby_cycles: 123378 -mbytes_resident: 45.0547 -mbytes_total: 217.531 -resident_ratio: 0.207118 +mbytes_resident: 46.1406 +mbytes_total: 217.871 +resident_ratio: 0.211779 ruby_cycles_executed: [ 123379 ] @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12045 +page_reclaims: 12216 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 6ae96cee0..ef2e2d974 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:51 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:06:24 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 6c31e7bc8..d4f9035ad 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000123 # Nu sim_ticks 123378 # Number of ticks simulated final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23789 # Simulator instruction rate (inst/s) -host_op_rate 23782 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1138300 # Simulator tick rate (ticks/s) -host_mem_usage 222756 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 56001 # Simulator instruction rate (inst/s) +host_op_rate 55979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2679090 # Simulator tick rate (ticks/s) +host_mem_usage 223104 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 108252687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 83807486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 16680445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 124933132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 83807486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24445201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 108252687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 83807486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 83807486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 16680445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16680445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 83807486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 41125646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 124933132 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 1cfaa4239..3d54d7382 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index 194a972c4..803a08b4e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:39:41 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 2a4818376..fab613981 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000017 # Nu sim_ticks 16769000 # Number of ticks simulated final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149101 # Simulator instruction rate (inst/s) -host_op_rate 148981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 968734693 # Simulator tick rate (ticks/s) -host_mem_usage 212944 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 308591 # Simulator instruction rate (inst/s) +host_op_rate 307918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1999557615 # Simulator tick rate (ticks/s) +host_mem_usage 213304 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15680 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 245 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 935058739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 935058739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory +system.physmem.bytes_read::total 15680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory +system.physmem.num_reads::total 245 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 622100304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 312958435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 935058739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 622100304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 622100304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 622100304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 312958435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 935058739 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 2586 # nu system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 8639000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 709 # nu system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,13 +242,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4346000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use @@ -269,18 +304,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 82 system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -313,18 +356,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 34353ab5e..d0f59b4b6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -551,9 +551,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -584,9 +583,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index a7713ed58..9fb63a7a7 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:23:41 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 7aa4a6157..ea50665b2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000010 # Nu sim_ticks 10303500 # Number of ticks simulated final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20985 # Simulator instruction rate (inst/s) -host_op_rate 26178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46991642 # Simulator tick rate (ticks/s) -host_mem_usage 229632 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 43907 # Simulator instruction rate (inst/s) +host_op_rate 54769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98312554 # Simulator tick rate (ticks/s) +host_mem_usage 230064 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25664 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 401 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory +system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 401 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -410,11 +417,17 @@ system.cpu.icache.demand_accesses::total 2031 # nu system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,11 +455,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 9833500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use @@ -502,15 +521,25 @@ system.cpu.dcache.demand_accesses::total 2879 # nu system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,13 +575,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4693500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use @@ -609,18 +646,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 149 system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -659,18 +704,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 816c7ba86..693c71c0c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index fa47f77da..fc15b65e3 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:23:30 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 82d7d38dc..85d0d7401 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000010 # Nu sim_ticks 10303500 # Number of ticks simulated final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29431 # Simulator instruction rate (inst/s) -host_op_rate 36712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65901409 # Simulator tick rate (ticks/s) -host_mem_usage 229344 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 49511 # Simulator instruction rate (inst/s) +host_op_rate 61757 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110854808 # Simulator tick rate (ticks/s) +host_mem_usage 229756 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25664 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 401 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory +system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 401 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -365,11 +372,17 @@ system.cpu.icache.demand_accesses::total 2031 # nu system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -397,11 +410,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 9833500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use @@ -457,15 +476,25 @@ system.cpu.dcache.demand_accesses::total 2879 # nu system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,13 +530,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4693500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use @@ -564,18 +601,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 149 system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,18 +659,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 151e2cd8c..f9ef190bc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -166,9 +166,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 435d1afac..a8cf8ab9b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:24:03 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 1b101d03e..a4d8f3fa5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 415244 # Simulator instruction rate (inst/s) -host_op_rate 516464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 258032084 # Simulator tick rate (ticks/s) -host_mem_usage 219364 # Number of bytes of host memory used +host_inst_rate 760705 # Simulator instruction rate (inst/s) +host_op_rate 946184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 472746039 # Simulator tick rate (ticks/s) +host_mem_usage 219832 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3648 # Number of bytes written to this memory -system.physmem.num_reads 5771 # Number of read requests responded to by this memory -system.physmem.num_writes 924 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory +system.physmem.bytes_read::total 22944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory +system.physmem.bytes_written::total 3648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 924 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index da6096ffc..10416c8b5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 73791bcc0..f818842dc 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:23:52 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index da264e87e..44b5714ac 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 249779 # Simulator instruction rate (inst/s) -host_op_rate 311187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155712783 # Simulator tick rate (ticks/s) -host_mem_usage 219320 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 577592 # Simulator instruction rate (inst/s) +host_op_rate 718947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 359450620 # Simulator tick rate (ticks/s) +host_mem_usage 219740 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3648 # Number of bytes written to this memory -system.physmem.num_reads 5771 # Number of read requests responded to by this memory -system.physmem.num_writes 924 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory +system.physmem.bytes_read::total 22944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory +system.physmem.bytes_written::total 3648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 924 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 91f39c039..89402c0d8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index f409a27fc..a6d6adcc2 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:24:13 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 55e20828c..0449db647 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000026 # Nu sim_ticks 26361000 # Number of ticks simulated final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148609 # Simulator instruction rate (inst/s) -host_op_rate 184448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 855039933 # Simulator tick rate (ticks/s) -host_mem_usage 228200 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 366471 # Simulator instruction rate (inst/s) +host_op_rate 454532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2105652624 # Simulator tick rate (ticks/s) +host_mem_usage 228652 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4574 # Number of instructions simulated sim_ops 5682 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 22400 # Number of bytes read from this memory -system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 350 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 849740146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 546261523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 849740146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory +system.physmem.bytes_read::total 22400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 350 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 546261523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 303478624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 849740146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546261523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546261523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546261523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 303478624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 849740146 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total 4614 # nu system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052232 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052232 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53211.618257 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53211.618257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12101000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052232 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052232 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use @@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total 2060 # nu system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085440 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.068447 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.068447 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51234.042553 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51234.042553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,13 +260,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6801000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085440 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.068447 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.068447 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use @@ -296,18 +331,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 141 system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,18 +383,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index 6db06c5ff..ee123d638 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 8cbac12cb..40197f717 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:16 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 2d3519846..705e8dbde 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000020 # Nu sim_ticks 19775000 # Number of ticks simulated final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83973 # Simulator instruction rate (inst/s) -host_op_rate 83956 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 284866754 # Simulator tick rate (ticks/s) -host_mem_usage 214812 # Number of bytes of host memory used +host_inst_rate 79967 # Simulator instruction rate (inst/s) +host_op_rate 79947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 271245925 # Simulator tick rate (ticks/s) +host_mem_usage 215348 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29120 # Number of bytes read from this memory -system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 455 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1472566372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1025941846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1472566372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 29120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 455 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1025941846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 446624526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1472566372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025941846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025941846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025941846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 446624526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1472566372 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -141,11 +148,17 @@ system.cpu.icache.demand_accesses::total 754 # nu system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.454907 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.454907 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.454907 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.454907 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.454907 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.454907 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55768.221574 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55768.221574 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55768.221574 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,11 +186,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 16951500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16951500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 16951500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53139.498433 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53139.498433 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53139.498433 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.746602 # Cycle average of tags in use @@ -221,13 +240,21 @@ system.cpu.dcache.demand_accesses::total 2089 # nu system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076460 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076460 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.175135 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.120153 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.120153 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56994.382022 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55003.086420 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55709.163347 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55709.163347 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -261,13 +288,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7448000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7448000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54051.724138 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53833.333333 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53971.014493 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53971.014493 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 205.517886 # Cycle average of tags in use @@ -321,18 +356,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995074 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995624 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52400.990099 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52588.235294 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52421.978022 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52421.978022 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,18 +408,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40215.346535 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40352.941176 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40230.769231 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40230.769231 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 5535b7c1b..a70bd3d3a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 6efd85bce..c92fa97a1 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:27 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 0f84e872e..69e82fc15 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000013 # Nu sim_ticks 12671500 # Number of ticks simulated final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56172 # Simulator instruction rate (inst/s) -host_op_rate 56163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137660070 # Simulator tick rate (ticks/s) -host_mem_usage 215596 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 63611 # Simulator instruction rate (inst/s) +host_op_rate 63597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155871053 # Simulator tick rate (ticks/s) +host_mem_usage 216124 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 483 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 30912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -340,11 +347,17 @@ system.cpu.icache.demand_accesses::total 2039 # nu system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -372,11 +385,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12065000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use @@ -420,13 +439,21 @@ system.cpu.dcache.demand_accesses::total 2944 # nu system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -460,13 +487,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5113000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use @@ -520,18 +555,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 142 system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,18 +607,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index b0d54d9f2..bb362afce 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index 289fd9d0d..43669dc21 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:38 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 91924afa4..fa97a6f47 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2913500 # Number of ticks simulated final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 826404 # Simulator instruction rate (inst/s) -host_op_rate 824787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 411656542 # Simulator tick rate (ticks/s) -host_mem_usage 205596 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 1277439 # Simulator instruction rate (inst/s) +host_op_rate 1267147 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 631162418 # Simulator tick rate (ticks/s) +host_mem_usage 206236 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27687 # Number of bytes read from this memory -system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3658 # Number of bytes written to this memory -system.physmem.num_reads 6992 # Number of read requests responded to by this memory -system.physmem.num_writes 925 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9503003261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 8001372919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1255534580 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10758537841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 23312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4375 # Number of bytes read from this memory +system.physmem.bytes_read::total 27687 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3658 # Number of bytes written to this memory +system.physmem.bytes_written::total 3658 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5828 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6992 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory +system.physmem.num_writes::total 925 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8001372919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1501630342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9503003261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8001372919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8001372919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1255534580 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1255534580 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8001372919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2757164922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10758537841 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index 4fad25b5f..9ce456b52 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:59 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index b950c6483..1e3413864 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000293 # Nu sim_ticks 292960 # Number of ticks simulated final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 60937 # Simulator instruction rate (inst/s) -host_op_rate 60929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3062846 # Simulator tick rate (ticks/s) -host_mem_usage 226192 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 55490 # Simulator instruction rate (inst/s) +host_op_rate 55480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2788890 # Simulator tick rate (ticks/s) +host_mem_usage 226736 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27687 # Number of bytes read from this memory -system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3658 # Number of bytes written to this memory -system.physmem.num_reads 6992 # Number of read requests responded to by this memory -system.physmem.num_writes 925 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 94507783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 79574003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 12486346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 106994129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 23312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4375 # Number of bytes read from this memory +system.physmem.bytes_read::total 27687 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3658 # Number of bytes written to this memory +system.physmem.bytes_written::total 3658 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5828 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6992 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory +system.physmem.num_writes::total 925 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 79574003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14933779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 94507783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 79574003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 79574003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 12486346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12486346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 79574003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 27420126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106994129 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index c6b1fd816..f7cc4efef 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 0276ca4b7..ac53df969 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:48 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 6c79a4c95..8f49928a9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000032 # Nu sim_ticks 32088000 # Number of ticks simulated final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 273601 # Simulator instruction rate (inst/s) -host_op_rate 273420 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504754975 # Simulator tick rate (ticks/s) -host_mem_usage 214572 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 540307 # Simulator instruction rate (inst/s) +host_op_rate 539410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2965678153 # Simulator tick rate (ticks/s) +host_mem_usage 215020 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 439 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 28096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 439 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 600349040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 275243082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 875592122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 600349040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 600349040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 600349040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 275243082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 875592122 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -95,11 +102,17 @@ system.cpu.icache.demand_accesses::total 5829 # nu system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.051981 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.051981 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.051981 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -121,11 +134,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 15975000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.051981 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.051981 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.051981 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use @@ -169,13 +188,21 @@ system.cpu.dcache.demand_accesses::total 2089 # nu system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.074742 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.066060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.066060 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -201,13 +228,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7314000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use @@ -261,18 +296,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,18 +348,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index b22bc0367..928f0469f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -475,9 +475,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -508,9 +507,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 7aac87cd9..b797dcfe3 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:03:54 -gem5 started May 8 2012 15:36:49 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:59:33 +gem5 started Jun 4 2012 14:44:10 +gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 129f4d9d2..975867801 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000011 # Nu sim_ticks 11243500 # Number of ticks simulated final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73653 # Simulator instruction rate (inst/s) -host_op_rate 73641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 142731766 # Simulator tick rate (ticks/s) -host_mem_usage 211540 # Number of bytes of host memory used +host_inst_rate 72271 # Simulator instruction rate (inst/s) +host_op_rate 72256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140039967 # Simulator tick rate (ticks/s) +host_mem_usage 211876 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28736 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 449 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory +system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -339,11 +346,17 @@ system.cpu.icache.demand_accesses::total 1899 # nu system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,11 +384,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12417500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use @@ -419,13 +438,21 @@ system.cpu.dcache.demand_accesses::total 2615 # nu system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,13 +486,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3570000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use @@ -519,18 +554,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 99 system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,18 +606,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index 0a48b581e..aaab5c18b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -95,9 +95,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index 4ba999389..b409adbd2 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:03:54 -gem5 started May 8 2012 15:36:50 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:59:33 +gem5 started Jun 4 2012 14:44:21 +gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 87b1b3e66..c355893c5 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2900000 # Number of ticks simulated final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 413372 # Simulator instruction rate (inst/s) -host_op_rate 412979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206267825 # Simulator tick rate (ticks/s) -host_mem_usage 201744 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 1223636 # Simulator instruction rate (inst/s) +host_op_rate 1219143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 607261041 # Simulator tick rate (ticks/s) +host_mem_usage 202160 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5801 # Number of instructions simulated sim_ops 5801 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26925 # Number of bytes read from this memory -system.physmem.bytes_inst_read 23204 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4209 # Number of bytes written to this memory -system.physmem.num_reads 6763 # Number of read requests responded to by this memory -system.physmem.num_writes 1046 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9284482759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 8001379310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1451379310 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10735862069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 23204 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3721 # Number of bytes read from this memory +system.physmem.bytes_read::total 26925 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23204 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23204 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 4209 # Number of bytes written to this memory +system.physmem.bytes_written::total 4209 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6763 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1046 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8001379310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1283103448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9284482759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8001379310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8001379310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1451379310 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1451379310 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8001379310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2734482759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10735862069 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 61b03b911..d62e06b17 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 19ecb4795..76c88733e 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:31 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 5aea2d352..b45b5b881 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000018 # Nu sim_ticks 18196500 # Number of ticks simulated final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72963 # Simulator instruction rate (inst/s) -host_op_rate 72948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 248531385 # Simulator tick rate (ticks/s) -host_mem_usage 221204 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 58781 # Simulator instruction rate (inst/s) +host_op_rate 58769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 200221364 # Simulator tick rate (ticks/s) +host_mem_usage 221628 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27072 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 423 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1487758635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1016459209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1487758635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory +system.physmem.bytes_read::total 27072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1016459209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 471299426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1487758635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1016459209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1016459209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1016459209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 471299426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1487758635 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 36394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -123,11 +130,17 @@ system.cpu.icache.demand_accesses::total 1174 # nu system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.295571 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.295571 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.295571 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55063.400576 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55063.400576 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55063.400576 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -155,11 +168,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 15468000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247871 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247871 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247871 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53154.639175 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use @@ -203,13 +222,21 @@ system.cpu.dcache.demand_accesses::total 1389 # nu system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082402 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.417533 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.244780 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.244780 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55788.135593 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55010.676157 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55145.588235 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55145.588235 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -243,13 +270,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7193500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53074.074074 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53425.925926 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53285.185185 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53285.185185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use @@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 135 system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52390.350877 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52228.395062 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52359.338061 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52359.338061 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40195.906433 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40191.358025 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index 3550cbb34..9462bf460 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 467d94a16..a096c2705 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:41 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index a0bb29684..c78599e75 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2701000 # Number of ticks simulated final_tick 2701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 660534 # Simulator instruction rate (inst/s) -host_op_rate 659359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 332979355 # Simulator tick rate (ticks/s) -host_mem_usage 211860 # Number of bytes of host memory used +host_inst_rate 947128 # Simulator instruction rate (inst/s) +host_op_rate 944143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 476131381 # Simulator tick rate (ticks/s) +host_mem_usage 212364 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26135 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5065 # Number of bytes written to this memory -system.physmem.num_reads 6099 # Number of read requests responded to by this memory -system.physmem.num_writes 673 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9676045909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7971862273 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1875231396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11551277305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4603 # Number of bytes read from this memory +system.physmem.bytes_read::total 26135 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21532 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory +system.physmem.bytes_written::total 5065 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 716 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6099 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory +system.physmem.num_writes::total 673 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7971862273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1704183636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9676045909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7971862273 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7971862273 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1875231396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1875231396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7971862273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3579415031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11551277305 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 5403 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index 5940396eb..095eef676 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:55 +Real time: Jun/04/2012 14:44:51 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.28 -Virtual_time_in_minutes: 0.00466667 -Virtual_time_in_hours: 7.77778e-05 -Virtual_time_in_days: 3.24074e-06 +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 Ruby_current_time: 253364 Ruby_start_time: 0 Ruby_cycles: 253364 -mbytes_resident: 48.3438 -mbytes_total: 226.668 -resident_ratio: 0.21328 +mbytes_resident: 49.3359 +mbytes_total: 227.086 +resident_ratio: 0.217257 ruby_cycles_executed: [ 253365 ] @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12864 +page_reclaims: 13015 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index dd8a0a7b3..e4a7b2f0d 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:51 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 362724c03..2f30e2be2 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000253 # Nu sim_ticks 253364 # Number of ticks simulated final_tick 253364 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 60301 # Simulator instruction rate (inst/s) -host_op_rate 60291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2860139 # Simulator tick rate (ticks/s) -host_mem_usage 232112 # Number of bytes of host memory used +host_inst_rate 57491 # Simulator instruction rate (inst/s) +host_op_rate 57480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2726732 # Simulator tick rate (ticks/s) +host_mem_usage 232540 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26135 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5065 # Number of bytes written to this memory -system.physmem.num_reads 6099 # Number of read requests responded to by this memory -system.physmem.num_writes 673 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 103151987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 84984449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 19991001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 123142988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4603 # Number of bytes read from this memory +system.physmem.bytes_read::total 26135 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21532 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory +system.physmem.bytes_written::total 5065 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 716 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6099 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory +system.physmem.num_writes::total 673 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84984449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 18167538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103151987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84984449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84984449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 19991001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 19991001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84984449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38158539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 123142988 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 253364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 958c9bb97..232d3350e 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index 702411d18..e4af58bc7 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:42 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index d2987c02e..3580b75db 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000028 # Nu sim_ticks 28206000 # Number of ticks simulated final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240215 # Simulator instruction rate (inst/s) -host_op_rate 240049 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1267195715 # Simulator tick rate (ticks/s) -host_mem_usage 220748 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 427855 # Simulator instruction rate (inst/s) +host_op_rate 427237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2253599179 # Simulator tick rate (ticks/s) +host_mem_usage 221156 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 24896 # Number of bytes read from this memory -system.physmem.bytes_inst_read 16320 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 389 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 882649082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 578600298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 882649082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory +system.physmem.bytes_read::total 24896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 389 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 578600298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 304048784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 882649082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 578600298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 578600298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 578600298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 304048784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 882649082 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 56412 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 5384 # nu system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.047734 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.047734 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.047734 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55673.151751 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55673.151751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 13537000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047734 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.047734 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.047734 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use @@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total 1389 # nu system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075419 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.097192 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097192 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097192 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097192 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55688.888889 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55688.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -183,13 +210,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7113000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use @@ -246,18 +281,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 135 system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,18 +333,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ebb140a84..19d634444 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:03:58 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 5a009d0f1..b16a10afa 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000012 # Nu sim_ticks 12198000 # Number of ticks simulated final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27776 # Simulator instruction rate (inst/s) -host_op_rate 50299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62542635 # Simulator tick rate (ticks/s) -host_mem_usage 245428 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 39950 # Simulator instruction rate (inst/s) +host_op_rate 72345 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89952499 # Simulator tick rate (ticks/s) +host_mem_usage 224288 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 451 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory +system.physmem.bytes_read::total 28864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 24397 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -321,11 +328,17 @@ system.cpu.icache.demand_accesses::total 1951 # nu system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,11 +366,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 10687000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.155818 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use @@ -401,13 +420,21 @@ system.cpu.dcache.demand_accesses::total 2556 # nu system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -439,13 +466,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5263500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.058294 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.058294 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use @@ -499,18 +534,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 149 system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994695 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995585 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995585 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34250 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,18 +586,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 0daaf6112..85d4b3244 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:09 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 2c5d9e840..971607574 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000006 # Nu sim_ticks 5651000 # Number of ticks simulated final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 8235 # Simulator instruction rate (inst/s) -host_op_rate 14913 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8590426 # Simulator tick rate (ticks/s) -host_mem_usage 234908 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host +host_inst_rate 420667 # Simulator instruction rate (inst/s) +host_op_rate 760787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 437668419 # Simulator tick rate (ticks/s) +host_mem_usage 214072 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62348 # Number of bytes read from this memory -system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7110 # Number of bytes written to this memory -system.physmem.num_reads 7966 # Number of read requests responded to by this memory -system.physmem.num_writes 934 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11033091488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 9782339409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1258184392 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12291275880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 55280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7068 # Number of bytes read from this memory +system.physmem.bytes_read::total 62348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory +system.physmem.bytes_written::total 7110 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1056 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7966 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory +system.physmem.num_writes::total 934 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9782339409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1250752079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11033091488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9782339409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9782339409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1258184392 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1258184392 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9782339409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2508936471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12291275880 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 11303 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index a0ea73428..400138927 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jun/03/2012 13:31:00 +Real time: Jun/04/2012 15:04:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.36 +Virtual_time_in_minutes: 0.006 +Virtual_time_in_hours: 0.0001 +Virtual_time_in_days: 4.16667e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 52.5547 -mbytes_total: 249.254 -resident_ratio: 0.210848 +mbytes_resident: 52.9648 +mbytes_total: 228.941 +resident_ratio: 0.232473 ruby_cycles_executed: [ 276485 ] @@ -125,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11223 +page_reclaims: 14034 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index bef47caec..781f2a777 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:30 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 436ded977..37cc5b98f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000276 # Nu sim_ticks 276484 # Number of ticks simulated final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 34222 # Simulator instruction rate (inst/s) -host_op_rate 61969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1746397 # Simulator tick rate (ticks/s) -host_mem_usage 255240 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 48659 # Simulator instruction rate (inst/s) +host_op_rate 88106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2482786 # Simulator tick rate (ticks/s) +host_mem_usage 234440 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62348 # Number of bytes read from this memory -system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7110 # Number of bytes written to this memory -system.physmem.num_reads 7966 # Number of read requests responded to by this memory -system.physmem.num_writes 934 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 225503103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199939237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 25715774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 251218877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 55280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7068 # Number of bytes read from this memory +system.physmem.bytes_read::total 62348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory +system.physmem.bytes_written::total 7110 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1056 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7966 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory +system.physmem.num_writes::total 934 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 199939237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 25563866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 225503103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199939237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199939237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 25715774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25715774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199939237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51279640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 251218877 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 276484 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 91d5c9297..62a044b81 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:19 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 2325f81a1..1e89d36d4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000029 # Nu sim_ticks 28768000 # Number of ticks simulated final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39729 # Simulator instruction rate (inst/s) -host_op_rate 71940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 210944443 # Simulator tick rate (ticks/s) -host_mem_usage 244104 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 318234 # Simulator instruction rate (inst/s) +host_op_rate 575684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1686451163 # Simulator tick rate (ticks/s) +host_mem_usage 223048 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 23104 # Number of bytes read from this memory -system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 361 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory +system.physmem.bytes_read::total 23104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 361 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 505005562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 298109010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 803114572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 505005562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505005562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 505005562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 298109010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 803114572 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 57536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 6911 # nu system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032991 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.032991 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.032991 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12042000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032991 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.032991 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.032991 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use @@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total 1990 # nu system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052083 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067337 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067337 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -183,13 +210,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7102000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052083 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084582 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067337 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067337 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use @@ -243,18 +278,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 134 system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -287,18 +330,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 60ac42ca2..01d2e4278 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -526,9 +525,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index c897f1e4e..0e67a0bd3 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:40:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:39:51 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 244839beb..972719e56 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000014 # Nu sim_ticks 13973500 # Number of ticks simulated final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43715 # Simulator instruction rate (inst/s) -host_op_rate 43711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47815570 # Simulator tick rate (ticks/s) -host_mem_usage 215652 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 68487 # Simulator instruction rate (inst/s) +host_op_rate 68480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74908448 # Simulator tick rate (ticks/s) +host_mem_usage 215960 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated sim_ops 12773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62784 # Number of bytes read from this memory -system.physmem.bytes_inst_read 40192 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 981 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 4493076180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2876301571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 4493076180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 40192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22592 # Number of bytes read from this memory +system.physmem.bytes_read::total 62784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40192 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 353 # Number of read requests responded to by this memory +system.physmem.num_reads::total 981 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2876301571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1616774609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4493076180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2876301571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2876301571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2876301571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1616774609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4493076180 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -383,7 +390,7 @@ system.cpu.iew.wb_rate::1 0.345356 # in system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 1.530777 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.765387 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ @@ -500,11 +507,17 @@ system.cpu.icache.demand_accesses::total 5262 # nu system.cpu.icache.overall_accesses::cpu.inst 5262 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5262 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169707 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.169707 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.169707 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.169707 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.169707 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.169707 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35538.633819 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35538.633819 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35538.633819 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35538.633819 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,11 +545,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 22442500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22442500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 22442500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119916 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.119916 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.119916 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.561014 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35566.561014 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements @@ -582,13 +601,21 @@ system.cpu.dcache.demand_accesses::total 5717 # nu system.cpu.dcache.overall_accesses::cpu.data 5717 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 5717 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078004 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078004 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.410405 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.178590 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.178590 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.178590 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.178590 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36080.385852 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36080.385852 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31737.323944 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31737.323944 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33060.235064 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33060.235064 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -622,13 +649,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 12899000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12899000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12899000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051919 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051919 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061746 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061746 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36751.207729 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36751.207729 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36243.150685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36243.150685 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements @@ -684,18 +719,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 353 system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995246 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.996420 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995246 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.996951 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995246 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.996951 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34452.229299 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34859.903382 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34553.293413 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34681.506849 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34681.506849 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34572.375127 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34572.375127 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -728,18 +771,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11181000 system.cpu.l2cache.overall_mshr_miss_latency::total 30840500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996420 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996951 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996951 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31304.936306 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31739.130435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31412.574850 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.191781 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.191781 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index 8b9b39b0d..b15f5671c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index b2566a0a7..30eeb514f 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:53 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 5325eaa70..73324a4d5 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000025 # Nu sim_ticks 25007500 # Number of ticks simulated final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55900 # Simulator instruction rate (inst/s) -host_op_rate 55897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92110077 # Simulator tick rate (ticks/s) -host_mem_usage 220976 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 72389 # Simulator instruction rate (inst/s) +host_op_rate 72383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119272701 # Simulator tick rate (ticks/s) +host_mem_usage 221376 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27904 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19072 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 436 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1115825252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 762651205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1115825252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 27904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 436 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 762651205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353174048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1115825252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 762651205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 762651205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 762651205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353174048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1115825252 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 50016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -123,11 +130,17 @@ system.cpu.icache.demand_accesses::total 2970 # nu system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123906 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123906 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123906 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54900.815217 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54900.815217 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54900.815217 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -155,11 +168,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 15872000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.101347 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.101347 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52730.897010 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 97.041769 # Cycle average of tags in use @@ -207,13 +226,21 @@ system.cpu.dcache.demand_accesses::total 3668 # nu system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026056 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.208044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097601 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097601 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56577.586207 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54656.666667 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54967.877095 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54967.877095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,13 +274,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7382000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7382000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7382000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53528.301887 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53470.588235 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 196.205624 # Cycle average of tags in use @@ -307,18 +342,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994350 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995444 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.625000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52264.705882 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52064.073227 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52064.073227 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,18 +394,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39910.511364 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40188.235294 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 64273b3fe..e306accf8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 076570d2f..f0f4b69ef 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:02 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 693d12ddb..a887522dd 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000020 # Nu sim_ticks 19744500 # Number of ticks simulated final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52427 # Simulator instruction rate (inst/s) -host_op_rate 52424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71633039 # Simulator tick rate (ticks/s) -host_mem_usage 221536 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 74885 # Simulator instruction rate (inst/s) +host_op_rate 74878 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 102311932 # Simulator tick rate (ticks/s) +host_mem_usage 222004 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated sim_ops 14449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30976 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 484 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory +system.physmem.bytes_read::total 30976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory +system.physmem.num_reads::total 484 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 39490 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -318,11 +325,17 @@ system.cpu.icache.demand_accesses::total 5506 # nu system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,11 +363,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 11937500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use @@ -402,13 +421,21 @@ system.cpu.dcache.demand_accesses::total 4603 # nu system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,13 +469,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5223000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use @@ -502,18 +537,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 146 system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,18 +589,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 63fce3718..9dd70f314 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index c5ff1dac8..0a6c1bd0d 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:04 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index b4eb79291..a62ce7951 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.000008 # Nu sim_ticks 7618500 # Number of ticks simulated final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147764 # Simulator instruction rate (inst/s) -host_op_rate 147721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74142280 # Simulator tick rate (ticks/s) -host_mem_usage 211580 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 949089 # Simulator instruction rate (inst/s) +host_op_rate 948034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 475431989 # Simulator tick rate (ticks/s) +host_mem_usage 212076 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 72223 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60880 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9042 # Number of bytes written to this memory -system.physmem.num_reads 17446 # Number of read requests responded to by this memory -system.physmem.num_writes 1442 # Number of write requests responded to by this memory -system.physmem.num_other 6 # Number of other requests responded to by this memory -system.physmem.bw_read 9479950121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7991074358 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1186847805 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10666797926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 60880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11343 # Number of bytes read from this memory +system.physmem.bytes_read::total 72223 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory +system.physmem.bytes_written::total 9042 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2226 # Number of read requests responded to by this memory +system.physmem.num_reads::total 17446 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory +system.physmem.num_other::total 6 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7991074358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1488875763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9479950121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7991074358 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7991074358 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186847805 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1186847805 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7991074358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2675723568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10666797926 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 15238 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index ad6d2cdd3..cfbf65944 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index 9346f2ccc..423d84a63 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:42:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:13 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index dfba79da8..f6532c6ee 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000042 # Nu sim_ticks 41800000 # Number of ticks simulated final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130693 # Simulator instruction rate (inst/s) -host_op_rate 130661 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 359830859 # Simulator tick rate (ticks/s) -host_mem_usage 220580 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 488993 # Simulator instruction rate (inst/s) +host_op_rate 488707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1345414902 # Simulator tick rate (ticks/s) +host_mem_usage 221064 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 416 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 26624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 416 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 425645933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 211291866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 636937799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 425645933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 425645933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 425645933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 211291866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 636937799 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 83600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 15221 # nu system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.018396 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.018396 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.018396 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 14756000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018396 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.018396 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.018396 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use @@ -155,13 +174,21 @@ system.cpu.dcache.demand_accesses::total 3668 # nu system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023810 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037623 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,13 +214,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7314000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use @@ -247,18 +282,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,18 +334,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 5684cea4e..08b3f6997 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1768,9 +1768,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -1791,9 +1790,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 9445b3529..51784eba5 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:42:58 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:14 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 243852286..1590e3eee 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,22 +4,59 @@ sim_seconds 0.000111 # Nu sim_ticks 111402500 # Number of ticks simulated final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79928 # Simulator instruction rate (inst/s) -host_op_rate 79928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8175729 # Simulator tick rate (ticks/s) -host_mem_usage 236248 # Number of bytes of host memory used -host_seconds 13.63 # Real time elapsed on the host +host_inst_rate 133234 # Simulator instruction rate (inst/s) +host_op_rate 133234 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13628365 # Simulator tick rate (ticks/s) +host_mem_usage 236536 # Number of bytes of host memory used +host_seconds 8.17 # Real time elapsed on the host sim_insts 1089093 # Number of instructions simulated sim_ops 1089093 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 43072 # Number of bytes read from this memory -system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 673 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 386634052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 263117973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 386634052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::total 43072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::total 673 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 208541101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97089383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 8042907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7468414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 45959471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11489868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 574493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7468414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 386634052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 208541101 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 8042907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 45959471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 574493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 263117973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 208541101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97089383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 8042907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7468414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 45959471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11489868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 574493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7468414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 386634052 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 222806 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -319,11 +356,17 @@ system.cpu0.icache.demand_accesses::total 6218 # n system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.122065 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.122065 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.122065 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38418.313570 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38418.313570 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38418.313570 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -351,11 +394,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 21891000 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.095529 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.095529 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.095529 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36853.535354 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 8 # number of replacements system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use @@ -407,15 +456,25 @@ system.cpu0.dcache.demand_accesses::total 164751 # n system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005927 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006722 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006319 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006319 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28234.343434 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44619.021978 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19025 # average SwapReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36828.036503 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36828.036503 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -455,15 +514,25 @@ system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002179 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002167 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002173 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002173 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27222.527473 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35511.363636 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16025 # average SwapReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 187393 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -765,11 +834,17 @@ system.cpu1.icache.demand_accesses::total 19809 # n system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.025493 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.025493 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.025493 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14852.475248 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14852.475248 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14852.475248 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -797,11 +872,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 5474500 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021960 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.021960 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.021960 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.057471 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use @@ -853,15 +934,25 @@ system.cpu1.dcache.demand_accesses::total 93422 # n system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009191 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003689 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006733 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006733 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20285.263158 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19269.480519 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 20770 # average SwapReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20036.565978 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20036.565978 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -901,15 +992,25 @@ system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003019 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002837 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002837 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13153.846154 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13977.064220 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17770 # average SwapReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 187102 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -1211,11 +1312,17 @@ system.cpu2.icache.demand_accesses::total 21870 # n system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.023411 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.023411 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.023411 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 21760.742188 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 21760.742188 # average overall miss latency system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 21760.742188 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1243,11 +1350,17 @@ system.cpu2.icache.demand_mshr_miss_latency::total 8467000 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020119 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.020119 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.020119 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19243.181818 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use @@ -1299,15 +1412,25 @@ system.cpu2.dcache.demand_accesses::total 81444 # n system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009490 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004137 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.815789 # miss rate for SwapReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007171 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007171 # miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 23413.242009 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20116.438356 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 19048.387097 # average SwapReq miss latency system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 22589.041096 # average overall miss latency system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 22589.041096 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1347,15 +1470,25 @@ system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003705 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002862 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.815789 # mshr miss rate for SwapReq accesses system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003340 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003340 # mshr miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14502.923977 # average ReadReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15014.851485 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 16048.387097 # average SwapReq mshr miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 186832 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -1657,11 +1790,17 @@ system.cpu3.icache.demand_accesses::total 24454 # n system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.020569 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.020569 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13604.373757 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13604.373757 # average overall miss latency system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13604.373757 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1689,11 +1828,17 @@ system.cpu3.icache.demand_mshr_miss_latency::total 4912000 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017666 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.017666 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.017666 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11370.370370 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use @@ -1745,15 +1890,25 @@ system.cpu3.dcache.demand_accesses::total 74691 # n system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009688 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004755 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007618 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007618 # miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 20514.285714 # average ReadReq miss latency system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20184.563758 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 21017.543860 # average SwapReq miss latency system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 20427.943761 # average overall miss latency system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 20427.943761 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1793,15 +1948,25 @@ system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003760 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003319 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003575 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003575 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13196.319018 # average ReadReq mshr miss latency system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15586.538462 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 18017.543860 # average SwapReq mshr miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 441.136869 # Cycle average of tags in use @@ -1979,14 +2144,17 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # mi system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.271379 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.963855 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses @@ -1995,6 +2163,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.193182 # mi system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.315692 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses @@ -2003,6 +2172,7 @@ system.l2c.overall_miss_rate::cpu2.inst 0.193182 # mi system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.315692 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency @@ -2011,13 +2181,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 51985.428051 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1968.750000 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52480.916031 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency @@ -2026,6 +2199,7 @@ system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52080.882353 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency @@ -2034,6 +2208,7 @@ system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52080.882353 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2136,14 +2311,17 @@ system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.267919 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.963855 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses @@ -2152,6 +2330,7 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.312442 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses @@ -2160,6 +2339,7 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.312442 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency @@ -2168,14 +2348,17 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39979.704797 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.893130 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency @@ -2184,6 +2367,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency @@ -2192,6 +2376,7 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index a47e5e15d..f048ede7e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -460,9 +460,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -483,9 +482,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index ab456df4c..7edc0f615 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:23 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index e871b4c6b..a670e1cab 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,22 +4,59 @@ sim_seconds 0.000088 # Nu sim_ticks 87713500 # Number of ticks simulated final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 523852 # Simulator instruction rate (inst/s) -host_op_rate 523839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67834135 # Simulator tick rate (ticks/s) -host_mem_usage 1149444 # Number of bytes of host memory used -host_seconds 1.29 # Real time elapsed on the host +host_inst_rate 1597903 # Simulator instruction rate (inst/s) +host_op_rate 1597833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206906108 # Simulator tick rate (ticks/s) +host_mem_usage 1149840 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host sim_insts 677340 # Number of instructions simulated sim_ops 677340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 35776 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 559 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 407873360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 253917584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 407873360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::total 35776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::total 559 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 205760801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 120391958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45238190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 14592965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1459296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 9485427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1459296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 9485427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 407873360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205760801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45238190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1459296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1459296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253917584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205760801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 120391958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45238190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 14592965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1459296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 9485427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1459296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 9485427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 407873360 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 175428 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -71,8 +108,11 @@ system.cpu0.icache.demand_accesses::total 175401 # n system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002662 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002662 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002662 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -122,10 +162,15 @@ system.cpu0.dcache.demand_accesses::total 82337 # n system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.002766 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,8 +232,11 @@ system.cpu1.icache.demand_accesses::total 167430 # n system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -238,10 +286,15 @@ system.cpu1.dcache.demand_accesses::total 53313 # n system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004330 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005290 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005290 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,8 +356,11 @@ system.cpu2.icache.demand_accesses::total 167366 # n system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,10 +410,15 @@ system.cpu2.dcache.demand_accesses::total 58461 # n system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003825 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004636 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004636 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,8 +480,11 @@ system.cpu3.icache.demand_accesses::total 167301 # n system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,10 +534,15 @@ system.cpu3.dcache.demand_accesses::total 55820 # n system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003835 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004676 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004676 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -625,14 +694,17 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # mi system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.256519 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.977528 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses @@ -641,6 +713,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.005587 # mi system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.313165 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses @@ -649,6 +722,7 @@ system.l2c.overall_miss_rate::cpu2.inst 0.005587 # mi system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.313165 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 7658e05d6..cf4b383de 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -444,9 +444,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -467,9 +466,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index bd4b2c9b4..3d54c9924 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:33 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 70ef2d753..36b8c656f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,22 +4,59 @@ sim_seconds 0.000262 # Nu sim_ticks 262298000 # Number of ticks simulated final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 323904 # Simulator instruction rate (inst/s) -host_op_rate 323899 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 128274037 # Simulator tick rate (ticks/s) -host_mem_usage 231956 # Number of bytes of host memory used -host_seconds 2.05 # Real time elapsed on the host +host_inst_rate 1070900 # Simulator instruction rate (inst/s) +host_op_rate 1070867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 424091073 # Simulator tick rate (ticks/s) +host_mem_usage 232420 # Number of bytes of host memory used +host_seconds 0.62 # Real time elapsed on the host sim_insts 662307 # Number of instructions simulated sim_ops 662307 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 36608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 572 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 139566447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 86375039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 139566447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 36608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 572 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 69539226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40259552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14395840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5367940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2195976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3903957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 243997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3659959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139566447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69539226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14395840 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2195976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 243997 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86375039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69539226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40259552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14395840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5367940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2195976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3903957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 243997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3659959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139566447 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 524596 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +114,17 @@ system.cpu0.icache.demand_accesses::total 158416 # n system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002948 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002948 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002948 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 39665.952891 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 39665.952891 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 39665.952891 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +146,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 17123000 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002948 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002948 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002948 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36665.952891 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use @@ -159,15 +208,25 @@ system.cpu0.dcache.demand_accesses::total 73844 # n system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003312 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007342 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29314.814815 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39207.650273 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 14884.615385 # average SwapReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34562.318841 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34562.318841 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,15 +258,25 @@ system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007342 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26314.814815 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36207.650273 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11884.615385 # average SwapReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 524596 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -265,11 +334,17 @@ system.cpu1.icache.demand_accesses::total 172358 # n system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21640.710383 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21640.710383 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21640.710383 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,11 +366,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 6822000 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18639.344262 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use @@ -347,15 +428,25 @@ system.cpu1.dcache.demand_accesses::total 47806 # n system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004570 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005836 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005836 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20513.812155 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19275.510204 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20078.853047 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20078.853047 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,15 +478,25 @@ system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004570 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005836 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005836 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17513.812155 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16275.510204 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 524596 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -453,11 +554,17 @@ system.cpu2.icache.demand_accesses::total 165532 # n system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002211 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002211 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002211 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15433.060109 # average overall miss latency system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15433.060109 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,11 +586,17 @@ system.cpu2.icache.demand_mshr_miss_latency::total 4550500 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002211 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002211 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002211 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use @@ -535,15 +648,25 @@ system.cpu2.dcache.demand_accesses::total 57869 # n system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003728 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004579 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004579 # miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16198.717949 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 19119.266055 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17400 # average overall miss latency system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17400 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,15 +698,25 @@ system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003728 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004579 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004579 # mshr miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13198.717949 # average ReadReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16119.266055 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 524596 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -641,11 +774,17 @@ system.cpu3.icache.demand_accesses::total 166163 # n system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15072.207084 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15072.207084 # average overall miss latency system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15072.207084 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -667,11 +806,17 @@ system.cpu3.icache.demand_mshr_miss_latency::total 4430500 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12072.207084 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use @@ -723,15 +868,25 @@ system.cpu3.dcache.demand_accesses::total 57168 # n system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004635 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004635 # miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16363.057325 # average ReadReq miss latency system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19259.259259 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17543.396226 # average overall miss latency system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17543.396226 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -763,15 +918,25 @@ system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006988 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004635 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004635 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13363.057325 # average ReadReq mshr miss latency system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16259.259259 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3037.037037 # average SwapReq mshr miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 353.886259 # Cycle average of tags in use @@ -949,14 +1114,17 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # mi system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.268496 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.972973 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses @@ -965,6 +1133,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.032787 # mi system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.325633 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses @@ -973,6 +1142,7 @@ system.l2c.overall_miss_rate::cpu2.inst 0.032787 # mi system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.325633 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency @@ -981,13 +1151,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 51844.444444 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2166.666667 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52007.042254 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency @@ -996,6 +1169,7 @@ system.l2c.demand_avg_miss_latency::cpu2.inst 51250 system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51883.445946 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency @@ -1004,6 +1178,7 @@ system.l2c.overall_avg_miss_latency::cpu2.inst 51250 system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51883.445946 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1112,14 +1287,17 @@ system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.256563 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.972973 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses @@ -1128,6 +1306,7 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.314631 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses @@ -1136,6 +1315,7 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.314631 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency @@ -1144,14 +1324,17 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.976744 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.042254 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency @@ -1160,6 +1343,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency @@ -1168,6 +1352,7 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index b44d5a4c2..1cbda9483 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:38:27 +Real time: Jun/04/2012 14:41:50 Profiler Stats -------------- -Elapsed_time_in_seconds: 113 -Elapsed_time_in_minutes: 1.88333 -Elapsed_time_in_hours: 0.0313889 -Elapsed_time_in_days: 0.00130787 +Elapsed_time_in_seconds: 88 +Elapsed_time_in_minutes: 1.46667 +Elapsed_time_in_hours: 0.0244444 +Elapsed_time_in_days: 0.00101852 -Virtual_time_in_seconds: 112.14 -Virtual_time_in_minutes: 1.869 -Virtual_time_in_hours: 0.03115 -Virtual_time_in_days: 0.00129792 +Virtual_time_in_seconds: 87.84 +Virtual_time_in_minutes: 1.464 +Virtual_time_in_hours: 0.0244 +Virtual_time_in_days: 0.00101667 Ruby_current_time: 22495354 Ruby_start_time: 0 Ruby_cycles: 22495354 -mbytes_resident: 60.2695 -mbytes_total: 361.398 -resident_ratio: 0.166768 +mbytes_resident: 61.2852 +mbytes_total: 361.766 +resident_ratio: 0.169406 ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ] @@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 3280807 average: 0.508064 | Resource Usage -------------- page_size: 4096 -user_time: 112 +user_time: 87 system_time: 0 -page_reclaims: 15932 +page_reclaims: 16135 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 232 +block_outputs: 216 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index 26548e28d..4c179bc95 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 14:40:22 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index 1ae2ff15c..c7afc7b3a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.022495 # Nu sim_ticks 22495354 # Number of ticks simulated final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 200233 # Simulator tick rate (ticks/s) -host_mem_usage 370076 # Number of bytes of host memory used -host_seconds 112.35 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 256726 # Simulator tick rate (ticks/s) +host_mem_usage 370452 # Number of bytes of host memory used +host_seconds 87.62 # Real time elapsed on the host system.cpu0.num_reads 99326 # number of read accesses completed system.cpu0.num_writes 53132 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index af42ad0ff..e3b9d4def 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -14,7 +14,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index cb3fdaf16..c5ae1c27c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:42:43 +Real time: Jun/04/2012 14:45:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 365 -Elapsed_time_in_minutes: 6.08333 -Elapsed_time_in_hours: 0.101389 -Elapsed_time_in_days: 0.00422454 +Elapsed_time_in_seconds: 244 +Elapsed_time_in_minutes: 4.06667 +Elapsed_time_in_hours: 0.0677778 +Elapsed_time_in_days: 0.00282407 -Virtual_time_in_seconds: 361.58 -Virtual_time_in_minutes: 6.02633 -Virtual_time_in_hours: 0.100439 -Virtual_time_in_days: 0.00418495 +Virtual_time_in_seconds: 244.12 +Virtual_time_in_minutes: 4.06867 +Virtual_time_in_hours: 0.0678111 +Virtual_time_in_days: 0.00282546 Ruby_current_time: 19400856 Ruby_start_time: 0 Ruby_cycles: 19400856 -mbytes_resident: 60.2344 -mbytes_total: 361.566 -resident_ratio: 0.166593 +mbytes_resident: 61.3008 +mbytes_total: 361.941 +resident_ratio: 0.169367 ruby_cycles_executed: [ 19400857 19400857 19400857 19400857 19400857 19400857 19400857 19400857 ] @@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 361 +user_time: 244 system_time: 0 -page_reclaims: 15956 +page_reclaims: 16161 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 448 +block_outputs: 216 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 403e6654c..ca77e3fc7 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:26 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 9aec04ac2..fcc191198 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019401 # Nu sim_ticks 19400856 # Number of ticks simulated final_tick 19400856 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 53186 # Simulator tick rate (ticks/s) -host_mem_usage 370248 # Number of bytes of host memory used -host_seconds 364.77 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 79524 # Simulator tick rate (ticks/s) +host_mem_usage 370632 # Number of bytes of host memory used +host_seconds 243.96 # Real time elapsed on the host system.cpu0.num_reads 98844 # number of read accesses completed system.cpu0.num_writes 53478 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index ab5cb8e9e..fe9a9f183 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:39:26 +Real time: Jun/04/2012 14:44:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 164 -Elapsed_time_in_minutes: 2.73333 -Elapsed_time_in_hours: 0.0455556 -Elapsed_time_in_days: 0.00189815 +Elapsed_time_in_seconds: 117 +Elapsed_time_in_minutes: 1.95 +Elapsed_time_in_hours: 0.0325 +Elapsed_time_in_days: 0.00135417 -Virtual_time_in_seconds: 163.7 -Virtual_time_in_minutes: 2.72833 -Virtual_time_in_hours: 0.0454722 -Virtual_time_in_days: 0.00189468 +Virtual_time_in_seconds: 117.17 +Virtual_time_in_minutes: 1.95283 +Virtual_time_in_hours: 0.0325472 +Virtual_time_in_days: 0.00135613 Ruby_current_time: 19665440 Ruby_start_time: 0 Ruby_cycles: 19665440 -mbytes_resident: 60.0117 -mbytes_total: 361.082 -resident_ratio: 0.1662 +mbytes_resident: 61.0625 +mbytes_total: 361.484 +resident_ratio: 0.168922 ruby_cycles_executed: [ 19665441 19665441 19665441 19665441 19665441 19665441 19665441 19665441 ] @@ -125,13 +125,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 163 +user_time: 117 system_time: 0 -page_reclaims: 15846 +page_reclaims: 16038 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 288 +block_outputs: 232 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index 7601ab137..4dc86aa94 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:42 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:33 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index d352be3a5..284e6ab5c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019665 # Nu sim_ticks 19665440 # Number of ticks simulated final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 119847 # Simulator tick rate (ticks/s) -host_mem_usage 369752 # Number of bytes of host memory used -host_seconds 164.09 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 168119 # Simulator tick rate (ticks/s) +host_mem_usage 370164 # Number of bytes of host memory used +host_seconds 116.97 # Real time elapsed on the host system.cpu0.num_reads 99534 # number of read accesses completed system.cpu0.num_writes 53920 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 08a16b146..f9a059734 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:38:42 +Real time: Jun/04/2012 13:44:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 131 -Elapsed_time_in_minutes: 2.18333 -Elapsed_time_in_hours: 0.0363889 -Elapsed_time_in_days: 0.0015162 +Elapsed_time_in_seconds: 111 +Elapsed_time_in_minutes: 1.85 +Elapsed_time_in_hours: 0.0308333 +Elapsed_time_in_days: 0.00128472 -Virtual_time_in_seconds: 129.82 -Virtual_time_in_minutes: 2.16367 -Virtual_time_in_hours: 0.0360611 -Virtual_time_in_days: 0.00150255 +Virtual_time_in_seconds: 111.55 +Virtual_time_in_minutes: 1.85917 +Virtual_time_in_hours: 0.0309861 +Virtual_time_in_days: 0.00129109 Ruby_current_time: 19129199 Ruby_start_time: 0 Ruby_cycles: 19129199 -mbytes_resident: 59.6641 -mbytes_total: 360.938 -resident_ratio: 0.165303 +mbytes_resident: 60.7188 +mbytes_total: 361.293 +resident_ratio: 0.16806 ruby_cycles_executed: [ 19129200 19129200 19129200 19129200 19129200 19129200 19129200 19129200 ] @@ -124,13 +124,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 129 +user_time: 111 system_time: 0 -page_reclaims: 15794 +page_reclaims: 15994 page_faults: 0 swaps: 0 -block_inputs: 16 -block_outputs: 256 +block_inputs: 0 +block_outputs: 224 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 9fc5d7446..bc60d72d3 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index cad2377ee..7c588684e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019129 # Nu sim_ticks 19129199 # Number of ticks simulated final_tick 19129199 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 146249 # Simulator tick rate (ticks/s) -host_mem_usage 369604 # Number of bytes of host memory used -host_seconds 130.80 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 171697 # Simulator tick rate (ticks/s) +host_mem_usage 369968 # Number of bytes of host memory used +host_seconds 111.41 # Real time elapsed on the host system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 53893 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index 379029232..ceb7b2a64 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:42:37 +Real time: Jun/04/2012 14:22:53 Profiler Stats -------------- -Elapsed_time_in_seconds: 69 -Elapsed_time_in_minutes: 1.15 -Elapsed_time_in_hours: 0.0191667 -Elapsed_time_in_days: 0.000798611 +Elapsed_time_in_seconds: 41 +Elapsed_time_in_minutes: 0.683333 +Elapsed_time_in_hours: 0.0113889 +Elapsed_time_in_days: 0.000474537 -Virtual_time_in_seconds: 68.73 -Virtual_time_in_minutes: 1.1455 -Virtual_time_in_hours: 0.0190917 -Virtual_time_in_days: 0.000795486 +Virtual_time_in_seconds: 41.24 +Virtual_time_in_minutes: 0.687333 +Virtual_time_in_hours: 0.0114556 +Virtual_time_in_days: 0.000477315 Ruby_current_time: 28725020 Ruby_start_time: 0 Ruby_cycles: 28725020 -mbytes_resident: 59.4102 -mbytes_total: 360.535 -resident_ratio: 0.164783 +mbytes_resident: 60.7461 +mbytes_total: 361.262 +resident_ratio: 0.16815 ruby_cycles_executed: [ 28725021 28725021 28725021 28725021 28725021 28725021 28725021 28725021 ] @@ -118,13 +118,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 Resource Usage -------------- page_size: 4096 -user_time: 68 +user_time: 41 system_time: 0 -page_reclaims: 15745 -page_faults: 0 +page_reclaims: 15955 +page_faults: 2 swaps: 0 -block_inputs: 0 -block_outputs: 256 +block_inputs: 128 +block_outputs: 184 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout index 4cb3155a6..19534930d 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:28 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:22:12 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 12fdf4aa3..fbf03980e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.028725 # Nu sim_ticks 28725020 # Number of ticks simulated final_tick 28725020 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 417169 # Simulator tick rate (ticks/s) -host_mem_usage 369192 # Number of bytes of host memory used -host_seconds 68.86 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 699351 # Simulator tick rate (ticks/s) +host_mem_usage 369936 # Number of bytes of host memory used +host_seconds 41.07 # Real time elapsed on the host system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 53147 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini index dfa7c1d18..db9f08590 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini @@ -417,9 +417,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=2 header_cycles=1 use_default_range=false @@ -440,9 +439,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=2 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index cd078a3a4..4cc5a9b4f 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:08 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:15:53 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 58bdafd11..9aa493322 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -4,24 +4,76 @@ sim_seconds 0.000263 # Nu sim_ticks 263488655 # Number of ticks simulated final_tick 263488655 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1217695 # Simulator tick rate (ticks/s) -host_mem_usage 343548 # Number of bytes of host memory used -host_seconds 216.38 # Real time elapsed on the host -system.physmem.bytes_read 4057580 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2644316 # Number of bytes written to this memory -system.physmem.num_reads 141878 # Number of read requests responded to by this memory -system.physmem.num_writes 83744 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15399448602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write 10035786930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 25435235532 # Total bandwidth to/from this memory (bytes/s) -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 1558675 # Simulator tick rate (ticks/s) +host_mem_usage 343952 # Number of bytes of host memory used +host_seconds 169.05 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 504730 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 513456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 503221 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 509883 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 511138 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 501110 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 514161 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 499881 # Number of bytes read from this memory +system.physmem.bytes_read::total 4057580 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 2601216 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5426 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5325 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5406 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5419 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5298 # Number of bytes written to this memory +system.physmem.bytes_written::total 2644316 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 17740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 17646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 17743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 17727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 17848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 17774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 17658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 17742 # Number of read requests responded to by this memory +system.physmem.num_reads::total 141878 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 40644 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5325 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5406 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5472 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5419 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5298 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 1915566346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 1948683521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 1909839344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 1935123165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 1939886178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 1901827614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 1951359158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 1897163276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15399448602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9872212525 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 20463879 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 20592917 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 20209599 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 20517012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 20767498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 20350022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 20566350 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 20107128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10035786930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9872212525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 1936030225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 1969276438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 1930048943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 1955640177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 1960653676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 1922177636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 1971925509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 1917270404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 25435235532 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 76856 # number of replacements system.l2c.tagsinuse 657.714518 # Cycle average of tags in use system.l2c.total_refs 139150 # Total number of references to valid blocks. @@ -239,6 +291,7 @@ system.l2c.ReadReq_miss_rate::cpu4 0.333248 # mi system.l2c.ReadReq_miss_rate::cpu5 0.329978 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu6 0.326978 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu7 0.323177 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.329797 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0 0.782485 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1 0.792266 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2 0.783810 # miss rate for UpgradeReq accesses @@ -247,6 +300,7 @@ system.l2c.UpgradeReq_miss_rate::cpu4 0.786706 # mi system.l2c.UpgradeReq_miss_rate::cpu5 0.778363 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu6 0.796469 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu7 0.793778 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.786224 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0 0.661926 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1 0.673235 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2 0.653281 # miss rate for ReadExReq accesses @@ -255,6 +309,7 @@ system.l2c.ReadExReq_miss_rate::cpu4 0.664491 # mi system.l2c.ReadExReq_miss_rate::cpu5 0.652798 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu6 0.668049 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu7 0.659537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.662584 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0 0.445972 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1 0.454617 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2 0.441105 # miss rate for demand accesses @@ -263,6 +318,7 @@ system.l2c.demand_miss_rate::cpu4 0.449498 # mi system.l2c.demand_miss_rate::cpu5 0.443762 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu6 0.448253 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu7 0.443015 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.446844 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0 0.445972 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1 0.454617 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2 0.441105 # miss rate for overall accesses @@ -271,6 +327,7 @@ system.l2c.overall_miss_rate::cpu4 0.449498 # mi system.l2c.overall_miss_rate::cpu5 0.443762 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu6 0.448253 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu7 0.443015 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.446844 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1 49611.864250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2 49597.501643 # average ReadReq miss latency @@ -279,6 +336,7 @@ system.l2c.ReadReq_avg_miss_latency::cpu4 49599.928365 # a system.l2c.ReadReq_avg_miss_latency::cpu5 49643.596206 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu6 49631.254810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu7 49598.091273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49615.022334 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2 20319.092146 # average UpgradeReq miss latency @@ -287,6 +345,7 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu4 19801.786885 system.l2c.UpgradeReq_avg_miss_latency::cpu5 20703.490160 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu6 19895.977833 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu7 20570.862832 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 20284.674323 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0 49777.383282 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1 49793.150482 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2 49738.978778 # average ReadExReq miss latency @@ -295,6 +354,7 @@ system.l2c.ReadExReq_avg_miss_latency::cpu4 49860.337739 # system.l2c.ReadExReq_avg_miss_latency::cpu5 49799.127293 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu6 49869.189138 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu7 49835.864788 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 49817.112873 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0 49702.290320 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1 49707.635619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2 49670.188364 # average overall miss latency @@ -303,6 +363,7 @@ system.l2c.demand_avg_miss_latency::cpu4 49735.031412 # av system.l2c.demand_avg_miss_latency::cpu5 49724.239243 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu6 49757.341526 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu7 49724.208008 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 49720.418420 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0 49702.290320 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1 49707.635619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2 49670.188364 # average overall miss latency @@ -311,6 +372,7 @@ system.l2c.overall_avg_miss_latency::cpu4 49735.031412 # a system.l2c.overall_avg_miss_latency::cpu5 49724.239243 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu6 49757.341526 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu7 49724.208008 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 49720.418420 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked @@ -491,6 +553,7 @@ system.l2c.ReadReq_mshr_miss_rate::cpu4 0.325355 # ms system.l2c.ReadReq_mshr_miss_rate::cpu5 0.322622 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu6 0.319987 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu7 0.315803 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.322103 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.779153 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.788299 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.781386 # mshr miss rate for UpgradeReq accesses @@ -499,6 +562,7 @@ system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.783730 # system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.775969 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.794017 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.790768 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.783235 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.653800 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.664889 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.644556 # mshr miss rate for ReadExReq accesses @@ -507,6 +571,7 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.657963 # m system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.644263 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.661368 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.652291 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.655102 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for demand accesses @@ -515,6 +580,7 @@ system.l2c.demand_mshr_miss_rate::cpu4 0.442084 # ms system.l2c.demand_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.439225 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for overall accesses @@ -523,6 +589,7 @@ system.l2c.overall_mshr_miss_rate::cpu4 0.442084 # ms system.l2c.overall_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.439225 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40002.870565 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40002.812241 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40002.878951 # average ReadReq mshr miss latency @@ -531,6 +598,7 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 39994.796252 system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.304600 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 39986.772989 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39994.349857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39998.692981 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40002.238852 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39976.872327 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40002.032258 # average UpgradeReq mshr miss latency @@ -539,6 +607,7 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40002.012025 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40002.360888 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40002.153799 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40002.212563 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39998.991821 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40002.446171 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39995.372559 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39994.920452 # average ReadExReq mshr miss latency @@ -547,6 +616,7 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40002.443543 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40002.523827 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40002.451411 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 40002.352804 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000.638344 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency @@ -555,6 +625,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu4 39998.790654 system.l2c.demand_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency @@ -563,6 +634,7 @@ system.l2c.overall_avg_mshr_miss_latency::cpu4 39998.790654 system.l2c.overall_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -571,6 +643,7 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -579,6 +652,7 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency @@ -587,6 +661,7 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.num_reads 99815 # number of read accesses completed system.cpu0.num_writes 53929 # number of write accesses completed @@ -633,13 +708,21 @@ system.cpu0.l1c.demand_accesses::total 69070 # nu system.cpu0.l1c.overall_accesses::cpu0 69070 # number of overall (read+write) accesses system.cpu0.l1c.overall_accesses::total 69070 # number of overall (read+write) accesses system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.831953 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.831953 # miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956350 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956350 # miss rate for WriteReq accesses system.cpu0.l1c.demand_miss_rate::cpu0 0.875648 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.875648 # miss rate for demand accesses system.cpu0.l1c.overall_miss_rate::cpu0 0.875648 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.875648 # miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 34863.258698 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 34863.258698 # average ReadReq miss latency system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 43164.731144 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 43164.731144 # average WriteReq miss latency system.cpu0.l1c.demand_avg_miss_latency::cpu0 38047.907822 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 38047.907822 # average overall miss latency system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 38047.907822 # average overall miss latency system.cpu0.l1c.blocked_cycles::no_mshrs 253845135 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.blocked::no_mshrs 69110 # number of cycles access was blocked @@ -673,16 +756,27 @@ system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 569723237 system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1464301869 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1464301869 # number of overall MSHR uncacheable cycles system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.831953 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.831953 # mshr miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956350 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956350 # mshr miss rate for WriteReq accesses system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.875648 # mshr miss rate for demand accesses system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.875648 # mshr miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 33859.391373 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 33859.391373 # average ReadReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 42160.816007 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 42160.816007 # average WriteReq mshr miss latency system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.num_reads 98493 # number of read accesses completed system.cpu1.num_writes 53671 # number of write accesses completed @@ -729,13 +823,21 @@ system.cpu1.l1c.demand_accesses::total 68880 # nu system.cpu1.l1c.overall_accesses::cpu1 68880 # number of overall (read+write) accesses system.cpu1.l1c.overall_accesses::total 68880 # number of overall (read+write) accesses system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.833202 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.833202 # miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956206 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.956206 # miss rate for WriteReq accesses system.cpu1.l1c.demand_miss_rate::cpu1 0.876670 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.876670 # miss rate for demand accesses system.cpu1.l1c.overall_miss_rate::cpu1 0.876670 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.876670 # miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 35078.437375 # average ReadReq miss latency system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 43578.818690 # average WriteReq miss latency system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 38354.853291 # average overall miss latency system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 38354.853291 # average overall miss latency system.cpu1.l1c.blocked_cycles::no_mshrs 253325402 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.blocked::no_mshrs 68822 # number of cycles access was blocked @@ -769,16 +871,27 @@ system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 578327433 system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1455446592 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1455446592 # number of overall MSHR uncacheable cycles system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.833202 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.833202 # mshr miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956206 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956206 # mshr miss rate for WriteReq accesses system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.876670 # mshr miss rate for demand accesses system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.876670 # mshr miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 34074.598410 # average ReadReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 42575.032825 # average WriteReq mshr miss latency system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.num_reads 99149 # number of read accesses completed system.cpu2.num_writes 53185 # number of write accesses completed @@ -825,13 +938,21 @@ system.cpu2.l1c.demand_accesses::total 68674 # nu system.cpu2.l1c.overall_accesses::cpu2 68674 # number of overall (read+write) accesses system.cpu2.l1c.overall_accesses::total 68674 # number of overall (read+write) accesses system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.830590 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.830590 # miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955373 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955373 # miss rate for WriteReq accesses system.cpu2.l1c.demand_miss_rate::cpu2 0.874115 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.874115 # miss rate for demand accesses system.cpu2.l1c.overall_miss_rate::cpu2 0.874115 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.874115 # miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 35074.051314 # average ReadReq miss latency system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 43332.089535 # average WriteReq miss latency system.cpu2.l1c.demand_avg_miss_latency::cpu2 38222.283080 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 38222.283080 # average overall miss latency system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 38222.283080 # average overall miss latency system.cpu2.l1c.blocked_cycles::no_mshrs 254303447 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.blocked::no_mshrs 68698 # number of cycles access was blocked @@ -865,16 +986,27 @@ system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 566349170 system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1466862226 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1466862226 # number of overall MSHR uncacheable cycles system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.830590 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.830590 # mshr miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955373 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955373 # mshr miss rate for WriteReq accesses system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.874115 # mshr miss rate for demand accesses system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.874115 # mshr miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 34070.157684 # average ReadReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 42328.351409 # average WriteReq mshr miss latency system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.num_reads 99588 # number of read accesses completed system.cpu3.num_writes 53645 # number of write accesses completed @@ -921,13 +1053,21 @@ system.cpu3.l1c.demand_accesses::total 69040 # nu system.cpu3.l1c.overall_accesses::cpu3 69040 # number of overall (read+write) accesses system.cpu3.l1c.overall_accesses::total 69040 # number of overall (read+write) accesses system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.831214 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.831214 # miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955632 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955632 # miss rate for WriteReq accesses system.cpu3.l1c.demand_miss_rate::cpu3 0.875000 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.875000 # miss rate for demand accesses system.cpu3.l1c.overall_miss_rate::cpu3 0.875000 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.875000 # miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 35278.022452 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 35278.022452 # average ReadReq miss latency system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 42875.562470 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 42875.562470 # average WriteReq miss latency system.cpu3.l1c.demand_avg_miss_latency::cpu3 38198.189340 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 38198.189340 # average overall miss latency system.cpu3.l1c.overall_avg_miss_latency::cpu3 38198.189340 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 38198.189340 # average overall miss latency system.cpu3.l1c.blocked_cycles::no_mshrs 254462667 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.blocked::no_mshrs 68939 # number of cycles access was blocked @@ -961,16 +1101,27 @@ system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 569772276 system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1459204213 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1459204213 # number of overall MSHR uncacheable cycles system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.831214 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.831214 # mshr miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955632 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955632 # mshr miss rate for WriteReq accesses system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.875000 # mshr miss rate for demand accesses system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.875000 # mshr miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34274.209970 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34274.209970 # average ReadReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 41871.690641 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 41871.690641 # average WriteReq mshr miss latency system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu4.num_reads 99725 # number of read accesses completed system.cpu4.num_writes 53533 # number of write accesses completed @@ -1017,13 +1168,21 @@ system.cpu4.l1c.demand_accesses::total 68997 # nu system.cpu4.l1c.overall_accesses::cpu4 68997 # number of overall (read+write) accesses system.cpu4.l1c.overall_accesses::total 68997 # number of overall (read+write) accesses system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.828961 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.828961 # miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953325 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953325 # miss rate for WriteReq accesses system.cpu4.l1c.demand_miss_rate::cpu4 0.872328 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.872328 # miss rate for demand accesses system.cpu4.l1c.overall_miss_rate::cpu4 0.872328 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.872328 # miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 34981.938149 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 34981.938149 # average ReadReq miss latency system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 43355.729302 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 43355.729302 # average WriteReq miss latency system.cpu4.l1c.demand_avg_miss_latency::cpu4 38173.099970 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 38173.099970 # average overall miss latency system.cpu4.l1c.overall_avg_miss_latency::cpu4 38173.099970 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 38173.099970 # average overall miss latency system.cpu4.l1c.blocked_cycles::no_mshrs 254136532 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.blocked::no_mshrs 68868 # number of cycles access was blocked @@ -1057,16 +1216,27 @@ system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 576408625 system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1474870536 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1474870536 # number of overall MSHR uncacheable cycles system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.828961 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.828961 # mshr miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953325 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953325 # mshr miss rate for WriteReq accesses system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.872328 # mshr miss rate for demand accesses system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.872328 # mshr miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 33978.070817 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 33978.070817 # average ReadReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 42351.902864 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 42351.902864 # average WriteReq mshr miss latency system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu5.num_reads 100000 # number of read accesses completed system.cpu5.num_writes 53710 # number of write accesses completed @@ -1113,13 +1283,21 @@ system.cpu5.l1c.demand_accesses::total 69080 # nu system.cpu5.l1c.overall_accesses::cpu5 69080 # number of overall (read+write) accesses system.cpu5.l1c.overall_accesses::total 69080 # number of overall (read+write) accesses system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.831067 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.831067 # miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953353 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953353 # miss rate for WriteReq accesses system.cpu5.l1c.demand_miss_rate::cpu5 0.873798 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.873798 # miss rate for demand accesses system.cpu5.l1c.overall_miss_rate::cpu5 0.873798 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.873798 # miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 34590.842352 # average ReadReq miss latency system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 43380.004563 # average WriteReq miss latency system.cpu5.l1c.demand_avg_miss_latency::cpu5 37941.708625 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 37941.708625 # average overall miss latency system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 37941.708625 # average overall miss latency system.cpu5.l1c.blocked_cycles::no_mshrs 253381114 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.blocked::no_mshrs 68969 # number of cycles access was blocked @@ -1153,16 +1331,27 @@ system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567587171 system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1470443205 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1470443205 # number of overall MSHR uncacheable cycles system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.831067 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.831067 # mshr miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953353 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953353 # mshr miss rate for WriteReq accesses system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.873798 # mshr miss rate for demand accesses system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.873798 # mshr miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 33586.894160 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 33586.894160 # average ReadReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 42376.221397 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 42376.221397 # average WriteReq mshr miss latency system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu6.num_reads 99389 # number of read accesses completed system.cpu6.num_writes 53686 # number of write accesses completed @@ -1209,13 +1398,21 @@ system.cpu6.l1c.demand_accesses::total 68913 # nu system.cpu6.l1c.overall_accesses::cpu6 68913 # number of overall (read+write) accesses system.cpu6.l1c.overall_accesses::total 68913 # number of overall (read+write) accesses system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.831071 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.831071 # miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953877 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953877 # miss rate for WriteReq accesses system.cpu6.l1c.demand_miss_rate::cpu6 0.874305 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.874305 # miss rate for demand accesses system.cpu6.l1c.overall_miss_rate::cpu6 0.874305 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.874305 # miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 35026.520844 # average ReadReq miss latency system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 43893.173019 # average WriteReq miss latency system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 38432.141740 # average overall miss latency system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 38432.141740 # average overall miss latency system.cpu6.l1c.blocked_cycles::no_mshrs 253794713 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.blocked::no_mshrs 68612 # number of cycles access was blocked @@ -1249,16 +1446,27 @@ system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 574689009 system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1452670464 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1452670464 # number of overall MSHR uncacheable cycles system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.831071 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.831071 # mshr miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953877 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953877 # mshr miss rate for WriteReq accesses system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.874305 # mshr miss rate for demand accesses system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.874305 # mshr miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 34022.708723 # average ReadReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 42889.171809 # average WriteReq mshr miss latency system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu7.num_reads 99694 # number of read accesses completed system.cpu7.num_writes 53501 # number of write accesses completed @@ -1305,13 +1513,21 @@ system.cpu7.l1c.demand_accesses::total 68980 # nu system.cpu7.l1c.overall_accesses::cpu7 68980 # number of overall (read+write) accesses system.cpu7.l1c.overall_accesses::total 68980 # number of overall (read+write) accesses system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.830316 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.830316 # miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954152 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954152 # miss rate for WriteReq accesses system.cpu7.l1c.demand_miss_rate::cpu7 0.873818 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.873818 # miss rate for demand accesses system.cpu7.l1c.overall_miss_rate::cpu7 0.873818 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.873818 # miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 34642.102409 # average ReadReq miss latency system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 43516.263916 # average WriteReq miss latency system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 38046.102147 # average overall miss latency system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 38046.102147 # average overall miss latency system.cpu7.l1c.blocked_cycles::no_mshrs 254008986 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.blocked::no_mshrs 69036 # number of cycles access was blocked @@ -1345,16 +1561,27 @@ system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 558194703 system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1460156339 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1460156339 # number of overall MSHR uncacheable cycles system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.830316 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.830316 # mshr miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954152 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954152 # mshr miss rate for WriteReq accesses system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.873818 # mshr miss rate for demand accesses system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.873818 # mshr miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 33638.262764 # average ReadReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 42512.349466 # average WriteReq mshr miss latency system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats index f9dd021f3..7b092c66b 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:35 +Real time: Jun/04/2012 14:40:53 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.3 -Virtual_time_in_minutes: 0.005 -Virtual_time_in_hours: 8.33333e-05 -Virtual_time_in_days: 3.47222e-06 +Virtual_time_in_seconds: 0.36 +Virtual_time_in_minutes: 0.006 +Virtual_time_in_hours: 0.0001 +Virtual_time_in_days: 4.16667e-06 Ruby_current_time: 349711 Ruby_start_time: 0 Ruby_cycles: 349711 -mbytes_resident: 42.2773 -mbytes_total: 215.703 -resident_ratio: 0.195998 +mbytes_resident: 43.2695 +mbytes_total: 216.074 +resident_ratio: 0.200253 ruby_cycles_executed: [ 349712 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11317 +page_reclaims: 11518 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 80 +block_outputs: 88 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout index 56e348b35..bfa4f7e73 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 14:40:53 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index 715dd6b55..f6f4e6847 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000350 # Nu sim_ticks 349711 # Number of ticks simulated final_tick 349711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2733901 # Simulator tick rate (ticks/s) -host_mem_usage 220884 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 2288501 # Simulator tick rate (ticks/s) +host_mem_usage 221264 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats index 706512ef6..ebeb573bc 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:38 +Real time: Jun/04/2012 14:42:01 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.56 -Virtual_time_in_minutes: 0.00933333 -Virtual_time_in_hours: 0.000155556 -Virtual_time_in_days: 6.48148e-06 +Virtual_time_in_seconds: 0.66 +Virtual_time_in_minutes: 0.011 +Virtual_time_in_hours: 0.000183333 +Virtual_time_in_days: 7.63889e-06 Ruby_current_time: 357561 Ruby_start_time: 0 Ruby_cycles: 357561 -mbytes_resident: 42.2305 -mbytes_total: 215.871 -resident_ratio: 0.195628 +mbytes_resident: 43.5312 +mbytes_total: 216.246 +resident_ratio: 0.201304 ruby_cycles_executed: [ 357562 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11327 +page_reclaims: 11528 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 72 +block_outputs: 80 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index 45991493b..473ebc3b9 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:42:00 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index a0c426ba8..22e36183d 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000358 # Nu sim_ticks 357561 # Number of ticks simulated final_tick 357561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 908445 # Simulator tick rate (ticks/s) -host_mem_usage 221056 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 776030 # Simulator tick rate (ticks/s) +host_mem_usage 221440 # Number of bytes of host memory used +host_seconds 0.46 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats index 3806bbb4c..c55e7feb6 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:42 +Real time: Jun/04/2012 14:43:05 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.28 -Virtual_time_in_minutes: 0.00466667 -Virtual_time_in_hours: 7.77778e-05 -Virtual_time_in_days: 3.24074e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 259241 Ruby_start_time: 0 Ruby_cycles: 259241 -mbytes_resident: 42.25 -mbytes_total: 215.77 -resident_ratio: 0.195811 +mbytes_resident: 43.2578 +mbytes_total: 216.168 +resident_ratio: 0.200112 ruby_cycles_executed: [ 259242 ] @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11326 +page_reclaims: 11509 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 80 +block_outputs: 88 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index 2d7dcae80..a79f03bf6 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:42 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:43:05 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 29c84ee49..b667f4459 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000259 # Nu sim_ticks 259241 # Number of ticks simulated final_tick 259241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2436767 # Simulator tick rate (ticks/s) -host_mem_usage 220952 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 2053459 # Simulator tick rate (ticks/s) +host_mem_usage 221360 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats index 5a24f618a..8e58b5f4d 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:31 +Real time: Jun/04/2012 13:42:34 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.32 +Virtual_time_in_minutes: 0.00533333 +Virtual_time_in_hours: 8.88889e-05 +Virtual_time_in_days: 3.7037e-06 Ruby_current_time: 205611 Ruby_start_time: 0 Ruby_cycles: 205611 -mbytes_resident: 42.1211 -mbytes_total: 215.602 -resident_ratio: 0.195365 +mbytes_resident: 43.1602 +mbytes_total: 215.941 +resident_ratio: 0.19987 ruby_cycles_executed: [ 205612 ] @@ -127,10 +127,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11276 +page_reclaims: 11479 page_faults: 0 swaps: 0 -block_inputs: 16 +block_inputs: 0 block_outputs: 80 Network Stats diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 1f028aa91..4f76e711e 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 35d1a046f..863fa07d3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000206 # Nu sim_ticks 205611 # Number of ticks simulated final_tick 205611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2474305 # Simulator tick rate (ticks/s) -host_mem_usage 220780 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 2093129 # Simulator tick rate (ticks/s) +host_mem_usage 221128 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats index 3b6b0e305..1f17ccfc3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:56 +Real time: Jun/04/2012 13:52:42 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.29 -Virtual_time_in_minutes: 0.00483333 -Virtual_time_in_hours: 8.05556e-05 -Virtual_time_in_days: 3.35648e-06 +Virtual_time_in_seconds: 0.28 +Virtual_time_in_minutes: 0.00466667 +Virtual_time_in_hours: 7.77778e-05 +Virtual_time_in_days: 3.24074e-06 Ruby_current_time: 280571 Ruby_start_time: 0 Ruby_cycles: 280571 -mbytes_resident: 41.6914 -mbytes_total: 214.977 -resident_ratio: 0.193935 +mbytes_resident: 43.0117 +mbytes_total: 215.34 +resident_ratio: 0.199739 ruby_cycles_executed: [ 280572 ] @@ -121,11 +121,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11172 -page_faults: 0 +page_reclaims: 11376 +page_faults: 5 swaps: 0 -block_inputs: 0 -block_outputs: 72 +block_inputs: 432 +block_outputs: 80 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout index 4e724cd5b..d291e3597 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:52:42 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index c5e74a2ba..b210abac4 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000281 # Nu sim_ticks 280571 # Number of ticks simulated final_tick 280571 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2565590 # Simulator tick rate (ticks/s) -host_mem_usage 220140 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 3251259 # Simulator tick rate (ticks/s) +host_mem_usage 220512 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host ---------- End Simulation Statistics ---------- |