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-rwxr-xr-xsrc/arch/isa_parser.py20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 7edb9f3d7..95c57af2f 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
+# Gabe Black
# Korey Sewell
import os
@@ -1410,6 +1411,25 @@ class ControlRegOperand(Operand):
error(0, 'Attempt to write control register as FP')
wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
(self.dest_reg_idx, self.base_name)
+
+class ControlBitfieldOperand(ControlRegOperand):
+ def makeRead(self):
+ bit_select = 0
+ if (self.ctype == 'float' or self.ctype == 'double'):
+ error(0, 'Attempt to read control register as FP')
+ base = 'xc->readMiscReg(%s)' % self.reg_spec
+ name = self.base_name
+ return '%s = bits(%s, %s_HI, %s_LO);' % \
+ (name, base, name, name)
+
+ def makeWrite(self):
+ if (self.ctype == 'float' or self.ctype == 'double'):
+ error(0, 'Attempt to write control register as FP')
+ base = 'xc->readMiscReg(%s)' % self.reg_spec
+ name = self.base_name
+ wb_val = 'insertBits(%s, %s_HI, %s_LO, %s)' % \
+ (base, name, name, self.base_name)
+ wb = 'xc->setMiscRegOperand(this, %s, %s );\n' % (self.dest_reg_idx, wb_val)
wb += 'if (traceData) { traceData->setData(%s); }' % \
self.base_name
return wb