diff options
| -rw-r--r-- | src/arch/arm/fastmodel/iris/arm/thread_context.cc | 6 | ||||
| -rw-r--r-- | src/arch/arm/fastmodel/iris/arm/thread_context.hh | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc index 8a36ce3d3..c48ade817 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc @@ -201,6 +201,12 @@ ArmThreadContext::readVecReg(const RegId ®_id) const return reg; } +const ArmISA::VecRegContainer & +ArmThreadContext::readVecRegFlat(RegIndex idx) const +{ + return readVecReg(RegId(VecRegClass, idx)); +} + Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({ { ArmISA::MISCREG_CPSR, "CPSR" }, { ArmISA::MISCREG_SPSR, "SPSR" }, diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.hh b/src/arch/arm/fastmodel/iris/arm/thread_context.hh index c7f26e3bd..8344f57b8 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.hh @@ -83,6 +83,7 @@ class ArmThreadContext : public Iris::ThreadContext } const VecRegContainer &readVecReg(const RegId ®) const override; + const VecRegContainer &readVecRegFlat(RegIndex idx) const override; }; } // namespace Iris |