diff options
| -rw-r--r-- | src/arch/riscv/interrupts.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh index 729af6fb9..912bf45ca 100644 --- a/src/arch/riscv/interrupts.hh +++ b/src/arch/riscv/interrupts.hh @@ -125,10 +125,10 @@ class Interrupts : public SimObject ip = 0; } - MiscReg readIP() const { return (MiscReg)ip.to_ulong(); } - MiscReg readIE() const { return (MiscReg)ie.to_ulong(); } - void setIP(const MiscReg& val) { ip = val; } - void setIE(const MiscReg& val) { ie = val; } + uint64_t readIP() const { return (uint64_t)ip.to_ulong(); } + uint64_t readIE() const { return (uint64_t)ie.to_ulong(); } + void setIP(const uint64_t& val) { ip = val; } + void setIE(const uint64_t& val) { ie = val; } void serialize(CheckpointOut &cp) @@ -150,4 +150,4 @@ class Interrupts : public SimObject } // namespace RiscvISA -#endif // __ARCH_RISCV_INTERRUPT_HH__
\ No newline at end of file +#endif // __ARCH_RISCV_INTERRUPT_HH__ |