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-rw-r--r--src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py4
-rw-r--r--src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py
index 08296bd56..edabdc6e4 100644
--- a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py
+++ b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py
@@ -38,14 +38,14 @@
microcode = '''
def macroop MOVNTDQ_M_XMM {
- warn "MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!"
+ warn_once "MOVNTDQ: Ignoring non-temporal hint, modeling as cacheable!"
cda seg, sib, "DISPLACEMENT + 8", dataSize=8
stfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
};
def macroop MOVNTDQ_P_XMM {
- warn "MOVNTDQ_P: Ignoring non-temporal hint, modeling as cacheable!"
+ warn_once "MOVNTDQ_P: Ignoring non-temporal hint, modeling as cacheable!"
rdip t7
cda seg, riprel, "DISPLACEMENT + 8", dataSize=8
stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py
index ccd37f165..fdf303f37 100644
--- a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py
+++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py
@@ -38,12 +38,12 @@
microcode = '''
def macroop MOVNTQ_M_MMX {
- warn "MOVNTQ: Ignoring non-temporal hint, modeling as cacheable!"
+ warn_once "MOVNTQ: Ignoring non-temporal hint, modeling as cacheable!"
stfp mmx, seg, sib, "DISPLACEMENT", dataSize=8
};
def macroop MOVNTQ_P_MMX {
- warn "MOVNTQ_P: Ignoring non-temporal hint, modeling as cacheable!"
+ warn_once "MOVNTQ_P: Ignoring non-temporal hint, modeling as cacheable!"
rdip t7
stfp mmx, seg, riprel, "DISPLACEMENT", dataSize=8
};