diff options
Diffstat (limited to 'arch/alpha/alpha_memory.cc')
| -rw-r--r-- | arch/alpha/alpha_memory.cc | 72 |
1 files changed, 46 insertions, 26 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 23815bf01..31f5a9b20 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -44,6 +44,11 @@ using namespace std; // // Alpha TLB // +#ifdef DEBUG +bool uncacheBit39 = false; +bool uncacheBit40 = false; +#endif + AlphaTLB::AlphaTLB(const string &name, int s) : SimObject(name), size(s), nlu(0) { @@ -87,24 +92,27 @@ AlphaTLB::checkCacheability(MemReqPtr &req) { // in Alpha, cacheability is controlled by upper-level bits of the // physical address - if (req->paddr & PA_UNCACHED_BIT) { - if (PA_IPR_SPACE(req->paddr)) { - // IPR memory space not implemented - if (!req->xc->misspeculating()) { - switch (req->paddr) { - case ULL(0xFFFFF00188): - req->data = 0; - break; - - default: - panic("IPR memory space not implemented! PA=%x\n", - req->paddr); - } - } - } else { - // mark request as uncacheable - req->flags |= UNCACHEABLE; - } + + /* + * We support having the uncacheable bit in either bit 39 or bit 40. + * The Turbolaser platform (and EV5) support having the bit in 39, but + * Tsunami (which Linux assumes uses an EV6) generates accesses with + * the bit in 40. So we must check for both, but we have debug flags + * to catch a weird case where both are used, which shouldn't happen. + */ + + if (req->paddr & PA_UNCACHED_BIT_43) { + // IPR memory space not implemented + if (PA_IPR_SPACE(req->paddr)) + if (!req->xc->misspeculating()) + panic("IPR memory space not implemented! PA=%x\n", + req->paddr); + + // mark request as uncacheable + req->flags |= UNCACHEABLE; + + // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) + req->paddr &= PA_UNCACHED_MASK; } } @@ -290,10 +298,10 @@ AlphaITB::translate(MemReqPtr &req) const return ITB_Acv_Fault; } - // Check for "superpage" mapping: when SP<1> is set, and - // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>. - if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && - VA_SPACE(req->vaddr) == 2) { + + // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 + // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 + if (VA_SPACE_EV6(req->vaddr) == 0x7e) { // only valid in kernel mode if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) { @@ -303,6 +311,13 @@ AlphaITB::translate(MemReqPtr &req) const } req->paddr = req->vaddr & PA_IMPL_MASK; + + // sign extend the physical address properly + if (req->paddr & PA_UNCACHED_BIT_40) + req->paddr |= ULL(0xf0000000000); + else + req->paddr &= ULL(0xffffffffff); + } else { // not a physical address: need to look up pte AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr), @@ -468,10 +483,8 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const return DTB_Fault_Fault; } - // Check for "superpage" mapping: when SP<1> is set, and - // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>. - if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && - VA_SPACE(req->vaddr) == 2) { + // Check for "superpage" mapping + if (VA_SPACE_EV6(req->vaddr) == 0x7e) { // only valid in kernel mode if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != @@ -484,6 +497,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const } req->paddr = req->vaddr & PA_IMPL_MASK; + + // sign extend the physical address properly + if (req->paddr & PA_UNCACHED_BIT_40) + req->paddr |= ULL(0xf0000000000); + else + req->paddr &= ULL(0xffffffffff); + } else { if (write) write_accesses++; |