1 files changed, 8 insertions, 113 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 9d2ff4db7..11faf1850 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/tlb.hh"
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/osfpal.hh"
 #include "base/kgdb.h"
@@ -47,66 +47,22 @@ using namespace EV5;
 
 ////////////////////////////////////////////////////////////////////////
 //
-//
-//
-void
-AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
-{
-    if (regs->pal_shadow == use_shadow)
-        panic("swap_palshadow: wrong PAL shadow state");
-
-    regs->pal_shadow = use_shadow;
-
-    for (int i = 0; i < NumIntRegs; i++) {
-        if (reg_redir[i]) {
-            IntReg temp = regs->intRegFile[i];
-            regs->intRegFile[i] = regs->palregs[i];
-            regs->palregs[i] = temp;
-        }
-    }
-}
-
-////////////////////////////////////////////////////////////////////////
-//
 //  Machine dependent functions
 //
 void
 AlphaISA::initCPU(ExecContext *xc, int cpuId)
 {
     initIPRs(xc, cpuId);
-    // CPU comes up with PAL regs enabled
-    swap_palshadow(regs, true);
 
     xc->setIntReg(16, cpuId);
     xc->setIntReg(0, cpuId);
 
-    xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + fault_addr(ResetFault));
+    xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
     xc->setNextPC(xc->readPC() + sizeof(MachInst));
 }
 
 ////////////////////////////////////////////////////////////////////////
 //
-// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
-//
-const Addr
-AlphaISA::fault_addr(Fault fault)
-{
-        //Check for the system wide faults
-        if(fault == NoFault) return 0x0000;
-        else if(fault == MachineCheckFault) return 0x0401;
-        else if(fault == AlignmentFault) return 0x0301;
-        //Deal with the alpha specific faults
-        return ((AlphaFault*)fault)->vect;
-};
-
-const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
-    /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
-    /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
-    /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
-    /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
-
-////////////////////////////////////////////////////////////////////////
-//
 //
 //
 void
@@ -163,7 +119,7 @@ AlphaISA::processInterrupts(CPU *cpu)
     if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
         cpu->setMiscReg(IPR_ISR, summary);
         cpu->setMiscReg(IPR_INTID, ipl);
-        cpu->trap(InterruptFault);
+        cpu->trap(new InterruptFault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                 cpu->readMiscReg(IPR_IPLR), ipl, summary);
     }
@@ -181,78 +137,17 @@ AlphaISA::zeroRegisters(CPU *cpu)
     cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0);
 }
 
-void
-CPUExecContext::ev5_trap(Fault fault)
-{
-    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
-    cpu->recordEvent(csprintf("Fault %s", fault->name));
-
-    assert(!misspeculating());
-    cpu->kernelStats->fault(fault);
-
-    if (fault == ArithmeticFault)
-        panic("Arithmetic traps are unimplemented!");
-
-    // exception restart address
-    if (fault != InterruptFault || !inPalMode())
-        setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
-
-    if (fault == PalFault || fault == ArithmeticFault /* ||
-        fault == InterruptFault && !inPalMode() */) {
-        // traps...  skip faulting instruction
-        setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
-    }
-
-    if (!inPalMode())
-        AlphaISA::swap_palshadow(&regs, true);
-
-    regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) + AlphaISA::fault_addr(fault);
-    regs.npc = regs.pc + sizeof(MachInst);
-}
-
-
-void
-AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
-{
-    bool use_pc = (fault == NoFault);
-
-    if (fault == ArithmeticFault)
-        panic("arithmetic faults NYI...");
-
-    // compute exception restart address
-    if (use_pc || fault == PalFault || fault == ArithmeticFault) {
-        // traps...  skip faulting instruction
-        regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
-    } else {
-        // fault, post fault at excepting instruction
-        regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
-    }
-
-    // jump to expection address (PAL PC bit set here as well...)
-    if (!use_pc)
-        regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
-            fault_addr(fault);
-    else
-        regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
-
-    // that's it! (orders of magnitude less painful than x86)
-}
-
 Fault
 CPUExecContext::hwrei()
 {
     if (!inPalMode())
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
     setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
 
     if (!misspeculating()) {
         cpu->kernelStats->hwrei();
 
-        if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
-            AlphaISA::swap_palshadow(&regs, false);
-
         cpu->checkInterrupts = true;
     }
 
@@ -354,12 +249,12 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
       case AlphaISA::IPR_DTB_IAP:
       case AlphaISA::IPR_ITB_IA:
       case AlphaISA::IPR_ITB_IAP:
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
 
       default:
         // invalid IPR
-        fault = UnimplementedOpcodeFault;
+        fault = new UnimplementedOpcodeFault;
         break;
     }
 
@@ -523,7 +418,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
       case AlphaISA::IPR_ITB_PTE_TEMP:
       case AlphaISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
 
       case AlphaISA::IPR_HWINT_CLR:
       case AlphaISA::IPR_SL_XMIT:
@@ -627,7 +522,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
 
       default:
         // invalid IPR
-        return UnimplementedOpcodeFault;
+        return new UnimplementedOpcodeFault;
     }
 
     // no error...