1 files changed, 2 insertions, 34 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 2bb005eb4..c6da628be 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -164,41 +164,9 @@ AlphaISA::zeroRegisters(CPU *cpu)
 }
 
 void
-ExecContext::ev5_temp_trap(Fault fault)
-{
-    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
-    cpu->recordEvent(csprintf("Fault %s", fault->name()));
-
-    assert(!misspeculating());
-    kernelStats->fault(fault);
-
-    if (fault->isA<ArithmeticFault>())
-        panic("Arithmetic traps are unimplemented!");
-
-    // exception restart address
-    if (!fault->isA<InterruptFault>() || !inPalMode())
-        setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
-
-    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
-        fault == InterruptFault && !inPalMode() */) {
-        // traps...  skip faulting instruction.
-        setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
-    }
-
-    if (!inPalMode())
-        AlphaISA::swap_palshadow(&regs, true);
-
-    regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) +
-        (dynamic_cast<AlphaFault *>(fault.get()))->vect();
-    regs.npc = regs.pc + sizeof(MachInst);
-}
-
-
-void
 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 {
-    bool use_pc = (fault == NoFault);
+/*    bool use_pc = (fault == NoFault);
 
     if (fault->isA<ArithmeticFault>())
         panic("arithmetic faults NYI...");
@@ -218,7 +186,7 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
             (dynamic_cast<AlphaFault *>(fault.get()))->vect();
     else
         regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
-
+*/
     // that's it! (orders of magnitude less painful than x86)
 }