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-rw-r--r--arch/alpha/isa/fp.isa14
-rw-r--r--arch/alpha/isa/main.isa8
-rw-r--r--arch/alpha/isa/mem.isa52
-rw-r--r--arch/alpha/isa/unimp.isa4
-rw-r--r--arch/alpha/isa/unknown.isa2
5 files changed, 40 insertions, 40 deletions
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index c718c5524..7e81fb830 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -32,16 +32,16 @@ output exec {{
/// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault.
#if FULL_SYSTEM
- inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
+ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
- Fault * fault = NoFault; // dummy... this ipr access should not fault
+ Fault fault = NoFault; // dummy... this ipr access should not fault
if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
fault = FloatEnableFault;
}
return fault;
}
#else
- inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
+ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
return NoFault;
}
@@ -199,7 +199,7 @@ output decoder {{
// FP instruction class execute method template. Handles non-standard
// rounding modes.
def template FloatingPointExecute {{
- Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -208,7 +208,7 @@ def template FloatingPointExecute {{
warnedOnTrapping = true;
}
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@@ -242,7 +242,7 @@ def template FloatingPointExecute {{
// rounding mode control is needed. Like BasicExecute, but includes
// check & warning for non-standard trapping mode.
def template FPFixedRoundingExecute {{
- Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -251,7 +251,7 @@ def template FPFixedRoundingExecute {{
warnedOnTrapping = true;
}
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index 862b2b95e..b8d03c0be 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -258,7 +258,7 @@ output decoder {{
// Declarations for execute() methods.
def template BasicExecDeclare {{
- Fault * execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
@@ -287,10 +287,10 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
- Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@@ -382,7 +382,7 @@ output decoder {{
}};
output exec {{
- Fault *
+ Fault
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
return NoFault;
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 33b7341ef..61d6ea8fa 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -173,12 +173,12 @@ def template LoadStoreDeclare {{
def template InitiateAccDeclare {{
- Fault * initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
- Fault * completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
@@ -208,12 +208,12 @@ def template LoadStoreConstructor {{
def template EACompExecute {{
- Fault *
+ Fault
%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@@ -230,12 +230,12 @@ def template EACompExecute {{
}};
def template LoadMemAccExecute {{
- Fault *
+ Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@@ -257,11 +257,11 @@ def template LoadMemAccExecute {{
def template LoadExecute {{
- Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@@ -283,11 +283,11 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
- Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
@@ -304,11 +304,11 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
- Fault * %(class_name)s::completeAcc(uint8_t *data,
+ Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
@@ -330,12 +330,12 @@ def template LoadCompleteAcc {{
def template StoreMemAccExecute {{
- Fault *
+ Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -367,11 +367,11 @@ def template StoreMemAccExecute {{
def template StoreExecute {{
- Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -402,11 +402,11 @@ def template StoreExecute {{
}};
def template StoreInitiateAcc {{
- Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -431,11 +431,11 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
- Fault * %(class_name)s::completeAcc(uint8_t *data,
+ Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault * fault = NoFault;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -457,11 +457,11 @@ def template StoreCompleteAcc {{
def template MiscMemAccExecute {{
- Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@@ -477,11 +477,11 @@ def template MiscMemAccExecute {{
}};
def template MiscExecute {{
- Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
- Fault * fault = NoFault;
+ Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@@ -497,7 +497,7 @@ def template MiscExecute {{
}};
def template MiscInitiateAcc {{
- Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("Misc instruction does not support split access method!");
@@ -507,7 +507,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
- Fault * %(class_name)s::completeAcc(uint8_t *data,
+ Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index ce8197708..de4ac3eaf 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -105,7 +105,7 @@ output decoder {{
}};
output exec {{
- Fault *
+ Fault
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -114,7 +114,7 @@ output exec {{
return UnimplementedOpcodeFault;
}
- Fault *
+ Fault
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa
index e7f8bc8db..4601b3684 100644
--- a/arch/alpha/isa/unknown.isa
+++ b/arch/alpha/isa/unknown.isa
@@ -36,7 +36,7 @@ output decoder {{
}};
output exec {{
- Fault *
+ Fault
Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 23:22:31 +0000