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-rw-r--r--arch/alpha/isa/decoder.isa38
-rw-r--r--arch/alpha/isa/fp.isa7
-rw-r--r--arch/alpha/isa/main.isa6
-rw-r--r--arch/alpha/isa/unimp.isa2
-rw-r--r--arch/alpha/isa/unknown.isa2
5 files changed, 29 insertions, 26 deletions
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index b93b6575c..2fb3fbd2a 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() {
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp;
}});
0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
@@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() {
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = tmp;
}});
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() {
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp;
}});
0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
@@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() {
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = tmp;
}});
0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() {
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp<31:0>;
}}, IntMultOp);
0x60: mulqv({{
@@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() {
// the lower 64
if (!((hi == 0 && lo<63:> == 0) ||
(hi == mask(64) && lo<63:> == 1)))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = lo;
}}, IntMultOp);
}
@@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() {
#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
#else
0x0b: sqrts({{
if (Fb.sf < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc.sf = sqrt(Fb.sf);
}}, FloatSqrtOp);
#endif
0x2b: sqrtt({{
if (Fb < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
}
@@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() {
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = Fb.uq<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
}});
@@ -618,7 +618,7 @@ decode OPCODE default Unknown::unknown() {
/* Rb is a fake dependency so here is a fun way to get
* the parser to understand that.
*/
- Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
+ Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
#else
Ra = curTick;
@@ -670,10 +670,10 @@ decode OPCODE default Unknown::unknown() {
0x00: CallPal::call_pal({{
if (!palValid ||
(palPriv
- && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
+ && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
// invalid pal function code, or attempt to do privileged
// PAL call in non-kernel mode
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
// check to see if simulator wants to do something special
@@ -682,8 +682,8 @@ decode OPCODE default Unknown::unknown() {
if (dopal) {
AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
- xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
- NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
+ xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
+ NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
}
}
}}, IsNonSpeculative);
@@ -729,19 +729,19 @@ decode OPCODE default Unknown::unknown() {
0x19: hw_mfpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
- Ra = xc->readIpr(ipr_index, fault);
+ Ra = xc->readMiscRegWithEffect(ipr_index, fault);
}
}});
0x1d: hw_mtpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
- xc->setIpr(ipr_index, Ra);
+ xc->setMiscRegWithEffect(ipr_index, Ra);
if (traceData) { traceData->setData(Ra); }
}
}});
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index 7e81fb830..13656359f 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -35,8 +35,8 @@ output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
- if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
- fault = FloatEnableFault;
+ if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) {
+ fault = new FloatEnableFault;
}
return fault;
}
@@ -217,7 +217,8 @@ def template FloatingPointExecute {{
if (roundingMode == Normal) {
%(code)s;
} else {
- fesetround(getC99RoundingMode(xc->readFpcr()));
+ fesetround(getC99RoundingMode(
+ xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
%(code)s;
fesetround(FE_TONEAREST);
}
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index b8d03c0be..ad9c2a55e 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -161,8 +161,8 @@ def operands {{
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
- 'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
- 'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1),
+ 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
+ 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),
@@ -194,6 +194,8 @@ output header {{
FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
Uniq_DepTag = AlphaISA::Uniq_DepTag,
+ Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
+ Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
};
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index de4ac3eaf..09df39706 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -111,7 +111,7 @@ output exec {{
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
Fault
diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa
index 4601b3684..47d166255 100644
--- a/arch/alpha/isa/unknown.isa
+++ b/arch/alpha/isa/unknown.isa
@@ -42,7 +42,7 @@ output exec {{
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
}};
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-15 09:37:47 +0000