1 files changed, 48 insertions, 8 deletions

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index aaf0cb0a7..e34739b86 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -28,7 +28,9 @@ let {{
 #include "cpu/simple_cpu/simple_cpu.hh"
 #include "cpu/static_inst.hh"
 #include "sim/annotation.hh"
+#include "sim/serialize.hh"
 #include "sim/sim_events.hh"
+#include "sim/sim_stats.hh"
 
 #ifdef FULL_SYSTEM
 #include "targetarch/ev5.hh"
@@ -2431,20 +2433,58 @@ decode OPCODE default Unknown::unknown() {
 	    }}, No_OpClass);
 	    0x21: m5exit({{
 		if (!xc->misspeculating()) {
-		    Tick when = curTick;
 		    Tick delay = xc->regs.intRegFile[16];
-		    if (delay != 0) {
-			delay *= ticksPerUS;
-			delay /= 1000;
-			when += delay;
-		    }
+		    Tick when = curTick + NS2Ticks(delay);
 		    SimExit(when, "m5_exit instruction encountered");
 		}
 	    }}, No_OpClass);
             0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
             0x40: resetstats({{
-		if (!xc->misspeculating())
-		    Statistics::reset();
+		if (!xc->misspeculating()) {
+		    using namespace Statistics;
+		    Tick delay = xc->regs.intRegFile[16];
+		    Tick period = xc->regs.intRegFile[17];
+
+		    Tick when = curTick + NS2Ticks(delay);
+		    Tick repeat = NS2Ticks(period);
+
+		    SetupEvent(Reset, when, repeat);
+		}
+	    }});
+            0x41: dumpstats({{
+		if (!xc->misspeculating()) {
+		    using namespace Statistics;
+		    Tick delay = xc->regs.intRegFile[16];
+		    Tick period = xc->regs.intRegFile[17];
+
+		    Tick when = curTick + NS2Ticks(delay);
+		    Tick repeat = NS2Ticks(period);
+
+		    SetupEvent(Dump, when, repeat);
+		}
+	    }});
+            0x42: dumpresetstats({{
+		if (!xc->misspeculating()) {
+		    using namespace Statistics;
+		    Tick delay = xc->regs.intRegFile[16];
+		    Tick period = xc->regs.intRegFile[17];
+
+		    Tick when = curTick + NS2Ticks(delay);
+		    Tick repeat = NS2Ticks(period);
+
+		    SetupEvent(Dump|Reset, when, repeat);
+		}
+	    }});
+            0x43: m5checkpoint({{
+		if (!xc->misspeculating()) {
+		    Tick delay = xc->regs.intRegFile[16];
+		    Tick period = xc->regs.intRegFile[17];
+
+		    Tick when = curTick + NS2Ticks(delay);
+		    Tick repeat = NS2Ticks(period);
+
+		    SetupCheckpoint(when, repeat);
+		}
 	    }});
 	}
     }