summaryrefslogtreecommitdiff
path: root/arch/alpha/isa_traits.hh
diff options
context:
space:
mode:
Diffstat (limited to 'arch/alpha/isa_traits.hh')
-rw-r--r--arch/alpha/isa_traits.hh10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 05ab89978..37ba77192 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -33,6 +33,7 @@
#include "targetarch/faults.hh"
#include "base/misc.hh"
+class FastCPU;
class FullCPU;
class Checkpoint;
@@ -156,8 +157,6 @@ class AlphaISA
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
#endif // FULL_SYSTEM
- // Are these architectural, or just for convenience?
- uint8_t opcode, ra; // current instruction details (for intr's)
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
@@ -233,6 +232,13 @@ class AlphaISA
ConfigNode *node,
RegFile &regs);
#endif
+
+ /**
+ * Function to insure ISA semantics about 0 registers.
+ * @param xc The execution context.
+ */
+ template <class XC>
+ static void zeroRegisters(XC *xc);
};