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-rw-r--r--arch/alpha/tlb.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc
index 562235ef8..3f991b10c 100644
--- a/arch/alpha/tlb.cc
+++ b/arch/alpha/tlb.cc
@@ -94,7 +94,7 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const
void
-AlphaTLB::checkCacheability(MemReqPtr &req)
+AlphaTLB::checkCacheability(CpuRequestPtr &req)
{
// in Alpha, cacheability is controlled by upper-level bits of the
// physical address
@@ -292,7 +292,7 @@ AlphaITB::regStats()
Fault
-AlphaITB::translate(MemReqPtr &req) const
+AlphaITB::translate(CpuRequestPtr &req) const
{
ExecContext *xc = req->xc;
@@ -451,7 +451,7 @@ AlphaDTB::regStats()
}
Fault
-AlphaDTB::translate(MemReqPtr &req, bool write) const
+AlphaDTB::translate(CpuRequestPtr &req, bool write) const
{
ExecContext *xc = req->xc;
Addr pc = xc->readPC();