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-rw-r--r--arch/alpha/SConscript8
-rw-r--r--arch/alpha/ev5.cc147
-rw-r--r--arch/alpha/faults.cc120
-rw-r--r--arch/alpha/faults.hh256
-rw-r--r--arch/alpha/isa/decoder.isa38
-rw-r--r--arch/alpha/isa/fp.isa7
-rw-r--r--arch/alpha/isa/main.isa6
-rw-r--r--arch/alpha/isa/unimp.isa2
-rw-r--r--arch/alpha/isa/unknown.isa2
-rw-r--r--arch/alpha/isa_traits.hh55
-rw-r--r--arch/alpha/linux_process.cc (renamed from arch/alpha/alpha_linux_process.cc)4
-rw-r--r--arch/alpha/linux_process.hh (renamed from arch/alpha/alpha_linux_process.hh)0
-rw-r--r--arch/alpha/stacktrace.cc14
-rw-r--r--arch/alpha/tlb.cc (renamed from arch/alpha/alpha_memory.cc)79
-rw-r--r--arch/alpha/tlb.hh (renamed from arch/alpha/alpha_memory.hh)0
-rw-r--r--arch/alpha/tru64_process.cc (renamed from arch/alpha/alpha_tru64_process.cc)4
-rw-r--r--arch/alpha/tru64_process.hh (renamed from arch/alpha/alpha_tru64_process.hh)0
-rw-r--r--arch/alpha/vtophys.cc2
18 files changed, 462 insertions, 282 deletions
diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript
index 050dfb9cf..3b0e69b7a 100644
--- a/arch/alpha/SConscript
+++ b/arch/alpha/SConscript
@@ -50,7 +50,7 @@ base_sources = Split('''
# Full-system sources
full_system_sources = Split('''
- alpha_memory.cc
+ tlb.cc
arguments.cc
ev5.cc
osfpal.cc
@@ -61,9 +61,9 @@ full_system_sources = Split('''
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
- alpha_common_syscall_emul.cc
- alpha_linux_process.cc
- alpha_tru64_process.cc
+ common_syscall_emul.cc
+ linux_process.cc
+ tru64_process.cc
''')
# Set up complete list of sources based on configuration.
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 14b87b16f..2bb005eb4 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/tlb.hh"
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/osfpal.hh"
#include "base/kgdb.h"
@@ -72,32 +72,17 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
void
AlphaISA::initCPU(RegFile *regs, int cpuId)
{
- initIPRs(regs, cpuId);
+ initIPRs(&regs->miscRegs, cpuId);
// CPU comes up with PAL regs enabled
swap_palshadow(regs, true);
regs->intRegFile[16] = cpuId;
regs->intRegFile[0] = cpuId;
- regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
+ regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + (new ResetFault)->vect();
regs->npc = regs->pc + sizeof(MachInst);
}
-////////////////////////////////////////////////////////////////////////
-//
-// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
-//
-const Addr
-AlphaISA::fault_addr(Fault fault)
-{
- //Check for the system wide faults
- if(fault == NoFault) return 0x0000;
- else if(fault == MachineCheckFault) return 0x0401;
- else if(fault == AlignmentFault) return 0x0301;
- //Deal with the alpha specific faults
- return ((AlphaFault*)fault)->vect;
-};
-
const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
/* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
@@ -109,14 +94,13 @@ const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
//
//
void
-AlphaISA::initIPRs(RegFile *regs, int cpuId)
+AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId)
{
- uint64_t *ipr = regs->ipr;
+ miscRegs->clearIprs();
- bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
- ipr[IPR_PAL_BASE] = PalBase;
- ipr[IPR_MCSR] = 0x6;
- ipr[IPR_PALtemp16] = cpuId;
+ miscRegs->setReg(IPR_PAL_BASE, PalBase);
+ miscRegs->setReg(IPR_MCSR, 0x6);
+ miscRegs->setReg(IPR_PALtemp16, cpuId);
}
@@ -128,17 +112,16 @@ AlphaISA::processInterrupts(CPU *cpu)
//Handle the interrupts
int ipl = 0;
int summary = 0;
- IntReg *ipr = cpu->getIprPtr();
cpu->checkInterrupts = false;
- if (ipr[IPR_ASTRR])
+ if (cpu->readMiscReg(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
- if (ipr[IPR_SIRR]) {
+ if (cpu->readMiscReg(IPR_SIRR)) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+ if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of the 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
@@ -159,12 +142,12 @@ AlphaISA::processInterrupts(CPU *cpu)
}
}
- if (ipl && ipl > ipr[IPR_IPLR]) {
- ipr[IPR_ISR] = summary;
- ipr[IPR_INTID] = ipl;
- cpu->trap(InterruptFault);
+ if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
+ cpu->setMiscReg(IPR_ISR, summary);
+ cpu->setMiscReg(IPR_INTID, ipl);
+ cpu->trap(new InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- ipr[IPR_IPLR], ipl, summary);
+ cpu->readMiscReg(IPR_IPLR), ipl, summary);
}
}
@@ -181,33 +164,33 @@ AlphaISA::zeroRegisters(CPU *cpu)
}
void
-ExecContext::ev5_trap(Fault fault)
+ExecContext::ev5_temp_trap(Fault fault)
{
- DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
- cpu->recordEvent(csprintf("Fault %s", fault->name));
+ DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
+ cpu->recordEvent(csprintf("Fault %s", fault->name()));
assert(!misspeculating());
kernelStats->fault(fault);
- if (fault == ArithmeticFault)
+ if (fault->isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
- AlphaISA::InternalProcReg *ipr = regs.ipr;
-
// exception restart address
- if (fault != InterruptFault || !inPalMode())
- ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
+ if (!fault->isA<InterruptFault>() || !inPalMode())
+ setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
- if (fault == PalFault || fault == ArithmeticFault /* ||
+ if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
fault == InterruptFault && !inPalMode() */) {
- // traps... skip faulting instruction
- ipr[AlphaISA::IPR_EXC_ADDR] += 4;
+ // traps... skip faulting instruction.
+ setMiscReg(AlphaISA::IPR_EXC_ADDR,
+ readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
if (!inPalMode())
AlphaISA::swap_palshadow(&regs, true);
- regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
+ regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) +
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect();
regs.npc = regs.pc + sizeof(MachInst);
}
@@ -215,26 +198,26 @@ ExecContext::ev5_trap(Fault fault)
void
AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
{
- InternalProcReg *ipr = regs->ipr;
bool use_pc = (fault == NoFault);
- if (fault == ArithmeticFault)
+ if (fault->isA<ArithmeticFault>())
panic("arithmetic faults NYI...");
// compute exception restart address
- if (use_pc || fault == PalFault || fault == ArithmeticFault) {
+ if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
// traps... skip faulting instruction
- ipr[IPR_EXC_ADDR] = regs->pc + 4;
+ regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
} else {
// fault, post fault at excepting instruction
- ipr[IPR_EXC_ADDR] = regs->pc;
+ regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
}
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
- regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
+ regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect();
else
- regs->npc = ipr[IPR_PAL_BASE] + pc;
+ regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
// that's it! (orders of magnitude less painful than x86)
}
@@ -242,17 +225,15 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
Fault
ExecContext::hwrei()
{
- uint64_t *ipr = regs.ipr;
-
if (!inPalMode())
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
- setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+ setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
if (!misspeculating()) {
kernelStats->hwrei();
- if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
+ if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
AlphaISA::swap_palshadow(&regs, false);
cpu->checkInterrupts = true;
@@ -262,10 +243,15 @@ ExecContext::hwrei()
return NoFault;
}
-uint64_t
-ExecContext::readIpr(int idx, Fault &fault)
+void
+AlphaISA::MiscRegFile::clearIprs()
+{
+ bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
+}
+
+AlphaISA::MiscReg
+AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
{
- uint64_t *ipr = regs.ipr;
uint64_t retval = 0; // return value, default 0
switch (idx) {
@@ -318,7 +304,7 @@ ExecContext::readIpr(int idx, Fault &fault)
case AlphaISA::IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
- retval |= cpu->curCycle() & ULL(0x00000000ffffffff);
+ retval |= xc->cpu->curCycle() & ULL(0x00000000ffffffff);
break;
case AlphaISA::IPR_VA:
@@ -335,7 +321,7 @@ ExecContext::readIpr(int idx, Fault &fault)
case AlphaISA::IPR_DTB_PTE:
{
- AlphaISA::PTE &pte = dtb->index(!misspeculating());
+ AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -357,12 +343,12 @@ ExecContext::readIpr(int idx, Fault &fault)
case AlphaISA::IPR_DTB_IAP:
case AlphaISA::IPR_ITB_IA:
case AlphaISA::IPR_ITB_IAP:
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
break;
default:
// invalid IPR
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
break;
}
@@ -375,12 +361,11 @@ int break_ipl = -1;
#endif
Fault
-ExecContext::setIpr(int idx, uint64_t val)
+AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
{
- uint64_t *ipr = regs.ipr;
uint64_t old;
- if (misspeculating())
+ if (xc->misspeculating())
return NoFault;
switch (idx) {
@@ -433,7 +418,7 @@ ExecContext::setIpr(int idx, uint64_t val)
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
- kernelStats->context(old, val);
+ xc->kernelStats->context(old, val);
break;
case AlphaISA::IPR_DTB_PTE:
@@ -460,14 +445,14 @@ ExecContext::setIpr(int idx, uint64_t val)
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
- kernelStats->swpipl(ipr[idx]);
+ xc->kernelStats->swpipl(ipr[idx]);
break;
case AlphaISA::IPR_DTB_CM:
if (val & 0x18)
- kernelStats->mode(Kernel::user);
+ xc->kernelStats->mode(Kernel::user);
else
- kernelStats->mode(Kernel::kernel);
+ xc->kernelStats->mode(Kernel::kernel);
case AlphaISA::IPR_ICM:
// only write two mode bits - processor mode
@@ -527,7 +512,7 @@ ExecContext::setIpr(int idx, uint64_t val)
case AlphaISA::IPR_ITB_PTE_TEMP:
case AlphaISA::IPR_DTB_PTE_TEMP:
// read-only registers
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
case AlphaISA::IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT:
@@ -541,21 +526,21 @@ ExecContext::setIpr(int idx, uint64_t val)
// really a control write
ipr[idx] = 0;
- dtb->flushAll();
+ xc->dtb->flushAll();
break;
case AlphaISA::IPR_DTB_IAP:
// really a control write
ipr[idx] = 0;
- dtb->flushProcesses();
+ xc->dtb->flushProcesses();
break;
case AlphaISA::IPR_DTB_IS:
// really a control write
ipr[idx] = val;
- dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+ xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
break;
case AlphaISA::IPR_DTB_TAG: {
@@ -578,7 +563,7 @@ ExecContext::setIpr(int idx, uint64_t val)
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
- dtb->insert(val, pte);
+ xc->dtb->insert(val, pte);
}
break;
@@ -602,7 +587,7 @@ ExecContext::setIpr(int idx, uint64_t val)
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
- itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
+ xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
}
break;
@@ -610,26 +595,26 @@ ExecContext::setIpr(int idx, uint64_t val)
// really a control write
ipr[idx] = 0;
- itb->flushAll();
+ xc->itb->flushAll();
break;
case AlphaISA::IPR_ITB_IAP:
// really a control write
ipr[idx] = 0;
- itb->flushProcesses();
+ xc->itb->flushProcesses();
break;
case AlphaISA::IPR_ITB_IS:
// really a control write
ipr[idx] = val;
- itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
+ xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
break;
default:
// invalid IPR
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
// no error...
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index fa4950198..78613761d 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -27,37 +27,95 @@
*/
#include "arch/alpha/faults.hh"
+#include "cpu/exec_context.hh"
-ResetFaultType * const ResetFault =
- new ResetFaultType("reset", 1, 0x0001);
-ArithmeticFaultType * const ArithmeticFault =
- new ArithmeticFaultType("arith", 3, 0x0501);
-InterruptFaultType * const InterruptFault =
- new InterruptFaultType("interrupt", 4, 0x0101);
-NDtbMissFaultType * const NDtbMissFault =
- new NDtbMissFaultType("dtb_miss_single", 5, 0x0201);
-PDtbMissFaultType * const PDtbMissFault =
- new PDtbMissFaultType("dtb_miss_double", 6, 0x0281);
-DtbPageFaultType * const DtbPageFault =
- new DtbPageFaultType("dfault", 8, 0x0381);
-DtbAcvFaultType * const DtbAcvFault =
- new DtbAcvFaultType("dfault", 9, 0x0381);
-ItbMissFaultType * const ItbMissFault =
- new ItbMissFaultType("itbmiss", 10, 0x0181);
-ItbPageFaultType * const ItbPageFault =
- new ItbPageFaultType("itbmiss", 11, 0x0181);
-ItbAcvFaultType * const ItbAcvFault =
- new ItbAcvFaultType("iaccvio", 12, 0x0081);
-UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault =
- new UnimplementedOpcodeFaultType("opdec", 13, 0x0481);
-FloatEnableFaultType * const FloatEnableFault =
- new FloatEnableFaultType("fen", 14, 0x0581);
-PalFaultType * const PalFault =
- new PalFaultType("pal", 15, 0x2001);
-IntegerOverflowFaultType * const IntegerOverflowFault =
- new IntegerOverflowFaultType("intover", 16, 0x0501);
-
-Fault * ListOfFaults[] = {
+namespace AlphaISA
+{
+
+FaultVect AlphaMachineCheckFault::_vect = 0x0401;
+FaultStat AlphaMachineCheckFault::_stat;
+
+FaultVect AlphaAlignmentFault::_vect = 0x0301;
+FaultStat AlphaAlignmentFault::_stat;
+
+FaultName ResetFault::_name = "reset";
+FaultVect ResetFault::_vect = 0x0001;
+FaultStat ResetFault::_stat;
+
+FaultName ArithmeticFault::_name = "arith";
+FaultVect ArithmeticFault::_vect = 0x0501;
+FaultStat ArithmeticFault::_stat;
+
+FaultName InterruptFault::_name = "interrupt";
+FaultVect InterruptFault::_vect = 0x0101;
+FaultStat InterruptFault::_stat;
+
+FaultName NDtbMissFault::_name = "dtb_miss_single";
+FaultVect NDtbMissFault::_vect = 0x0201;
+FaultStat NDtbMissFault::_stat;
+
+FaultName PDtbMissFault::_name = "dtb_miss_double";
+FaultVect PDtbMissFault::_vect = 0x0281;
+FaultStat PDtbMissFault::_stat;
+
+FaultName DtbPageFault::_name = "dfault";
+FaultVect DtbPageFault::_vect = 0x0381;
+FaultStat DtbPageFault::_stat;
+
+FaultName DtbAcvFault::_name = "dfault";
+FaultVect DtbAcvFault::_vect = 0x0381;
+FaultStat DtbAcvFault::_stat;
+
+FaultName ItbMissFault::_name = "itbmiss";
+FaultVect ItbMissFault::_vect = 0x0181;
+FaultStat ItbMissFault::_stat;
+
+FaultName ItbPageFault::_name = "itbmiss";
+FaultVect ItbPageFault::_vect = 0x0181;
+FaultStat ItbPageFault::_stat;
+
+FaultName ItbAcvFault::_name = "iaccvio";
+FaultVect ItbAcvFault::_vect = 0x0081;
+FaultStat ItbAcvFault::_stat;
+
+FaultName UnimplementedOpcodeFault::_name = "opdec";
+FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
+FaultStat UnimplementedOpcodeFault::_stat;
+
+FaultName FloatEnableFault::_name = "fen";
+FaultVect FloatEnableFault::_vect = 0x0581;
+FaultStat FloatEnableFault::_stat;
+
+FaultName PalFault::_name = "pal";
+FaultVect PalFault::_vect = 0x2001;
+FaultStat PalFault::_stat;
+
+FaultName IntegerOverflowFault::_name = "intover";
+FaultVect IntegerOverflowFault::_vect = 0x0501;
+FaultStat IntegerOverflowFault::_stat;
+
+#if FULL_SYSTEM
+
+void AlphaFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+void AlphaMachineCheckFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+void AlphaAlignmentFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+#endif
+
+} // namespace AlphaISA
+
+/*Fault * ListOfFaults[] = {
(Fault *)&NoFault,
(Fault *)&ResetFault,
(Fault *)&MachineCheckFault,
@@ -77,4 +135,4 @@ Fault * ListOfFaults[] = {
(Fault *)&IntegerOverflowFault,
};
-int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);
+int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 3e25adc4e..156faa8fb 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -30,131 +30,231 @@
#define __ALPHA_FAULTS_HH__
#include "sim/faults.hh"
-#include "arch/isa_traits.hh" //For the Addr type
-class AlphaFault : public FaultBase
+// The design of the "name" and "vect" functions is in sim/faults.hh
+
+namespace AlphaISA
+{
+
+typedef const Addr FaultVect;
+
+class AlphaFault : public virtual FaultBase
{
public:
- AlphaFault(char * newName, int newId, Addr newVect)
- : FaultBase(newName, newId), vect(newVect)
- {;}
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
+ virtual FaultVect vect() = 0;
+};
- Addr vect;
+class AlphaMachineCheckFault :
+ public MachineCheckFault,
+ public AlphaFault
+{
+ private:
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
};
-extern class ResetFaultType : public AlphaFault
+class AlphaAlignmentFault :
+ public AlignmentFault,
+ public AlphaFault
{
+ private:
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ResetFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ResetFault;
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class ArithmeticFaultType : public AlphaFault
+static inline Fault genMachineCheckFault()
{
+ return new AlphaMachineCheckFault;
+}
+
+static inline Fault genAlignmentFault()
+{
+ return new AlphaAlignmentFault;
+}
+
+class ResetFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ArithmeticFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ArithmeticFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class InterruptFaultType : public AlphaFault
+class ArithmeticFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- InterruptFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const InterruptFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class NDtbMissFaultType : public AlphaFault
+class InterruptFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- NDtbMissFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const NDtbMissFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class PDtbMissFaultType : public AlphaFault
+class NDtbMissFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- PDtbMissFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const PDtbMissFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class DtbPageFaultType : public AlphaFault
+class PDtbMissFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- DtbPageFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const DtbPageFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class DtbAcvFaultType : public AlphaFault
+class DtbPageFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- DtbAcvFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const DtbAcvFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
+
+class DtbAcvFault : public AlphaFault
+{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
+ public:
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class ItbMissFaultType : public AlphaFault
+class ItbMissFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ItbMissFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ItbMissFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class ItbPageFaultType : public AlphaFault
+class ItbPageFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ItbPageFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ItbPageFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class ItbAcvFaultType : public AlphaFault
+class ItbAcvFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- ItbAcvFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const ItbAcvFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class UnimplementedOpcodeFaultType : public AlphaFault
+class UnimplementedOpcodeFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const UnimplementedOpcodeFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class FloatEnableFaultType : public AlphaFault
+class FloatEnableFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- FloatEnableFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const FloatEnableFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class PalFaultType : public AlphaFault
+class PalFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- PalFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const PalFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern class IntegerOverflowFaultType : public AlphaFault
+class IntegerOverflowFault : public AlphaFault
{
+ private:
+ static FaultName _name;
+ static FaultVect _vect;
+ static FaultStat _stat;
public:
- IntegerOverflowFaultType(char * newName, int newId, Addr newVect)
- : AlphaFault(newName, newId, newVect)
- {;}
-} * const IntegerOverflowFault;
+ FaultName name() {return _name;}
+ FaultVect vect() {return _vect;}
+ FaultStat & stat() {return _stat;}
+};
-extern Fault * ListOfFaults[];
-extern int NumFaults;
+} // AlphaISA namespace
#endif // __FAULTS_HH__
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index b93b6575c..2fb3fbd2a 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() {
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp;
}});
0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
@@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() {
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = tmp;
}});
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() {
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp;
}});
0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
@@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() {
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = tmp;
}});
0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() {
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc.sl = tmp<31:0>;
}}, IntMultOp);
0x60: mulqv({{
@@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() {
// the lower 64
if (!((hi == 0 && lo<63:> == 0) ||
(hi == mask(64) && lo<63:> == 1)))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Rc = lo;
}}, IntMultOp);
}
@@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() {
#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
#else
0x0b: sqrts({{
if (Fb.sf < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc.sf = sqrt(Fb.sf);
}}, FloatSqrtOp);
#endif
0x2b: sqrtt({{
if (Fb < 0.0)
- fault = ArithmeticFault;
+ fault = new ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
}
@@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() {
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = Fb.uq<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = IntegerOverflowFault;
+ fault = new IntegerOverflowFault;
Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
}});
@@ -618,7 +618,7 @@ decode OPCODE default Unknown::unknown() {
/* Rb is a fake dependency so here is a fun way to get
* the parser to understand that.
*/
- Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
+ Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
#else
Ra = curTick;
@@ -670,10 +670,10 @@ decode OPCODE default Unknown::unknown() {
0x00: CallPal::call_pal({{
if (!palValid ||
(palPriv
- && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
+ && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
// invalid pal function code, or attempt to do privileged
// PAL call in non-kernel mode
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
// check to see if simulator wants to do something special
@@ -682,8 +682,8 @@ decode OPCODE default Unknown::unknown() {
if (dopal) {
AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
- xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
- NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
+ xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
+ NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
}
}
}}, IsNonSpeculative);
@@ -729,19 +729,19 @@ decode OPCODE default Unknown::unknown() {
0x19: hw_mfpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
- Ra = xc->readIpr(ipr_index, fault);
+ Ra = xc->readMiscRegWithEffect(ipr_index, fault);
}
}});
0x1d: hw_mtpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
}
else {
- xc->setIpr(ipr_index, Ra);
+ xc->setMiscRegWithEffect(ipr_index, Ra);
if (traceData) { traceData->setData(Ra); }
}
}});
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index 7e81fb830..13656359f 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -35,8 +35,8 @@ output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
- if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
- fault = FloatEnableFault;
+ if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) {
+ fault = new FloatEnableFault;
}
return fault;
}
@@ -217,7 +217,8 @@ def template FloatingPointExecute {{
if (roundingMode == Normal) {
%(code)s;
} else {
- fesetround(getC99RoundingMode(xc->readFpcr()));
+ fesetround(getC99RoundingMode(
+ xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
%(code)s;
fesetround(FE_TONEAREST);
}
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index b8d03c0be..ad9c2a55e 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -161,8 +161,8 @@ def operands {{
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
- 'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
- 'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1),
+ 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
+ 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),
@@ -194,6 +194,8 @@ output header {{
FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
Uniq_DepTag = AlphaISA::Uniq_DepTag,
+ Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
+ Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
};
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index de4ac3eaf..09df39706 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -111,7 +111,7 @@ output exec {{
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
Fault
diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa
index 4601b3684..47d166255 100644
--- a/arch/alpha/isa/unknown.isa
+++ b/arch/alpha/isa/unknown.isa
@@ -42,7 +42,7 @@ output exec {{
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
}};
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index f47e90f86..938ba696e 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -38,6 +38,7 @@ using namespace LittleEndianGuest;
#include "sim/host.hh"
#include "sim/faults.hh"
+class ExecContext;
class FastCPU;
class FullCPU;
class Checkpoint;
@@ -64,6 +65,7 @@ namespace AlphaISA
NumIntRegs = 32,
NumFloatRegs = 32,
+ // @todo: Figure out what this number really should be.
NumMiscRegs = 32,
MaxRegsOfAnyType = 32,
@@ -106,7 +108,9 @@ namespace AlphaISA
Ctrl_Base_DepTag = 64,
Fpcr_DepTag = 64, // floating point control register
Uniq_DepTag = 65,
- IPR_Base_DepTag = 66
+ Lock_Flag_DepTag = 66,
+ Lock_Addr_DepTag = 67,
+ IPR_Base_DepTag = 68
};
typedef uint64_t IntReg;
@@ -123,15 +127,6 @@ namespace AlphaISA
double d[NumFloatRegs]; // double-precision floating point view
} FloatRegFile;
- // control register file contents
- typedef uint64_t MiscReg;
- typedef struct {
- uint64_t fpcr; // floating point condition codes
- uint64_t uniq; // process-unique register
- bool lock_flag; // lock flag for LL/SC
- Addr lock_addr; // lock address for LL/SC
- } MiscRegFile;
-
extern const Addr PageShift;
extern const Addr PageBytes;
extern const Addr PageMask;
@@ -149,6 +144,39 @@ extern const Addr PageOffset;
};
#endif
+ // control register file contents
+ typedef uint64_t MiscReg;
+ class MiscRegFile {
+ protected:
+ uint64_t fpcr; // floating point condition codes
+ uint64_t uniq; // process-unique register
+ bool lock_flag; // lock flag for LL/SC
+ Addr lock_addr; // lock address for LL/SC
+
+ public:
+ MiscReg readReg(int misc_reg);
+
+ MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
+
+ Fault setReg(int misc_reg, const MiscReg &val);
+
+ Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+ ExecContext *xc);
+
+#if FULL_SYSTEM
+ void clearIprs();
+
+ protected:
+ InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
+
+ private:
+ MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
+
+ Fault setIpr(int idx, uint64_t val, ExecContext *xc);
+#endif
+ friend class RegFile;
+ };
+
enum {
TotalNumRegs =
NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
@@ -172,11 +200,12 @@ extern const Addr PageOffset;
Addr npc; // next-cycle program counter
#if FULL_SYSTEM
IntReg palregs[NumIntRegs]; // PAL shadow registers
- InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
- inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
- inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
+ inline int instAsid()
+ { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
+ inline int dataAsid()
+ { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
#endif // FULL_SYSTEM
void serialize(std::ostream &os);
diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/linux_process.cc
index 16ebcca7b..0b193fb55 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/linux_process.cc
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/alpha/alpha_common_syscall_emul.hh"
-#include "arch/alpha/alpha_linux_process.hh"
+#include "arch/alpha/common_syscall_emul.hh"
+#include "arch/alpha/linux_process.hh"
#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
diff --git a/arch/alpha/alpha_linux_process.hh b/arch/alpha/linux_process.hh
index 7de1b1ac1..7de1b1ac1 100644
--- a/arch/alpha/alpha_linux_process.hh
+++ b/arch/alpha/linux_process.hh
diff --git a/arch/alpha/stacktrace.cc b/arch/alpha/stacktrace.cc
index 30ed07d9d..89b6b73a9 100644
--- a/arch/alpha/stacktrace.cc
+++ b/arch/alpha/stacktrace.cc
@@ -124,7 +124,7 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
{
xc = _xc;
- bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
+ bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
Addr pc = xc->regs.npc;
bool kernel = xc->system->kernelStart <= pc && pc <= xc->system->kernelEnd;
@@ -196,22 +196,22 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
bool
StackTrace::isEntry(Addr addr)
{
- if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp12])
+ if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12))
return true;
- if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp7])
+ if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7))
return true;
- if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp11])
+ if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11))
return true;
- if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp21])
+ if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21))
return true;
- if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp9])
+ if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9))
return true;
- if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp2])
+ if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2))
return true;
return false;
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/tlb.cc
index d00186d95..0f2cedc83 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/tlb.cc
@@ -30,7 +30,7 @@
#include <string>
#include <vector>
-#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/tlb.hh"
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
@@ -293,12 +293,11 @@ AlphaITB::regStats()
void
AlphaITB::fault(Addr pc, ExecContext *xc) const
{
- uint64_t *ipr = xc->regs.ipr;
-
if (!xc->misspeculating()) {
- ipr[AlphaISA::IPR_ITB_TAG] = pc;
- ipr[AlphaISA::IPR_IFAULT_VA_FORM] =
- ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3);
+ xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
+ xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
+ xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
+ (AlphaISA::VAddr(pc).vpn() << 3));
}
}
@@ -306,7 +305,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const
Fault
AlphaITB::translate(MemReqPtr &req) const
{
- InternalProcReg *ipr = req->xc->regs.ipr;
+ ExecContext *xc = req->xc;
if (AlphaISA::PcPAL(req->vaddr)) {
// strip off PAL PC marker (lsb is 1)
@@ -322,24 +321,24 @@ AlphaITB::translate(MemReqPtr &req) const
if (!validVirtualAddress(req->vaddr)) {
fault(req->vaddr, req->xc);
acv++;
- return ItbAcvFault;
+ return new ItbAcvFault;
}
// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
#if ALPHA_TLASER
- if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+ if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->vaddr) == 2) {
#else
if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
#endif
// only valid in kernel mode
- if (ICM_CM(ipr[AlphaISA::IPR_ICM]) !=
+ if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
AlphaISA::mode_kernel) {
fault(req->vaddr, req->xc);
acv++;
- return ItbAcvFault;
+ return new ItbAcvFault;
}
req->paddr = req->vaddr & PAddrImplMask;
@@ -354,24 +353,26 @@ AlphaITB::translate(MemReqPtr &req) const
} else {
// not a physical address: need to look up pte
+ int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
- DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+ asn);
if (!pte) {
fault(req->vaddr, req->xc);
misses++;
- return ItbPageFault;
+ return new ItbPageFault;
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
(AlphaISA::VAddr(req->vaddr).offset() & ~3);
// check permissions for this access
- if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) {
+ if (!(pte->xre &
+ (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
// instruction access fault
fault(req->vaddr, req->xc);
acv++;
- return ItbAcvFault;
+ return new ItbAcvFault;
}
hits++;
@@ -380,7 +381,7 @@ AlphaITB::translate(MemReqPtr &req) const
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
- return MachineCheckFault;
+ return genMachineCheckFault();
checkCacheability(req);
@@ -469,7 +470,6 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
{
ExecContext *xc = req->xc;
AlphaISA::VAddr vaddr = req->vaddr;
- uint64_t *ipr = xc->regs.ipr;
// Set fault address and flags. Even though we're modeling an
// EV5, we use the EV6 technique of not latching fault registers
@@ -479,17 +479,17 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
if (!xc->misspeculating()
&& !(req->flags & VPTE) && !(req->flags & NO_FAULT)) {
// set VA register with faulting address
- ipr[AlphaISA::IPR_VA] = req->vaddr;
+ xc->setMiscReg(AlphaISA::IPR_VA, req->vaddr);
// set MM_STAT register flags
- ipr[AlphaISA::IPR_MM_STAT] =
+ xc->setMiscReg(AlphaISA::IPR_MM_STAT,
(((Opcode(xc->getInst()) & 0x3f) << 11)
| ((Ra(xc->getInst()) & 0x1f) << 6)
- | (flags & 0x3f));
+ | (flags & 0x3f)));
// set VA_FORM register with faulting formatted address
- ipr[AlphaISA::IPR_VA_FORM] =
- ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3);
+ xc->setMiscReg(AlphaISA::IPR_VA_FORM,
+ xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
}
}
@@ -497,11 +497,11 @@ Fault
AlphaDTB::translate(MemReqPtr &req, bool write) const
{
RegFile *regs = &req->xc->regs;
+ ExecContext *xc = req->xc;
Addr pc = regs->pc;
- InternalProcReg *ipr = regs->ipr;
AlphaISA::mode_type mode =
- (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
+ (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
/**
@@ -511,12 +511,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, write ? MM_STAT_WR_MASK : 0);
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
req->size);
- return AlignmentFault;
+ return genAlignmentFault();
}
if (pc & 0x1) {
mode = (req->flags & ALTMODE) ?
- (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])
+ (AlphaISA::mode_type)ALT_MODE_AM(
+ xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
: AlphaISA::mode_kernel;
}
@@ -530,24 +531,24 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
MM_STAT_ACV_MASK);
if (write) { write_acv++; } else { read_acv++; }
- return DtbPageFault;
+ return new DtbPageFault;
}
// Check for "superpage" mapping
#if ALPHA_TLASER
- if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+ if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->vaddr) == 2) {
#else
if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
#endif
// only valid in kernel mode
- if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
+ if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
AlphaISA::mode_kernel) {
fault(req, ((write ? MM_STAT_WR_MASK : 0) |
MM_STAT_ACV_MASK));
if (write) { write_acv++; } else { read_acv++; }
- return DtbAcvFault;
+ return new DtbAcvFault;
}
req->paddr = req->vaddr & PAddrImplMask;
@@ -566,16 +567,20 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
else
read_accesses++;
+ int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
+
// not a physical address: need to look up pte
AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
- DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+ asn);
if (!pte) {
// page fault
fault(req, (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK);
if (write) { write_misses++; } else { read_misses++; }
- return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault;
+ return (req->flags & VPTE) ?
+ (Fault)(new PDtbMissFault) :
+ (Fault)(new NDtbMissFault);
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -588,25 +593,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
MM_STAT_ACV_MASK |
(pte->fonw ? MM_STAT_FONW_MASK : 0));
write_acv++;
- return DtbPageFault;
+ return new DtbPageFault;
}
if (pte->fonw) {
fault(req, MM_STAT_WR_MASK |
MM_STAT_FONW_MASK);
write_acv++;
- return DtbPageFault;
+ return new DtbPageFault;
}
} else {
if (!(pte->xre & MODE2MASK(mode))) {
fault(req, MM_STAT_ACV_MASK |
(pte->fonr ? MM_STAT_FONR_MASK : 0));
read_acv++;
- return DtbAcvFault;
+ return new DtbAcvFault;
}
if (pte->fonr) {
fault(req, MM_STAT_FONR_MASK);
read_acv++;
- return DtbPageFault;
+ return new DtbPageFault;
}
}
}
@@ -619,7 +624,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
- return MachineCheckFault;
+ return genMachineCheckFault();
checkCacheability(req);
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/tlb.hh
index de955fa46..de955fa46 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/tlb.hh
diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/tru64_process.cc
index 8121d3452..90e8b1139 100644
--- a/arch/alpha/alpha_tru64_process.cc
+++ b/arch/alpha/tru64_process.cc
@@ -27,8 +27,8 @@
*/
#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/alpha_common_syscall_emul.hh"
-#include "arch/alpha/alpha_tru64_process.hh"
+#include "arch/alpha/common_syscall_emul.hh"
+#include "arch/alpha/tru64_process.hh"
#include "cpu/exec_context.hh"
#include "kern/tru64/tru64.hh"
#include "mem/functional/functional.hh"
diff --git a/arch/alpha/alpha_tru64_process.hh b/arch/alpha/tru64_process.hh
index 051760702..051760702 100644
--- a/arch/alpha/alpha_tru64_process.hh
+++ b/arch/alpha/tru64_process.hh
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index 3ffa4bd14..1d70196c5 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -82,7 +82,7 @@ Addr
vtophys(ExecContext *xc, Addr addr)
{
AlphaISA::VAddr vaddr = addr;
- Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
+ Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code
//so I put it back in. Perhaps something to do with gdb debugging?
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-19 15:08:50 +0000