2 files changed, 17 insertions, 0 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index e313c1a1c..47ada6de6 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -152,6 +152,18 @@ ExecContext::hwrei()
     return NoFault;
 }
 
+int
+AlphaISA::MiscRegFile::getInstAsid()
+{
+    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
+}
+
+int
+AlphaISA::MiscRegFile::getDataAsid()
+{
+    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+}
+
 void
 AlphaISA::MiscRegFile::clearIprs()
 {
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 742539e89..be6d5111d 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -166,6 +166,11 @@ extern const int reg_redir[NumIntRegs];
       public:
         MiscReg readReg(int misc_reg);
 
+        //These functions should be removed once the simplescalar cpu model
+        //has been replaced.
+        int getInstAsid();
+        int getDataAsid();
+
         MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
 
         Fault setReg(int misc_reg, const MiscReg &val);