4 files changed, 64 insertions, 12 deletions

diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc
index 019390aeb..a782ea330 100644
--- a/arch/alpha/arguments.cc
+++ b/arch/alpha/arguments.cc
@@ -54,7 +54,7 @@ AlphaArguments::getArg(bool fp)
 {
     if (number < 6) {
         if (fp)
-            return xc->readFloatRegInt(16 + number);
+            return xc->readFloatRegBits(16 + number);
         else
             return xc->readIntReg(16 + number);
     } else {
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 019e83dd4..fed2f5358 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -134,7 +134,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
     // (no longer very clean due to the change in setIntReg() in the
     // cpu model.  Consider changing later.)
     cpu->cpuXC->setIntReg(ZeroReg, 0);
-    cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0);
+    cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
 }
 
 Fault
diff --git a/arch/alpha/registerfile.hh b/arch/alpha/registerfile.hh
index c2fb56ec1..13288e087 100644
--- a/arch/alpha/registerfile.hh
+++ b/arch/alpha/registerfile.hh
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_ALPHA_REGISTERFILE_HH__
-#define __ARCH_ALPHA_REGISTERFILE_HH__
+#ifndef __ARCH_ALPHA_REGFILE_HH__
+#define __ARCH_ALPHA_REGFILE_HH__
 
 #include "arch/alpha/types.hh"
 #include "arch/alpha/constants.hh"
@@ -40,10 +40,64 @@ namespace AlphaISA
 
     typedef IntReg IntRegFile[NumIntRegs];
 
-    typedef union {
-        uint64_t q[NumFloatRegs];	// integer qword view
-        double d[NumFloatRegs];		// double-precision floating point view
-    } FloatRegFile;
+    class FloatRegFile
+    {
+      protected:
+
+        union {
+            uint64_t q[NumFloatRegs];	// integer qword view
+            double d[NumFloatRegs];	// double-precision floating point view
+        };
+
+      public:
+
+        FloatReg readReg(int floatReg)
+        {
+            return d[floatReg];
+        }
+
+        FloatReg readReg(int floatReg, int width)
+        {
+            return readReg(floatReg);
+        }
+
+        FloatRegBits readRegBits(int floatReg)
+        {
+            return q[floatReg];
+        }
+
+        FloatRegBits readRegBits(int floatReg, int width)
+        {
+            return readRegBits(floatReg);
+        }
+
+        Fault setReg(int floatReg, const FloatReg &val)
+        {
+            d[floatReg] = val;
+            return NoFault;
+        }
+
+        Fault setReg(int floatReg, const FloatReg &val, int width)
+        {
+            return setReg(floatReg, val);
+        }
+
+        Fault setRegBits(int floatReg, const FloatRegBits &val)
+        {
+            q[floatReg] = val;
+            return NoFault;
+        }
+
+        Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
+        {
+            return setRegBits(floatReg, val);
+        }
+
+        void serialize(std::ostream &os);
+
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+    };
 
     class MiscRegFile {
       protected:
diff --git a/arch/alpha/types.hh b/arch/alpha/types.hh
index 7af3bebd8..3cd93c6b0 100644
--- a/arch/alpha/types.hh
+++ b/arch/alpha/types.hh
@@ -54,10 +54,8 @@ namespace AlphaISA
     typedef uint64_t IntReg;
 
     // floating point register file entry type
-    typedef union {
-        uint64_t q;
-        double d;
-    } FloatReg;
+    typedef double FloatReg;
+    typedef uint64_t FloatRegBits;
 
     // control register file contents
     typedef uint64_t MiscReg;