diff options
Diffstat (limited to 'arch/alpha')
-rw-r--r-- | arch/alpha/alpha_memory.cc | 119 | ||||
-rw-r--r-- | arch/alpha/alpha_memory.hh | 7 | ||||
-rw-r--r-- | arch/alpha/ev5.cc | 4 | ||||
-rw-r--r-- | arch/alpha/ev5.hh | 167 | ||||
-rw-r--r-- | arch/alpha/isa_desc | 10 | ||||
-rw-r--r-- | arch/alpha/isa_traits.hh | 15 | ||||
-rw-r--r-- | arch/alpha/vtophys.cc | 2 |
7 files changed, 153 insertions, 171 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index b9187a92e..81a1902a0 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -31,7 +31,6 @@ #include <vector> #include "arch/alpha/alpha_memory.hh" -#include "arch/alpha/ev5.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" @@ -39,6 +38,7 @@ #include "sim/builder.hh" using namespace std; +using namespace EV5; /////////////////////////////////////////////////////////////////////// // @@ -49,6 +49,8 @@ bool uncacheBit39 = false; bool uncacheBit40 = false; #endif +#define MODE2MASK(X) (1 << (X)) + AlphaTLB::AlphaTLB(const string &name, int s) : SimObject(name), size(s), nlu(0) { @@ -103,12 +105,12 @@ AlphaTLB::checkCacheability(MemReqPtr &req) #ifdef ALPHA_TLASER - if (req->paddr & PA_UNCACHED_BIT_39) { + if (req->paddr & PAddrUncachedBit39) { #else - if (req->paddr & PA_UNCACHED_BIT_43) { + if (req->paddr & PAddrUncachedBit43) { #endif // IPR memory space not implemented - if (PA_IPR_SPACE(req->paddr)) { + if (PAddrIprSpace(req->paddr)) { if (!req->xc->misspeculating()) { switch (req->paddr) { case ULL(0xFFFFF00188): @@ -126,7 +128,7 @@ AlphaTLB::checkCacheability(MemReqPtr &req) #ifndef ALPHA_TLASER // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) - req->paddr &= PA_UNCACHED_MASK; + req->paddr &= PAddrUncachedMask; #endif } } @@ -135,8 +137,9 @@ AlphaTLB::checkCacheability(MemReqPtr &req) // insert a new TLB entry void -AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte) +AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte) { + AlphaISA::VAddr vaddr = addr; if (table[nlu].valid) { Addr oldvpn = table[nlu].tag; PageTable::iterator i = lookupTable.find(oldvpn); @@ -157,14 +160,13 @@ AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte) lookupTable.erase(i); } - Addr vpn = VA_VPN(vaddr); - DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vpn, pte.ppn); + DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); table[nlu] = pte; - table[nlu].tag = vpn; + table[nlu].tag = vaddr.vpn(); table[nlu].valid = true; - lookupTable.insert(make_pair(vpn, nlu)); + lookupTable.insert(make_pair(vaddr.vpn(), nlu)); nextnlu(); } @@ -197,21 +199,22 @@ AlphaTLB::flushProcesses() } void -AlphaTLB::flushAddr(Addr vaddr, uint8_t asn) +AlphaTLB::flushAddr(Addr addr, uint8_t asn) { - Addr vpn = VA_VPN(vaddr); + AlphaISA::VAddr vaddr = addr; - PageTable::iterator i = lookupTable.find(vpn); + PageTable::iterator i = lookupTable.find(vaddr.vpn()); if (i == lookupTable.end()) return; - while (i->first == vpn) { + while (i->first == vaddr.vpn()) { int index = i->second; AlphaISA::PTE *pte = &table[index]; assert(pte->valid); - if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { - DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vpn, pte->ppn); + if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { + DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), + pte->ppn); // invalidate this entry pte->valid = false; @@ -287,7 +290,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const if (!xc->misspeculating()) { ipr[AlphaISA::IPR_ITB_TAG] = pc; ipr[AlphaISA::IPR_IFAULT_VA_FORM] = - ipr[AlphaISA::IPR_IVPTBR] | (VA_VPN(pc) << 3); + ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3); } } @@ -297,9 +300,9 @@ AlphaITB::translate(MemReqPtr &req) const { InternalProcReg *ipr = req->xc->regs.ipr; - if (PC_PAL(req->vaddr)) { + if (AlphaISA::PcPAL(req->vaddr)) { // strip off PAL PC marker (lsb is 1) - req->paddr = (req->vaddr & ~3) & PA_IMPL_MASK; + req->paddr = (req->vaddr & ~3) & PAddrImplMask; hits++; return No_Fault; } @@ -319,24 +322,23 @@ AlphaITB::translate(MemReqPtr &req) const // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #ifdef ALPHA_TLASER if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && - VA_SPACE_EV5(req->vaddr) == 2) { + VAddrSpaceEV5(req->vaddr) == 2) { #else - if (VA_SPACE_EV6(req->vaddr) == 0x7e) { + if (VAddrSpaceEV6(req->vaddr) == 0x7e) { #endif - - // only valid in kernel mode - if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) { + if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != + AlphaISA::mode_kernel) { fault(req->vaddr, req->xc); acv++; return ITB_Acv_Fault; } - req->paddr = req->vaddr & PA_IMPL_MASK; + req->paddr = req->vaddr & PAddrImplMask; #ifndef ALPHA_TLASER // sign extend the physical address properly - if (req->paddr & PA_UNCACHED_BIT_40) + if (req->paddr & PAddrUncachedBit40) req->paddr |= ULL(0xf0000000000); else req->paddr &= ULL(0xffffffffff); @@ -344,8 +346,8 @@ AlphaITB::translate(MemReqPtr &req) const } else { // not a physical address: need to look up pte - AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr), - DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), + DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); if (!pte) { fault(req->vaddr, req->xc); @@ -353,7 +355,8 @@ AlphaITB::translate(MemReqPtr &req) const return ITB_Fault_Fault; } - req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3); + req->paddr = (pte->ppn << AlphaISA::PageShift) + + (AlphaISA::VAddr(req->vaddr).offset() & ~3); // check permissions for this access if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) { @@ -368,7 +371,7 @@ AlphaITB::translate(MemReqPtr &req) const } // check that the physical address is ok (catch bad physical addresses) - if (req->paddr & ~PA_IMPL_MASK) + if (req->paddr & ~PAddrImplMask) return Machine_Check_Fault; checkCacheability(req); @@ -457,7 +460,7 @@ void AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const { ExecContext *xc = req->xc; - Addr vaddr = req->vaddr; + AlphaISA::VAddr vaddr = req->vaddr; uint64_t *ipr = xc->regs.ipr; // Set fault address and flags. Even though we're modeling an @@ -468,16 +471,17 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const if (!xc->misspeculating() && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) { // set VA register with faulting address - ipr[AlphaISA::IPR_VA] = vaddr; + ipr[AlphaISA::IPR_VA] = req->vaddr; // set MM_STAT register flags - ipr[AlphaISA::IPR_MM_STAT] = (((OPCODE(xc->getInst()) & 0x3f) << 11) - | ((RA(xc->getInst()) & 0x1f) << 6) - | (flags & 0x3f)); + ipr[AlphaISA::IPR_MM_STAT] = + (((Opcode(xc->getInst()) & 0x3f) << 11) + | ((Ra(xc->getInst()) & 0x1f) << 6) + | (flags & 0x3f)); // set VA_FORM register with faulting formatted address ipr[AlphaISA::IPR_VA_FORM] = - ipr[AlphaISA::IPR_MVPTBR] | (VA_VPN(vaddr) << 3); + ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3); } } @@ -500,7 +504,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const return Alignment_Fault; } - if (PC_PAL(pc)) { + if (pc & 0x1) { mode = (req->flags & ALTMODE) ? (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE]) : AlphaISA::mode_kernel; @@ -511,8 +515,9 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const } else { // verify that this is a good virtual address if (!validVirtualAddress(req->vaddr)) { - fault(req, (write ? MM_STAT_WR_MASK : 0) | MM_STAT_BAD_VA_MASK | - MM_STAT_ACV_MASK); + fault(req, (write ? MM_STAT_WR_MASK : 0) | + MM_STAT_BAD_VA_MASK | + MM_STAT_ACV_MASK); if (write) { write_acv++; } else { read_acv++; } return DTB_Fault_Fault; @@ -521,24 +526,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const // Check for "superpage" mapping #ifdef ALPHA_TLASER if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && - VA_SPACE_EV5(req->vaddr) == 2) { + VAddrSpaceEV5(req->vaddr) == 2) { #else - if (VA_SPACE_EV6(req->vaddr) == 0x7e) { + if (VAddrSpaceEV6(req->vaddr) == 0x7e) { #endif // only valid in kernel mode if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != AlphaISA::mode_kernel) { - fault(req, ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK)); + fault(req, ((write ? MM_STAT_WR_MASK : 0) | + MM_STAT_ACV_MASK)); if (write) { write_acv++; } else { read_acv++; } return DTB_Acv_Fault; } - req->paddr = req->vaddr & PA_IMPL_MASK; + req->paddr = req->vaddr & PAddrImplMask; #ifndef ALPHA_TLASER // sign extend the physical address properly - if (req->paddr & PA_UNCACHED_BIT_40) + if (req->paddr & PAddrUncachedBit40) req->paddr |= ULL(0xf0000000000); else req->paddr &= ULL(0xffffffffff); @@ -551,36 +557,39 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const read_accesses++; // not a physical address: need to look up pte - AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr), - DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), + DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); if (!pte) { // page fault - fault(req, - (write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK); + fault(req, (write ? MM_STAT_WR_MASK : 0) | + MM_STAT_DTB_MISS_MASK); if (write) { write_misses++; } else { read_misses++; } return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault; } - req->paddr = PA_PFN2PA(pte->ppn) | VA_POFS(req->vaddr); + req->paddr = (pte->ppn << AlphaISA::PageShift) + + AlphaISA::VAddr(req->vaddr).offset(); if (write) { if (!(pte->xwe & MODE2MASK(mode))) { // declare the instruction access fault - fault(req, (MM_STAT_WR_MASK | MM_STAT_ACV_MASK | - (pte->fonw ? MM_STAT_FONW_MASK : 0))); + fault(req, MM_STAT_WR_MASK | + MM_STAT_ACV_MASK | + (pte->fonw ? MM_STAT_FONW_MASK : 0)); write_acv++; return DTB_Fault_Fault; } if (pte->fonw) { - fault(req, MM_STAT_WR_MASK | MM_STAT_FONW_MASK); + fault(req, MM_STAT_WR_MASK | + MM_STAT_FONW_MASK); write_acv++; return DTB_Fault_Fault; } } else { if (!(pte->xre & MODE2MASK(mode))) { - fault(req, (MM_STAT_ACV_MASK | - (pte->fonr ? MM_STAT_FONR_MASK : 0))); + fault(req, MM_STAT_ACV_MASK | + (pte->fonr ? MM_STAT_FONR_MASK : 0)); read_acv++; return DTB_Acv_Fault; } @@ -599,7 +608,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const } // check that the physical address is ok (catch bad physical addresses) - if (req->paddr & ~PA_IMPL_MASK) + if (req->paddr & ~PAddrImplMask) return Machine_Check_Fault; checkCacheability(req); diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh index 42bc03ddd..0d4b8d1f2 100644 --- a/arch/alpha/alpha_memory.hh +++ b/arch/alpha/alpha_memory.hh @@ -31,9 +31,10 @@ #include <map> +#include "arch/alpha/isa_traits.hh" +#include "base/statistics.hh" #include "mem/mem_req.hh" #include "sim/sim_object.hh" -#include "base/statistics.hh" class ExecContext; @@ -66,8 +67,8 @@ class AlphaTLB : public SimObject // static helper functions... really EV5 VM traits static bool validVirtualAddress(Addr vaddr) { // unimplemented bits must be all 0 or all 1 - Addr unimplBits = vaddr & VA_UNIMPL_MASK; - return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK); + Addr unimplBits = vaddr & EV5::VAddrUnImplMask; + return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); } static void checkCacheability(MemReqPtr &req); diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 6deccefdb..2e32da531 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -15,6 +15,8 @@ #ifdef FULL_SYSTEM +using namespace EV5; + //////////////////////////////////////////////////////////////////////// // // @@ -92,7 +94,7 @@ AlphaISA::initIPRs(RegFile *regs) uint64_t *ipr = regs->ipr; bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); - ipr[IPR_PAL_BASE] = PAL_BASE; + ipr[IPR_PAL_BASE] = PalBase; ipr[IPR_MCSR] = 0x6; } diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh index 4956d65d9..317f3d19d 100644 --- a/arch/alpha/ev5.hh +++ b/arch/alpha/ev5.hh @@ -1,112 +1,79 @@ /* $Id$ */ -#ifndef __EV5_H__ -#define __EV5_H__ +#ifndef __ARCH_ALPHA_EV5_HH__ +#define __ARCH_ALPHA_EV5_HH__ -#define MODE2MASK(X) (1 << (X)) - -// Alpha IPR register accessors -#define PC_PAL(X) ((X) & 0x1) -#define MCSR_SP(X) (((X) >> 1) & 0x3) - -#define ICSR_SDE(X) (((X) >> 30) & 0x1) -#define ICSR_SPE(X) (((X) >> 28) & 0x3) -#define ICSR_FPE(X) (((X) >> 26) & 0x1) - -#define ALT_MODE_AM(X) (((X) >> 3) & 0x3) - -#define DTB_CM_CM(X) (((X) >> 3) & 0x3) +namespace EV5 { #ifdef ALPHA_TLASER -#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f) -#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff) +const uint64_t AsnMask = ULL(0x7f); #else -#define DTB_ASN_ASN(X) (((X) >> 57) & 0xff) -#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff) +const uint64_t AsnMask = ULL(0xff); #endif -#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf) -#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf) -#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1) -#define DTB_PTE_FONW(X) (((X) >> 2) & 0x1) -#define DTB_PTE_GH(X) (((X) >> 5) & 0x3) -#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1) - -#define ICM_CM(X) (((X) >> 3) & 0x3) +const int VAddrImplBits = 43; +const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; +const Addr VAddrUnImplMask = ~VAddrImplMask; +inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } +inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } +inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } +inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } +inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } #ifdef ALPHA_TLASER -#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f) -#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff) +inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } +const int PAddrImplBits = 40; #else -#define ITB_ASN_ASN(X) (((X) >> 4) & 0xff) -#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff) +inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } +const int PAddrImplBits = 44; // for Tsunami #endif - -#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf) -#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1) -#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1) -#define ITB_PTE_GH(X) (((X) >> 5) & 0x3) -#define ITB_PTE_ASMA(X) (((X) >> 4) & 0x1) - -#define VA_UNIMPL_MASK ULL(0xfffff80000000000) -#define VA_IMPL_MASK ULL(0x000007ffffffffff) -#define VA_IMPL(X) ((X) & VA_IMPL_MASK) -#define VA_VPN(X) (VA_IMPL(X) >> 13) -#define VA_SPACE_EV5(X) (((X) >> 41) & 0x3) -#define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f) -#define VA_POFS(X) ((X) & 0x1fff) - -#define PA_UNCACHED_BIT_39 ULL(0x8000000000) -#define PA_UNCACHED_BIT_40 ULL(0x10000000000) -#define PA_UNCACHED_BIT_43 ULL(0x80000000000) -#define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35> -#ifdef ALPHA_TLASER -#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000)) -#define PA_IMPL_MASK ULL(0xffffffffff) -#else -#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000)) -#define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami -#endif - -#define PA_PFN2PA(X) ((X) << 13) - - -#define MM_STAT_BAD_VA_MASK 0x0020 -#define MM_STAT_DTB_MISS_MASK 0x0010 -#define MM_STAT_FONW_MASK 0x0008 -#define MM_STAT_FONR_MASK 0x0004 -#define MM_STAT_ACV_MASK 0x0002 -#define MM_STAT_WR_MASK 0x0001 - -#define OPCODE(X) (X >> 26) & 0x3f -#define RA(X) (X >> 21) & 0x1f - -//////////////////////////////////////////////////////////////////////// -// -// -// - -// VPTE size for HW_LD/HW_ST -#define HW_VPTE ((inst >> 11) & 0x1) - -// QWORD size for HW_LD/HW_ST -#define HW_QWORD ((inst >> 12) & 0x1) - -// ALT mode for HW_LD/HW_ST -#define HW_ALT (((inst >> 14) & 0x1) ? ALTMODE : 0) - -// LOCK/COND mode for HW_LD/HW_ST -#define HW_LOCK (((inst >> 10) & 0x1) ? LOCKED : 0) -#define HW_COND (((inst >> 10) & 0x1) ? LOCKED : 0) - -// PHY size for HW_LD/HW_ST -#define HW_PHY (((inst >> 15) & 0x1) ? PHYSICAL : 0) - -// OFFSET for HW_LD/HW_ST -#define HW_OFS (inst & 0x3ff) - - -#define PAL_BASE 0x4000 -#define PAL_MAX 0x10000 - -#endif //__EV5_H__ +const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; +const Addr PAddrUncachedBit39 = ULL(0x8000000000); +const Addr PAddrUncachedBit40 = ULL(0x10000000000); +const Addr PAddrUncachedBit43 = ULL(0x80000000000); +const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> + +inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } +inline Addr DTB_PTE_PPN(uint64_t reg) +{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } +inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } +inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } +inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } +inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } +inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } +inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } + +inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } +inline Addr ITB_PTE_PPN(uint64_t reg) +{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } +inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } +inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } +inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } +inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } +inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } + +inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } + +inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } +inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } +inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } + +inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } +inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } +inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } + +const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); +const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); +const uint64_t MM_STAT_FONW_MASK = ULL(0x0008); +const uint64_t MM_STAT_FONR_MASK = ULL(0x0004); +const uint64_t MM_STAT_ACV_MASK = ULL(0x0002); +const uint64_t MM_STAT_WR_MASK = ULL(0x0001); +inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } +inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } + +const Addr PalBase = 0x4000; +const Addr PalMax = 0x10000; + +/* namespace EV5 */ } + +#endif // __ARCH_ALPHA_EV5_HH__ diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 9d65a02f0..5154d78d1 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -38,14 +38,12 @@ output exec {{ #include <fenv.h> #endif -#include "cpu/base_cpu.hh" -#include "cpu/exetrace.hh" -#include "sim/sim_exit.hh" - #ifdef FULL_SYSTEM -#include "arch/alpha/ev5.hh" #include "arch/alpha/pseudo_inst.hh" #endif +#include "cpu/base_cpu.hh" +#include "cpu/exetrace.hh" +#include "sim/sim_exit.hh" }}; //////////////////////////////////////////////////////////////////// @@ -515,7 +513,7 @@ output exec {{ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) { Fault fault = No_Fault; // dummy... this ipr access should not fault - if (!ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) { + if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) { fault = Fen_Fault; } return fault; diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index b22b2fa29..ff3da1502 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __ISA_TRAITS_HH__ -#define __ISA_TRAITS_HH__ +#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ +#define __ARCH_ALPHA_ISA_TRAITS_HH__ #include "arch/alpha/faults.hh" #include "base/misc.hh" @@ -42,6 +42,11 @@ class Checkpoint; template <class ISA> class StaticInst; template <class ISA> class StaticInstPtr; +namespace EV5 { +int DTB_ASN_ASN(uint64_t reg); +int ITB_ASN_ASN(uint64_t reg); +} + class AlphaISA { public: @@ -160,6 +165,8 @@ static const Addr PageOffset = PageBytes - 1; InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs int intrflag; // interrupt flag bool pal_shadow; // using pal_shadow registers + inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } + inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } #endif // FULL_SYSTEM void serialize(std::ostream &os); @@ -281,9 +288,7 @@ typedef TheISA::InternalProcReg InternalProcReg; const int NumInternalProcRegs = TheISA::NumInternalProcRegs; const int NumInterruptLevels = TheISA::NumInterruptLevels; -// more stuff that should be imported here, but I'm too tired to do it -// right now... #include "arch/alpha/ev5.hh" #endif -#endif // __ALPHA_ISA_H__ +#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc index a8af8f238..e26721aab 100644 --- a/arch/alpha/vtophys.cc +++ b/arch/alpha/vtophys.cc @@ -85,7 +85,7 @@ vtophys(ExecContext *xc, Addr addr) Addr paddr = 0; //@todo Andrew couldn't remember why he commented some of this code //so I put it back in. Perhaps something to do with gdb debugging? - if (PC_PAL(vaddr) && (vaddr < PAL_MAX)) { + if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) { paddr = vaddr & ~ULL(1); } else { if (AlphaISA::IsK0Seg(vaddr)) { |