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-rw-r--r--arch/alpha/ev5.cc8
-rw-r--r--arch/alpha/isa_desc17
2 files changed, 17 insertions, 8 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index ff1ecc4bf..826a1ab02 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -168,11 +168,11 @@ ExecContext::hwrei()
if (!PC_PAL(regs.pc))
return Unimplemented_Opcode_Fault;
- kernelStats.hwrei();
-
- regs.npc = ipr[AlphaISA::IPR_EXC_ADDR];
+ setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
if (!misspeculating()) {
+ kernelStats.hwrei();
+
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
AlphaISA::swap_palshadow(&regs, false);
@@ -560,7 +560,7 @@ ExecContext::simPalCheck(int palFunc)
case PAL::bpt:
case PAL::bugchk:
- if (system->breakpoint())
+ if (!misspeculating() && system->breakpoint())
return false;
break;
}
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index ac6934fac..75f765029 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2322,11 +2322,15 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate {
0xe000: rc({{
Ra = xc->regs.intrflag;
- xc->regs.intrflag = 0;
+ if (!xc->misspeculating()) {
+ xc->regs.intrflag = 0;
+ }
}}, No_OpClass);
0xf000: rs({{
Ra = xc->regs.intrflag;
- xc->regs.intrflag = 1;
+ if (!xc->misspeculating()) {
+ xc->regs.intrflag = 1;
+ }
}}, No_OpClass);
}
#else
@@ -2343,7 +2347,9 @@ decode OPCODE default Unknown::unknown() {
// on this PAL call (including maybe suppress it)
bool dopal = xc->simPalCheck(palFunc);
- Annotate::Callpal(xc, palFunc);
+ if (!xc->misspeculating()) {
+ Annotate::Callpal(xc, palFunc);
+ }
if (dopal) {
if (!xc->misspeculating()) {
@@ -2360,7 +2366,10 @@ decode OPCODE default Unknown::unknown() {
if (!xc->misspeculating())
SimExit("halt instruction encountered");
}});
- 0x83: callsys({{ xc->syscall(); }});
+ 0x83: callsys({{
+ if (!xc->misspeculating())
+ xc->syscall();
+ }});
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }});
// Write uniq reg with value from ABI arg register (r16)