diff options
Diffstat (limited to 'arch/alpha')
| -rw-r--r-- | arch/alpha/isa_desc | 8 | ||||
| -rw-r--r-- | arch/alpha/isa_traits.hh | 7 |
2 files changed, 8 insertions, 7 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index e9b93a895..b5536525d 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1808,11 +1808,19 @@ decode OPCODE default Unknown::unknown() { 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }}, {{ uint64_t tmp = Mem_write_result; + // see stq_c Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; }}, LOCKED); 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }}, {{ uint64_t tmp = Mem_write_result; + // If the write operation returns 0 or 1, then + // this was a conventional store conditional, + // and the value indicates the success/failure + // of the operation. If another value is + // returned, then this was a Turbolaser + // mailbox access, and we don't update the + // result register at all. Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; }}, LOCKED); } diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 6b78722ad..5e2dac9f3 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -168,13 +168,6 @@ class AlphaISA ITOUCH_ANNOTE = 0xffffffff, }; -#if 0 - static inline Addr - extractInstructionPrefetchTarget(const MachInst &IR, Addr PC) { - return(0); - } -#endif - static inline bool isCallerSaveIntegerRegister(unsigned int reg) { panic("register classification not implemented"); return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); |