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-rw-r--r--arch/mips/isa/decoder.isa323
1 files changed, 168 insertions, 155 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index f16da7f87..3f054f6a5 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -20,8 +20,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
0x1: decode MOVCI {
format BasicOp {
- 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
- 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
+ 0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}});
+ 1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}});
}
}
@@ -30,7 +30,17 @@ decode OPCODE_HI default Unknown::unknown() {
//Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
//are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
- 0x0: sll({{ Rd = Rt.uw << SA; }});
+ 0x0: decode RS {
+ 0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) {
+ 0x0: decode RD{
+ 0x0: decode HINT {
+ 0x0:nop({{}}); //really sll r0,r0,0
+ 0x1:ssnop({{}});//really sll r0,r0,1
+ 0x3:ehb({{}}); //really sll r0,r0,3
+ }
+ }
+ }
+ }
0x2: decode SRL {
0: srl({{ Rd = Rt.uw >> SA; }});
@@ -60,9 +70,9 @@ decode OPCODE_HI default Unknown::unknown() {
//to distinguish JR from JR.HB and JALR from JALR.HB"
format Jump {
0x0: decode HINT {
- 0:jr({{ NNPC = Rs; }},IsReturn);
+ 0:jr({{ NNPC = Rs & ~1; }},IsReturn);
- 1:jr_hb({{ NNPC = Rs; clear_exe_inst_hazards(); }},IsReturn);
+ 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn);
}
0x1: decode HINT {
@@ -86,10 +96,10 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode FUNCTION_LO {
format BasicOp {
- 0x0: mfhi({{ Rd = xc->miscRegs.hi; }});
- 0x1: mthi({{ xc->miscRegs.hi = Rs; }});
- 0x2: mflo({{ Rd = xc->miscRegs.lo; }});
- 0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
+ 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }});
+ 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }});
+ 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }});
+ 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }});
}
}
@@ -97,39 +107,38 @@ decode OPCODE_HI default Unknown::unknown() {
format IntOp {
0x0: mult({{
int64_t temp1 = Rs.sw * Rt.sw;
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>;
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x1: multu({{
int64_t temp1 = Rs.uw * Rt.uw;
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
- Rd.sw = Rs.uw * Rt.uw;
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x2: div({{
- xc->miscRegs.hi = Rs.sw % Rt.sw;
- xc->miscRegs.lo = Rs.sw / Rt.sw;
+ xc->setMiscReg(Hi,Rs.sw % Rt.sw);
+ xc->setMiscReg(Lo,Rs.sw / Rt.sw);
}});
0x3: divu({{
- xc->miscRegs.hi = Rs.uw % Rt.uw;
- xc->miscRegs.lo = Rs.uw / Rt.uw;
+ xc->setMiscReg(Hi,Rs.uw % Rt.uw);
+ xc->setMiscReg(Lo,Rs.uw / Rt.uw);
}});
}
}
0x4: decode FUNCTION_LO {
format IntOp {
- 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}});
- 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
- 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
- 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
- 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
- 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
- 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
- 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
+ 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
+ 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
+ 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
+ 0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}});
+ 0x4: and({{ Rd = Rs & Rt;}});
+ 0x5: or({{ Rd = Rs | Rt;}});
+ 0x6: xor({{ Rd = Rs ^ Rt;}});
+ 0x7: nor({{ Rd = ~(Rs | Rt);}});
}
}
@@ -141,8 +150,8 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x6: decode FUNCTION_LO {
- format BasicOp {
- 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
+ format Trap {
+ 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
@@ -167,7 +176,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x1: decode REGIMM_LO {
- format BasicOp {
+ format Trap {
0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
@@ -198,14 +207,14 @@ decode OPCODE_HI default Unknown::unknown() {
}
format Jump {
- 0x2: j({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}});
+ 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
- 0x3: jal({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}},IsCall,IsReturn);
+ 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn);
}
format Branch {
- 0x4: beq({{ cond = (Rs.sw == 0); }});
- 0x5: bne({{ cond = (Rs.sw != 0); }});
+ 0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
+ 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
0x6: blez({{ cond = (Rs.sw <= 0); }});
0x7: bgtz({{ cond = (Rs.sw > 0); }});
}
@@ -213,10 +222,10 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode OPCODE_LO {
format IntOp {
- 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
- 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
- 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
- 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
+ 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
+ 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
+ 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
+ 0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }});
0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
@@ -229,33 +238,17 @@ decode OPCODE_HI default Unknown::unknown() {
//Table A-11 MIPS32 COP0 Encoding of rs Field
0x0: decode RS_MSB {
0x0: decode RS {
- format BasicOp {
+ format System {
0x0: mfc0({{
- //The contents of the coprocessor 0 register specified by the
- //combination of rd and sel are loaded into general register
- //rt. Note that not all coprocessor 0 registers support the
- //sel field. In those instances, the sel field must be zero.
+ //uint64_t reg_num = Rd.uw;
- if (SEL > 0)
- panic("Can't Handle Cop0 with register select yet\n");
-
- uint64_t reg_num = Rd.uw;
-
- Rt = xc->miscRegs.cop0[reg_num];
+ Rt = xc->readMiscReg(RD << 5 | SEL);
}});
0x4: mtc0({{
- //The contents of the coprocessor 0 register specified by the
- //combination of rd and sel are loaded into general register
- //rt. Note that not all coprocessor 0 registers support the
- //sel field. In those instances, the sel field must be zero.
+ //uint64_t reg_num = Rd.uw;
- if (SEL > 0)
- panic("Can't Handle Cop0 with register select yet\n");
-
- uint64_t reg_num = Rd.uw;
-
- xc->miscRegs.cop0[reg_num] = Rt;
+ xc->setMiscReg(RD << 5 | SEL,Rt);
}});
0x8: mftr({{
@@ -279,64 +272,84 @@ decode OPCODE_HI default Unknown::unknown() {
0xA: rdpgpr({{
//Accessing Previous Shadow Set Register Number
- uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
- uint64_t reg_num = Rt.uw;
+ //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/;
+ //uint64_t reg_num = Rt.uw;
- Rd = xc->shadowIntRegFile[prev][reg_num];
+ //Rd = xc->regs.IntRegFile[prev];
+ //Rd = xc->shadowIntRegFile[prev][reg_num];
}});
0xB: decode RD {
0x0: decode SC {
0x0: dvpe({{
- Rt.sw = xc->miscRegs.cop0.MVPControl;
- xc->miscRegs.cop0.MVPControl[EVP] = 0;
+ int idx;
+ int sel;
+ getMiscRegIdx(MVPControl,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel);
}});
0x1: evpe({{
- Rt.sw = xc->miscRegs.cop0.MVPControl;
- xc->miscRegs.cop0.MVPControl[EVP] = 1;
+ int idx;
+ int sel;
+ getMiscRegIdx(MVPControl,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,1);
}});
}
0x1: decode SC {
0x0: dmt({{
- Rt.sw = xc->miscRegs.cop0.VPEControl;
- xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0;
+ int idx;
+ int sel;
+ getMiscRegIdx(VPEControl,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel);
}});
0x1: emt({{
- Rt.sw = xc->miscRegs.cop0.VPEControl;
- xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1;
+ int idx;
+ int sel;
+ getMiscRegIdx(VPEControl,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,1);
}});
}
0xC: decode SC {
0x0: di({{
- Rt.sw = xc->miscRegs.cop0.Status;
- xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0;
+ int idx;
+ int sel;
+ getMiscRegIdx(Status,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel);
}});
0x1: ei({{
- Rt.sw = xc->miscRegs.cop0.Status;
- xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1;
+ int idx;
+ int sel;
+ getMiscRegIdx(Status,idx,sel);
+ Rt.sw = xc->readMiscReg(idx,sel);
+ xc->setMiscReg(idx,sel,1);
}});
}
}
0xE: wrpgpr({{
//Accessing Previous Shadow Set Register Number
- uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
- uint64_t reg_num = Rd.uw;
+ //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/);
+ //uint64_t reg_num = Rd.uw;
- xc->shadowIntRegFile[prev][reg_num] = Rt;
+ //xc->regs.IntRegFile[prev];
+ //xc->shadowIntRegFile[prev][reg_num] = Rt;
}});
}
}
//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
0x1: decode FUNCTION {
- format BasicOp {
+ format System {
0x01: tlbr({{ }});
0x02: tlbwi({{ }});
0x06: tlbwr({{ }});
@@ -357,27 +370,27 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
- 0x0: mfc1({{ Rt = Fs<31:0>; }});
- 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}});
- 0x3: mfhc1({{ Rt = Fs<63:32>;}});
- 0x4: mtc1({{ Fs<31:0> = Rt}});
- 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}});
- 0x7: mftc1({{ Fs<63:32> = Rt}});
+ 0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }});
+ 0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}});
+ 0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}});
+ 0x4: mtc1({{ /*Fs = Rt.uw*/}});
+ 0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}});
+ 0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}});
}
}
0x1: decode ND {
0x0: decode TF {
format Branch {
- 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
- 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
+ 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }});
+ 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }});
}
}
0x1: decode TF {
format BranchLikely {
- 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
- 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
+ 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }});
+ 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }});
}
}
}
@@ -396,7 +409,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
- 0x5: abss({{ Fd.sf = abs(Fs.sf);}});
+ 0x5: abss({{ Fd.sf = fabs(Fs.sf);}});
0x6: movs({{ Fd.sf = Fs.sf;}});
0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
}
@@ -422,8 +435,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }});
- 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}});
+ 0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
+ 0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
}
}
@@ -434,29 +447,29 @@ decode OPCODE_HI default Unknown::unknown() {
format Float64Op {
0x5: recips({{ Fd = 1 / Fs; }});
- 0x6: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
+ 0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}});
}
}
0x4: decode RS_LO {
format FloatOp {
- 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ 0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
}});
- 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
}});
}
//only legal for 64 bit
format Float64Op {
- 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
}});
- 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }});
+ 0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }});
}
}
}
@@ -470,7 +483,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
- 0x5: absd({{ Fd.df = abs(Fs.df);}});
+ 0x5: absd({{ Fd.df = fabs(Fs.df);}});
0x6: movd({{ Fd.df = Fs.df;}});
0x7: negd({{ Fd.df = -1 * Fs.df;}});
}
@@ -496,8 +509,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }});
- 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }});
+ 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }});
+ 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }});
}
}
@@ -515,12 +528,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: decode RS_LO {
format FloatOp {
0x0: cvt_s_d({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
}});
0x4: cvt_w_d({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
}});
}
@@ -528,7 +541,7 @@ decode OPCODE_HI default Unknown::unknown() {
//only legal for 64 bit
format Float64Op {
0x5: cvt_l_d({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
}});
}
@@ -539,12 +552,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: decode FUNCTION {
format FloatOp {
0x20: cvt_s({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
}});
0x21: cvt_d({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
}});
}
@@ -556,12 +569,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: decode FUNCTION_HI {
format FloatOp {
0x10: cvt_s_l({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
}});
0x11: cvt_d_l({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
}});
}
@@ -590,12 +603,12 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
- Fd.df = abs(Fs.df);
+ Fd.df = fabs(Fs.df);
}});
0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
//Lower Halves Independently but we take simulator shortcut
- Fd.df = Fs<31:0> | Ft<31:0>;
+ //Fd.df = Fs<31:0> | Ft<31:0>;
}});
0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
@@ -608,21 +621,21 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode RS_LO {
0x1: decode MOVCF {
format Float64Op {
- 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
- 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
+ 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}});
+ 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
}
}
format BasicOp {
- 0x2: movzps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }});
- 0x3: movnps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }});
+ 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
+ 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }});
}
}
0x4: decode RS_LO {
0x0: Float64Op::cvt_s_pu({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
}});
}
@@ -630,13 +643,13 @@ decode OPCODE_HI default Unknown::unknown() {
0x5: decode RS_LO {
format Float64Op {
0x0: cvt_s_pl({{
- int rnd_mode = xc->miscRegs.fcsr;
+ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
}});
- 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}});
- 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}});
- 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}});
- 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}});
+ 0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}});
+ 0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}});
+ 0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}});
+ 0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}});
}
}
}
@@ -682,23 +695,23 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
format LoadMemory2 {
- 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.sf; }});
- 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }});
+ 0x0: lwxc1({{ EA = Rs + Rt; }},{{ /*F_t<31:0> = Mem.sf; */}});
+ 0x1: ldxc1({{ EA = Rs + Rt; }},{{ /*F_t<63:0> = Mem.df;*/ }});
0x5: luxc1({{ //Need to make EA<2:0> = 0
EA = Rs + Rt;
}},
- {{ Ft<31:0> = Mem.df; }});
+ {{ /*F_t<31:0> = Mem.df; */}});
}
}
0x1: decode FUNCTION_LO {
format StoreMemory2 {
- 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.sf = Ft<31:0>; }});
- 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.df = Ft<63:0>}});
+ 0x0: swxc1({{ EA = Rs + Rt; }},{{ /*Mem.sf = Ft<31:0>; */}});
+ 0x1: sdxc1({{ EA = Rs + Rt; }},{{ /*Mem.df = Ft<63:0> */}});
0x5: suxc1({{ //Need to make EA<2:0> = 0
EA = Rs + Rt;
}},
- {{ Mem.df = Ft<63:0>;}});
+ {{ /*Mem.df = F_t<63:0>;*/}});
}
0x7: WarnUnimpl::prefx();
@@ -768,33 +781,33 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
format IntOp {
0x0: madd({{
- int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 + (Rs.sw * Rt.sw);
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x1: maddu({{
- int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
- 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
+ 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
- int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
0x5: msubu({{
- int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
- xc->miscRegs.hi->temp1<63:32>;
- xc->miscRegs.lo->temp1<31:0>
+ xc->setMiscReg(Hi,temp1<63:32>);
+ xc->setMiscReg(Lo,temp1<31:0>);
}});
}
}
@@ -802,25 +815,25 @@ decode OPCODE_HI default Unknown::unknown() {
0x4: decode FUNCTION_LO {
format BasicOp {
0x0: clz({{
- int cnt = 0;
+ /*int cnt = 0;
int idx = 0;
- while ( Rs.uw<idx>!= 1) {
+ while ( Rs.uw<idx> != 1) {
cnt++;
idx--;
}
- Rd.uw = cnt;
+ Rd.uw = cnt;*/
}});
0x1: clo({{
- int cnt = 0;
+ /*int cnt = 0;
int idx = 0;
- while ( Rs.uw<idx>!= 0) {
+ while ( Rs.uw<idx> != 0) {
cnt++;
idx--;
}
- Rd.uw = cnt;
+ Rd.uw = cnt;*/
}});
}
}
@@ -860,20 +873,20 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x6: decode FUNCTION_LO {
- 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
+ 0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }});
}
}
}
0x4: decode OPCODE_LO default FailUnimpl::reserved() {
format LoadMemory {
- 0x0: lb({{ Rb.sw = Mem.sb; }});
- 0x1: lh({{ Rb.sw = Mem.sh; }});
- 0x2: lwl({{ Rb.sw = Mem.sw; }});//, WordAlign);
- 0x3: lw({{ Rb.uq = Mem.sb; }});
- 0x4: lbu({{ Rb.uw = Mem.ub; }});
- 0x5: lhu({{ Rb.uw = Mem.uh; }});
- 0x6: lwr({{ Rb.uw = Mem.uw; }});//, WordAlign);
+ 0x0: lb({{ Rt.sw = Mem.sb; }});
+ 0x1: lh({{ Rt.sw = Mem.sh; }});
+ 0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign);
+ 0x3: lw({{ Rt.sw = Mem.sb; }});
+ 0x4: lbu({{ Rt.uw = Mem.ub; }});
+ 0x5: lhu({{ Rt.uw = Mem.uh; }});
+ 0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign);
}
0x7: FailUnimpl::reserved();
@@ -898,19 +911,19 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: WarnUnimpl::ll();
format LoadMemory {
- 0x1: lwc1({{ Ft<31:0> = Mem.sf; }});
- 0x5: ldc1({{ Ft<63:0> = Mem.df; }});
+ 0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}});
+ 0x5: ldc1({{ /*F_t<63:0> = Mem.df; */}});
}
}
+
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
0x0: WarnUnimpl::sc();
format StoreMemory {
- 0x1: swc1({{ Mem.sf = Ft<31:0>; }});
- 0x5: sdc1({{ Mem.df = Ft<63:0>; }});
+ 0x1: swc1({{ //Mem.sf = Ft<31:0>; }});
+ 0x5: sdc1({{ //Mem.df = Ft<63:0>; }});
}
-
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 14:54:39 +0000