9 files changed, 166 insertions, 56 deletions
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index 0d2ad7855..8cfa37a20 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -179,7 +179,7 @@ output decoder {{
             ss << ",";
         }
 
-        Addr target = pc + 8 + disp;
+        Addr target = pc + 4 + disp;
 
         std::string str;
         if (symtab && symtab->findSymbol(target, str))
@@ -187,6 +187,12 @@ output decoder {{
         else
             ccprintf(ss, "0x%x", target);
 
+        string inst_name = mnemonic;
+
+        if (inst_name.substr(inst_name.length()-2,inst_name.length()) == "al"){
+            ccprintf(ss, " (r31=0x%x)",pc+8);
+        }
+
         return ss.str();
     }
 
@@ -255,7 +261,7 @@ def format Branch(code,*flags) {{
     #Add Link Code if Link instruction
     strlen = len(name)
     if name[strlen-2:] == 'al':
-        code += 'r31 = NNPC;\n'
+        code += 'R31 = NNPC;\n'
 
     #Condition code
     code = 'bool cond;\n' + code
@@ -265,8 +271,6 @@ def format Branch(code,*flags) {{
     code += '  NNPC = NNPC;\n'
     code += '} \n'
 
-    code += 'cout << hex << "NPC: " << NPC << " + " << disp << " = " << NNPC << endl;'
-
     iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
                         ('IsDirectControl', 'IsCondControl'))
 
@@ -281,7 +285,7 @@ def format BranchLikely(code,*flags) {{
     #Add Link Code if Link instruction
     strlen = len(name)
     if name[strlen-3:] == 'all':
-        code += 'r31 = NNPC;\n'
+        code += 'R31 = NNPC;\n'
 
     #Condition code
     code = 'bool cond;\n' + code
@@ -303,10 +307,8 @@ def format Jump(code,*flags) {{
     #Add Link Code if Link instruction
     strlen = len(name)
     if strlen > 1 and name[1:] == 'al':
-            code = 'r31 = NNPC;\n' + code
+            code = 'R31 = NNPC;\n' + code
 
-    #code += 'if(NNPC == 0x80000638) { NNPC = r31; cout << "SKIPPING JUMP TO SIM_GET_MEM_CONF" << endl;}'
-    #code += 'target = NNPC;'
 
     iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
                         ('IsIndirectControl', 'IsUncondControl'))
diff --git a/arch/mips/isa/formats/formats.isa b/arch/mips/isa/formats/formats.isa
new file mode 100644
index 000000000..7d493ffae
--- /dev/null
+++ b/arch/mips/isa/formats/formats.isa
@@ -0,0 +1,35 @@
+// -*- mode:c++ -*-
+
+//Templates from this format are used later
+//Include the basic format
+##include "basic.isa"
+
+//Include the basic format
+##include "noop.isa"
+
+//Include utility functions
+##include "util.isa"
+
+//Include the cop0 formats
+##include "cop0.isa"
+
+//Include the integer formats
+##include "int.isa"
+
+//Include the floatOp format
+##include "fp.isa"
+
+//Include the mem format
+##include "mem.isa"
+
+//Include the trap format
+##include "trap.isa"
+
+//Include the branch format
+##include "branch.isa"
+
+//Include the noop format
+##include "unimp.isa"
+
+//Include the noop format
+##include "unknown.isa"
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index 34b71acf7..9f2c24755 100644
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -30,7 +30,7 @@ output decoder {{
 }};
 
 
-// Primary format for integer operate instructions:
+// Primary format for float operate instructions:
 def format FloatOp(code, *flags) {{
         iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
@@ -39,7 +39,35 @@ def format FloatOp(code, *flags) {{
         exec_output = BasicExecute.subst(iop)
 }};
 
-// Primary format for integer operate instructions:
+def format FloatCompareOp(code, *flags) {{
+        code = 'bool cond;\n' + code
+        code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+def format FloatCompareWithXcptOp(code, *flags) {{
+        code = 'bool cond;\n' + code
+        code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+def format FloatConvertOp(code, *flags) {{
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+// Primary format for float64 operate instructions:
 def format Float64Op(code, *flags) {{
         iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
@@ -47,3 +75,35 @@ def format Float64Op(code, *flags) {{
         decode_block = BasicDecode.subst(iop)
         exec_output = BasicExecute.subst(iop)
 }};
+
+def format Float64ConvertOp(code, *flags) {{
+        code = 'bool cond;\n' + code
+        code += 'FCSR = makeCCVector(FCSR, CC,cond);\n'
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+def format FloatPSCompareOp(code, *flags) {{
+        code = 'bool cond1;\nbool cond2;\n' + code
+        code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n'
+        code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n'
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+def format FloatPSCompareWithXcptOp(code, *flags) {{
+        code = 'bool cond1;\nbool cond2;\n' + code
+        code += 'FCSR = makeCCVector(FCSR, CC+1, cond1);\n'
+        code += 'FCSR = makeCCVector(FCSR, CC, cond2);\n'
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index a47844bee..7d38b9ff5 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -29,17 +29,19 @@ output header {{
         {
                 protected:
 
-                int32_t imm;
+                int16_t imm;
+                int32_t sextImm;
+                uint32_t zextImm;
 
                 /// Constructor
                 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                                MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
+                    MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
+                    sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
                 {
                     //If Bit 15 is 1 then Sign Extend
-                    int32_t temp = imm & 0x00008000;
-
+                    int32_t temp = sextImm & 0x00008000;
                     if (temp > 0 && mnemonic != "lui") {
-                        imm |= 0xFFFF0000;
+                        sextImm |= 0xFFFF0000;
                     }
                 }
 
@@ -62,10 +64,9 @@ output decoder {{
             // it's generally implicit
             if (_numDestRegs > 0) {
                 printReg(ss, _destRegIdx[0]);
+                ss << ",";
             }
 
-            ss << ",";
-
             // just print the first two source regs... if there's
             // a third one, it's a read-modify-write dest (Rc),
             // e.g. for CMOVxx
@@ -99,9 +100,9 @@ output decoder {{
             }
 
             if( mnemonic == "lui")
-                ccprintf(ss, "%08p ", imm);
+                ccprintf(ss, "%08p ", sextImm);
             else
-                ss << (int) imm;
+                ss << (int) sextImm;
 
             return ss.str();
         }
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index 8a07e63d4..e2afc7252 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -276,8 +276,7 @@ def template LoadCompleteAcc {{
         Fault fault = NoFault;
 
         %(fp_enable_check)s;
-        %(op_src_decl)s;
-        %(op_dest_decl)s;
+        %(op_decl)s;
 
         memcpy(&Mem, data, sizeof(Mem));
 
@@ -375,8 +374,7 @@ def template StoreInitiateAcc {{
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
-        %(op_src_decl)s;
-        %(op_dest_decl)s;
+        %(op_decl)s;
         %(op_rd)s;
         %(ea_code)s;
 
@@ -449,21 +447,27 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
 }};
 
 //FP loads are offloaded to these formats for now ...
-def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }},
-                      mem_flags = [], inst_flags = []) {{
+def format LoadFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
+                     mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                      decode_template = LoadNopCheckDecode,
+                      decode_template = BasicDecode,
                       exec_template_base = 'Load')
 }};
 
 
-//FP stores are offloaded to these formats for now ...
-def format StoreMemory2(ea_code = {{ EA = Rs + disp; }},memacc_code = {{ }},
-                      mem_flags = [], inst_flags = []) {{
+def format StoreFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
+                     mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                      decode_template = LoadNopCheckDecode,
                       exec_template_base = 'Store')
 }};
 
+
+def format UnalignedStore(memacc_code, postacc_code,
+                     ea_code = {{ EA = Rb + disp; }},
+                     mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      postacc_code, exec_template_base = 'Store')
+}};
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index d35179005..2aa4816e3 100644
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -88,3 +88,7 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
     exec_output = BasicExecute.subst(iop)
 }};
 
+def format Nop() {{
+        decode_block = 'return new Nop(\"sll r0,r0,0\",machInst);\n'
+}};
+
diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa
index adbd5b5b1..475a88752 100644
--- a/arch/mips/isa/formats/unimp.isa
+++ b/arch/mips/isa/formats/unimp.isa
@@ -110,8 +110,9 @@ output exec {{
                                Trace::InstRecord *traceData) const
     {
         panic("attempt to execute unimplemented instruction '%s' "
-              "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
-        return UnimplementedOpcodeFault;
+              "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+              inst2string(machInst));
+        return new UnimplementedOpcodeFault;
     }
 
     Fault
diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa
index 4601b3684..ba83c007e 100644
--- a/arch/mips/isa/formats/unknown.isa
+++ b/arch/mips/isa/formats/unknown.isa
@@ -26,12 +26,34 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+output header {{
+        std::string inst2string(MachInst machInst);
+}};
 output decoder {{
+
+std::string inst2string(MachInst machInst)
+{
+    string str = "";
+    uint32_t mask = 0x80000000;
+
+    for(int i=0; i < 32; i++) {
+        if ((machInst & mask) == 0) {
+            str += "0";
+        } else {
+            str += "1";
+        }
+
+        mask = mask >> 1;
+    }
+
+    return str;
+}
+
     std::string
     Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
-        return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
-                        "unknown", machInst, OPCODE);
+        return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
+                        "unknown", machInst, OPCODE, inst2string(machInst));
     }
 }};
 
@@ -41,8 +63,8 @@ output exec {{
                      Trace::InstRecord *traceData) const
     {
         panic("attempt to execute unknown instruction "
-              "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
-        return UnimplementedOpcodeFault;
+              "(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst));
+        return new UnimplementedOpcodeFault;
     }
 }};
 
diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
index db4bf204a..615160931 100644
--- a/arch/mips/isa/formats/util.isa
+++ b/arch/mips/isa/formats/util.isa
@@ -93,8 +93,7 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 
 output exec {{
 
-using namespace MipsISA;
-
+    using namespace MipsISA;
 
     /// CLEAR ALL CPU INST/EXE HAZARDS
     inline void
@@ -124,25 +123,7 @@ using namespace MipsISA;
     }
 #endif
 
-    double convert_and_round(float w, int x, int y, int z)
-    {
-        double temp = .34000;
-
-        return temp;
-    }
 
-    enum FPTypes{
-        FP_SINGLE,
-        FP_DOUBLE,
-        FP_LONG,
-        FP_PS_LO,
-        FP_PS_HI,
-        FP_WORD,
-        RND_NEAREST,
-        RND_ZERO,
-        RND_UP,
-        RND_DOWN
-    };
 }};